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Part Number 74ABT16501CSSCX
Manufacturer Fairchild/ON Semiconductor
Datasheet 74ABT16501CSSCX Datasheet
Package 56-BSSOP (0.295", 7.50mm Width)
In Stock 402 piece(s)
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Part Number # 74ABT16501CSSCX (Logic - Universal Bus Functions) is manufactured by Fairchild/ON Semiconductor and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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74ABT16501CSSCX Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Universal Bus Functions
Datasheet 74ABT16501CSSCXDatasheet
Package56-BSSOP (0.295", 7.50mm Width)
Logic TypeUniversal Bus Transceiver
Number of Circuits18-Bit
Current - Output High, Low3mA, 64mA
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case56-BSSOP (0.295", 7.50mm Width)
Supplier Device Package56-SSOP

74ABT16501CSSCX Datasheet

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January 1995 Revised January 1999 7 4 A B T 1 6 5 0 1 1 8 -B it U n iv e rs a l B u s T ra n s c e iv e rs w ith 3 -S T A T E O u tp u ts © 1999 Fairchild Semiconductor Corporation DS011690.prf 74ABT16501 18-Bit Universal Bus Transceivers with 3-STATE Outputs General Description The ABT16501 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. Output-enable OEAB is active-high. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are com- plementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OE inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Features ■ Combines D-Type latches and D-Type flip-flops for oper- ation in transparent, latched, or clocked mode ■ Flow-through architecture optimizes PCB layout ■ Guaranteed latch-up protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Non-destructive hot insertion capability Ordering Code: Devices also available in Tape or Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignment for SSOP Function Table (Note 1) Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2: Output level before the indicated steady-state input conditions were established. Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Order Number Package Number Package Description 74ABT16501CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16501CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Inputs Output OEAB LEAB CLKAB A B L X X X Z H H X L L H H X H H H L ↑ L L H L ↑ H H H L H X B0 (Note 2) H L L X B0 (Note 3)

Page 3 2 7 4 A B T 1 6 5 0 1 Logic Diagram

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3 7 4 A B T 1 6 5 0 1 Absolute Maximum Ratings(Note 4) Recommended Operating Conditions Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Note 6: Guaranteed, but not tested. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 5) −0.5V to +7.0V Input Current (Note 5) −30 mA to +5.0 mA Voltage Applied to Any Output in the Disabled or Power-off State −0.5V to 5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Latchup Source Current −500 mA Over Voltage Latchup (I/O) 10V Free Air Ambient Temperature −40°C to +85°C Supply Voltage +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH Voltage 2.5 V Min IOH = −3 mA 2.0 V Min IOH = −32 mA VOL Output LOW Voltage 0.55 V Min IOL = 64 mA IIH Input HIGH Current 1 µA Max VIN = 2.7V (Note 6) 1 VIN = VCC IBVI Input HIGH Current Breakdown Test 7 µA Max VIN = 7.0V IIL Input LOW Current −1 µA Max VIN = 0.5V (Note 6) −1 VIN = 0.0V VID Input Leakage Test 4.75 V 0.0 IID = 1.9 µA All Other Pins Grounded IIH + Output Leakage Current 10 µA 0 − 5.5V VOUT = 2.7V; OE, OE = 2.0V IOZH IIL + Output Leakage Current −10 µA 0 − 5.5V VOUT = 0.5V; OE, OE = 2.0V IOZL IOS Output Short-Circuit Current −100 −275 mA Max VOUT = 0V ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 1.0 mA Max All Outputs HIGH ICCL Power Supply Current 68 mA Max An or Bn Outputs LOW ICCZ Power Supply Current 1.0 mA Max OEn = VCC, All Others at VCC or GND ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ Max Outputs Open (Note 6) 0.23 MHz Transparent Mode One Bit Toggling, 50% Duty Cycle

Page 5 4 7 4 A B T 1 6 5 0 1 DC Electrical Characteristics Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 8: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 9: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. AC Electrical Characteristics AC Operating Requirements Symbol Parameter Min Typ Max Units VCC Conditions CL = 50 pF; RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 0.7 1.2 V 5.0 TA = 25°C (Note 7) VOLV Quiet Output Minimum Dynamic VOL −1.5 −1.0 V 5.0 TA = 25°C (Note 7) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 8) VIHD Minimum HIGH Level Dynamic Input Voltage 2.2 1.8 V 5.0 TA = 25°C (Note 9) VILD Maximum LOW Level Dynamic Input Voltage 1.2 0.8 V 5.0 TA = 25°C (Note 9) Symbol Parameter TA = +25°C TA = −40°C to +85°C Units VCC = +5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Typ Max Min Max fmax Maximum Clock Frequency 150 200 150 MHz tPLH Propagation Delay 1.0 2.7 4.6 1.0 4.6 ns tPHL A or B to B or A 1.0 3.2 4.6 1.0 4.6 tPLH Propagation Delay 1.0 3.1 5.0 1.0 5.0 ns tPHL LEAB or LEBA to B or A 1.0 3.6 5.5 1.0 5.5 tPLH Propagation Delay 1.0 3.4 5.3 1.0 5.3 ns tPHL CLKAB or CLKBA to B or A 1.0 3.7 5.3 1.0 5.3 tPZH Propagation Delay 1.5 2.7 5.6 1.5 5.6 ns tPZL OEAB or OEBA to B or A 1.5 3.0 5.6 1.5 5.6 tPHZ Propagation Delay 1.5 3.7 6.0 1.5 6.0 ns tPLZ OEAB or OEBA to B or A 1.5 3.2 6.0 1.5 6.0 Symbol Parameter TA = +25°C TA = −40°C to +85°C Units VCC = +5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Max Min Max tS(H) Setup Time, 4.0 4.0 ns tS(L) A to CLKAB, B to CLKBA 4.0 4.0 tH(H) Hold Time, 0 0 ns tH(L) A to CLKAB, B to CLKBA 0 0 tS(H) Setup Time, A to LEAB 4.0 4.0 ns tS(L) or B to LEBA, CLK HIGH 4.0 4.0 tH(H) Hold Time, A to LEAB 1.5 1.5 ns tH(L) or B to LEBA, CLK HIGH 1.5 1.5 tS(H) Setup Time, A to LEAB 1.5 1.5 ns ts(L) or B to LEBA, CLK LOW 1.5 1.5 tH(H) Hold Time, A to LEAB 1.5 1.5 ns tH(L) or B to LEBA, CLK LOW 1.5 1.5 tW(H) Pulse Width, 3.3 3.3 ns tW(L) LEAB or LEBA, HIGH 3.3 3.3 tW(H) Pulse Width, CLKAB 3.3 3.3 ns tW(L) or CLKBA, HIGH or LOW 3.3 3.3

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5 7 4 A B T 1 6 5 0 1 Capacitance Note 10: CI/O is measured at frequency f = 1 MHz per MIL-STD-883, Method 3012. AC Loading *Includes jig and probe capacitance. FIGURE 1. Standard AC Test Load FIGURE 2. VM = 1.5V Input Pulse Requirements FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5.0 pF VCC = 0.0V CI/O (Note 10) Output Capacitance 11.0 pF VCC = 5.0V Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

Page 7 6 7 4 A B T 1 6 5 0 1 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A

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