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74ABT374CMTCX

74ABT374CMTCX

74ABT374CMTCX

For Reference Only

Part Number 74ABT374CMTCX
Manufacturer Fairchild/ON Semiconductor
Description IC D-TYPE POS TRG SNGL 20TSSOP
Datasheet 74ABT374CMTCX Datasheet
Package 20-TSSOP (0.173", 4.40mm Width)
In Stock 370 piece(s)
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74ABT374CMTCX Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Flip Flops
Datasheet 74ABT374CMTCX Datasheet
Package20-TSSOP (0.173", 4.40mm Width)
Series74ABT
FunctionStandard
TypeD-Type
Output TypeTri-State, Non-Inverted
Number of Elements1
Number of Bits per Element8
Clock Frequency200MHz
Max Propagation Delay @ V, Max CL5ns @ 5V, 50pF
Trigger TypePositive Edge
Current - Output High, Low32mA, 64mA
Voltage - Supply4.5 V ~ 5.5 V
Current - Quiescent50µA
Input Capacitance5pF
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case20-TSSOP (0.173", 4.40mm Width)

74ABT374CMTCX Datasheet

Page 1

Page 2

7 4 A B T 3 7 4 — O c ta l D -T y p e F lip -F lo p w ith 3 -S T A T E O u tp u ts ©1 74A December 2007 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs Features ■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ 3-STATE outputs for bus-oriented applications ■ Output sink capability of 64mA, source capability of 32mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50pF and 250pF loads ■ Guaranteed simultaneous switching, noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High-impedance, glitch-free bus loading during entire power up and power down cycle ■ Nondestructive, hot-insertion capability General Description The ABT374 is an octal D-type flip-flop featuring sepa- rate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. Ordering Information Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Package Number Package Description 74ABT374CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ABT374CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT374CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT374CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide992 Fairchild Semiconductor Corporation www.fairchildsemi.com BT374 Rev. 1.5.0

Page 3

©1 74A 7 4 A B T 3 7 4 — O c ta l D -T y p e F lip -F lo p w ith 3 -S T A T E O u tp u ts Connection Diagram Pin Descriptions Functional Description The ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are com- mon to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the con- tents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flip-flops. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input (Active Rising Edge) OE 3-STATE Output Enable Input (Active LOW) O0–O7 3-STATE Outputs Inputs Internal Outputs FunctionOE CP D Q O H H L NC Z Hold H H H NC Z Hold H L L Z Load H H H Z Load L L L L Data Available L H H H Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data992 Fairchild Semiconductor Corporation www.fairchildsemi.com BT374 Rev. 1.5.0 2

Page 4

©1 74A 7 4 A B T 3 7 4 — O c ta l D -T y p e F lip -F lo p w ith 3 -S T A T E O u tp u ts Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Note: 1. Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Rating TSTG Storage Temperature –65°C to +150°C TA Ambient Temperature Under Bias –55°C to +125°C TJ Junction Temperature Under Bias –55°C to +150°C VCC VCC Pin Potential to Ground Pin –0.5V to +7.0V VIN Input Voltage (1) –0.5V to +7.0V IIN Input Current (1) –30mA to +5.0mA VO Voltage Applied to Any Output Disabled or Power-Off State HIGH State –0.5V to 5.5V –0.5V to VCC Current Applied to Output in LOW State (Max.) twice the rated IOL (mA) DC Latchup Source Current Across Common Operating Range OE Pin Other Pins –150mA –500mA Over Voltage Latchup (I/O) 10V Symbol Parameter Rating TA Free Air Ambient Temperature –40°C to +85°C VCC Supply Voltage +4.5V to +5.5V ∆V / ∆t Minimum Input Edge Rate Data Input Enable Input Clock Input 50mV/ns 20mV/ns 100mV/ns992 Fairchild Semiconductor Corporation www.fairchildsemi.com BT374 Rev. 1.5.0 3

Page 5

©1 74A 7 4 A B T 3 7 4 — O c ta l D -T y p e F lip -F lo p w ith 3 -S T A T E O u tp u ts DC Electrical Characteristics Notes: 2. For 8-bit toggling, ICCD < 0.8mA/MHz. 3. Guaranteed, but not tested. Symbol Parameter VCC Conditions Min. Typ. Max. Units VIH Input HIGH Voltage Recognized HIGH Signal 2.0 V VIL Input LOW Voltage Recognized LOW Signal 0.8 V VCD Input Clamp Diode Voltage Min. IIN = –18mA –1.2 V VOH Output HIGH Voltage Min. IOH = –3mA 2.5 V IOH = –32mA 2.0 VOL Output LOW Voltage Min. IOL = 64mA 0.55 V IIH Input HIGH Current Max. VIN = 2.7V(3) 1 µA VIN = VCC 1 IBVI Input HIGH Current Breakdown Test Max. VIN = 7.0V 7 µA IIL Input LOW Current Max. VIN = 0.5V(3) –1 µA VIN = 0.0V –1 VID Input Leakage Test 0.0 IID = 1.9µA, All Other Pins Grounded 4.75 V IOZH Output Leakage Current 0–5.5V VOUT = 2.7V, OE = 2.0V 10 µA IOZL Output Leakage Current 0–5.5V VOUT = 0.5V, OE = 2.0V –10 µA IOS Output Short-Circuit Current Max. VOUT = 0.0V –100 –275 mA ICEX Output HIGH Leakage Current Max. VOUT = VCC 50 µA IZZ Bus Drainage Test 0.0 VOUT = 5.5V, All Others VCC or GND 100 µA ICCH Power Supply Current Max. All Outputs HIGH 50 µA ICCL Power Supply Current Max. All Outputs LOW 30 mA ICCZ Power Supply Current Max. OE = VCC, All Others at VCC or GND 50 µA ICCT Additional ICC/Input Outputs Enabled Max. VI = VCC – 2.1V 2.5 mA Outputs 3-STATE Enable Input VI = VCC – 2.1V 2.5 mA Outputs 3-STATE Data Input VI = VCC – 2.1V, All Others at VCC or GND 2.5 mA ICCD Dynamic ICC No Load (4) Max. Outputs OPEN, OE = GND(2), One-Bit Toggling, 50% Duty Cycle 0.30 mA/ MHz992 Fairchild Semiconductor Corporation www.fairchildsemi.com BT374 Rev. 1.5.0 4

Page 6

©1 74A 7 4 A B T 3 7 4 — O c ta l D -T y p e F lip -F lo p w ith 3 -S T A T E O u tp u tsDC Electrical Characteristics SOIC package. Notes: 4. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. 5. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. 6. Max number of data inputs (n) switching. n – 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. AC Electrical Characteristics SOIC and SSOP package. Symbol Parameter VCC Conditions CL = 50pF, RL = 500Ω Min. Typ. Max. Units VOLP Quiet Output Maximum Dynamic VOL 5.0 TA = 25°C(4) 0.5 0.8 V VOLV Quiet Output Minimum Dynamic VOL 5.0 TA = 25°C(4) –1.3 –0.9 V VOHV Minimum HIGH Level Dynamic Output Voltage 5.0 TA = 25°C(5) 2.5 3.0 V VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 TA = 25°C(6) 2.0 1.6 V VILD Maximum LOW Level Dynamic Input Voltage 5.0 TA = 25°C(6) 1.3 0.8 V Symbol Parameter TA = +25°C, VCC = +5V, CL = 50pF TA = –55°C to +125°C, VCC = 4.5V to 5.5V, CL = 50pF TA = –40°C to +85°C, VCC = 4.5V to 5.5V, CL = 50pF UnitsMin. Typ. Max. Min. Max. Min. Max. fMAX Maximum Clock Frequency 150 200 150 150 MHz tPLH Propagation Delay CP to On 2.0 3.2 5.0 1.4 6.6 2.0 5.0 ns tPHL 2.0 3.3 5.0 2.0 7.6 2.0 5.0 tPZH Output Enable Time 1.5 3.1 5.3 0.8 5.7 1.5 5.3 ns tPZL 1.5 3.1 5.3 1.5 7.2 1.5 5.3 tPHZ Output Disable Time 1.5 3.6 5.4 1.3 7.2 1.5 5.4 ns tPLZ 1.5 3.4 5.4 1.0 7.0 1.5 5.4992 Fairchild Semiconductor Corporation www.fairchildsemi.com BT374 Rev. 1.5.0 5

Page 7

©1 74A 7 4 A B T 3 7 4 — O c ta l D -T y p e F lip -F lo p w ith 3 -S T A T E O u tp u tsAC Operating Requirements Extended AC Electrical Characteristics SOIC package. Notes: 7. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). 8. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching only. 9. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 10. The 3-STATE delay Time is dominated by the RC network (500Ω, 250pF) on the output and has been excluded from the datasheet. Symbol Parameter TA = +25°C VCC = +5.0V CL = 50pF TA = –55°C to +125°C VCC = 4.5V to 5.5V CL = 50pF TA = –40°C to +85°C VCC = 4.5V to 5.5V CL = 50pF Units Min. Max. Min. Max. Min. Max. tS(H) Setup Time, HIGH or LOW Dn to CP 1.5 2.5 1.0 ns tS(L) 1.5 2.5 1.5 tH(H) Hold Time, HIGH or LOW Dn to CP 1.0 2.5 1.0 ns tH(L) 1.0 2.5 1.0 tW(H) Pulse Width, CP HIGH or LOW 3.0 3.3 3.0 ns tW(L) 3.0 3.3 3.0 Symbol Parameter TA = –40°C to +85°C, VCC = 4.5V to 5.5V, CL = 50pF, 8 Outputs Switching(7) TA = –40°C to +85°C, VCC = 4.5V to 5.5V, CL = 250pF(8) TA = –40°C to +85°C, VCC = 4.5V to 5.5V, CL = 250pF, 8 Outputs Switching(9) Units Min Max Min Max Min Max tPLH Propagation Delay CP to On 1.5 5.7 2.0 7.8 2.0 10.0 ns tPHL 1.5 5.7 2.0 7.8 2.0 10.0 tPZH Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5 ns tPZL 1.5 6.2 2.0 8.0 2.0 10.5 tPHZ Output Disable Time 1.0 5.5 (10) (10) ns tPZL 1.0 5.5992 Fairchild Semiconductor Corporation www.fairchildsemi.com BT374 Rev. 1.5.0 6

Page 8

©1 74A 7 4 A B T 3 7 4 — O c ta l D -T y p e F lip -F lo p w ith 3 -S T A T E O u tp u tsSkew(15) SOIC package. Notes: 11. This specification is guaranteed but not tested. The limits represent propagation delays with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 12. This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. 13. Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST). This specification is guaranteed but not tested. 14. Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. 15. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Capacitance Note: 16. COUT is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. Symbol Parameter TA = –40°C to +85°C VCC = 4.5V–5.5V CL = 50 pF 8 Outputs Switching(11) TA = –40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF 8 Outputs Switching(12) Units Max. Max. tOSHL (13) Pin to Pin Skew, HL Transitions 1.0 1.8 ns tOSLH (13) Pin to Pin Skew, LH Transitions 1.0 1.8 ns tPS (12) Duty Cycle, LH–HL Skew 1.8 4.3 ns tOST (13) Pin to Pin Skew, LH/HL Transitions 2.0 4.3 ns tPV (14) Device to Device Skew, LH/HL Transitions 2.5 4.6 ns Symbol Parameter Conditions TA = 25°C Typ. Units CIN Input Capacitance VCC = 0V 5.0 pF COUT (16) Output Capacitance VCC = 5.0V 9.0 pF992 Fairchild Semiconductor Corporation www.fairchildsemi.com BT374 Rev. 1.5.0 7

Page 9

©1 74A 7 4 A B T 3 7 4 — O c ta l D -T y p e F lip -F lo p w ith 3 -S T A T E O u tp u tsAC Loading *Includes jig and probe capacitance Figure 1. Standard AC Test Load Figure 2. VM = 1.5V Input Pulse Requirements Figure 3. Test Input Signal Requirements AC Waveforms Figure 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions Figure 5. Propagation Delay, Pulse Width Waveforms Figure 6. 3-STATE Output HIGH and LOW Enable and Disable Times Figure 7. Setup Time, Hold Time and Recovery Time Waveforms Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500ns 2.5ns 2.5ns992 Fairchild Semiconductor Corporation www.fairchildsemi.com BT374 Rev. 1.5.0 8

Page 10

©1 74A 7 4 A B T 3 7 4 — O c ta l D -T y p e F lip -F lo p w ith 3 -S T A T E O u tp u tsPhysical Dimensions Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ 0.10 C C A SEE DETAIL A NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. E) LANDPATTERN STANDARD: SOIC127P1030X265-20L PIN ONE INDICATOR 0.25 1 10 BC AM 20 11 B X 45° 8° 0° SEATING PLANE GAGE PLANE DETAIL A SCALE: 2:1 SEATING PLANE LAND PATTERN RECOMMENDATION F) DRAWING FILENAME: MKT-M20BREV3 0.65 1.27 2.25 9.50 13.00 12.60 11.43 7.60 7.40 10.65 10.00 0.51 0.35 1.27 2.65 MAX 0.30 0.10 0.33 0.20 0.75 0.25 (R0.10) (R0.10) 1.27 0.40 (1.40) 0.25 D) CONFORMS TO ASME Y14.5M-1994992 Fairchild Semiconductor Corporation www.fairchildsemi.com BT374 Rev. 1.5.0 9

74ABT374CMTCX Reviews

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Ashl*****uentes

February 19, 2020

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February 14, 2020

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December 7, 2019

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October 20, 2019

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October 12, 2019

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September 4, 2019

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