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74ABT899CSCX

74ABT899CSCX

74ABT899CSCX

For Reference Only

Part Number 74ABT899CSCX
Manufacturer ON Semiconductor
Description TXRX W/GENERATOR&CHECKER 28SOIC
Datasheet 74ABT899CSCX Datasheet
Package 28-SOIC (0.295", 7.50mm Width)
In Stock 354 piece(s)
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74ABT899CSCX Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Specialty Logic
Datasheet 74ABT899CSCX Datasheet
Package28-SOIC (0.295", 7.50mm Width)
Series74ABT
Logic TypeParity Generator/Checker
Supply Voltage4.5 V ~ 5.5 V
Number of Bits9
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case28-SOIC (0.295", 7.50mm Width)
Supplier Device Package28-SOIC

74ABT899CSCX Datasheet

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November 1992 Revised January 1999 7 4 A B T 8 9 9 9 -B it L a tc h a b le T ra n s c e iv e r w ith P a rity G e n e ra to r/C h e c k e r © 1999 Fairchild Semiconductor Corporation DS011509.prf www.fairchildsemi.com 74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description The ABT899 is a 9-bit to 9-bit parity transceiver with trans- parent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. The ABT899 features independent latch enables for the A- to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. Features ■ Latchable transceiver with output sink of 64 mA ■ Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A ■ Independent latch enables for A-to-B and B-to-A directions ■ Select pin for ODD/EVEN parity ■ ERRA and ERRB output pins for parity checking ■ Ability to simultaneously generate and check parity ■ May be used in systems applications in place of the 543 and 280 ■ May be used in system applications in place of the 657 and 373 (no need to change T/R to check parity) ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability ■ Disable time less than enable time to avoid bus contention Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for PLCC Pin Assignment for SOIC and SSOP Order Number Package Number Package Description 74ABT899CSC M28B 28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body 74ABT899CMSA MSA28 28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT899CQC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square

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www.fairchildsemi.com 2 7 4 A B T 8 9 9 Pin Descriptions Functional Description The ABT899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions. • Bus A (B) communicates to Bus B (A), parity is gener- ated and passed on to the B (A) Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL) is LOW, the parity generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA). • Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU). • Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function Table below). Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note 1: O/E = ODD/EVEN Pin Names Descriptions A0–A7 A Bus Data Inputs/Data Outputs B0–B7 B Bus Data Inputs/Data Outputs APAR, BPAR A and B Bus Parity Inputs/Outputs ODD/EVEN ODD/EVEN Parity Select, Active LOW for EVEN Parity GBA, GAB Output Enables for A or B Bus, Active LOW SEL Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode LEA, LEB Latch Enables for A and B Latches, HIGH for Transparent Mode ERRA, ERRB Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs Inputs Operation GAB GBA SEL LEA LEB H H X X X Busses A and B are 3-STATE. H L L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. H L L H H Generates parity from B[0:7] based on O/E. Generated parity → APAR. Gener- ated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. H L L X L Generates parity from B latch data based on O/E. Generated parity → APAR. Generated parity checked against latched BPAR and output as ERRB. H L H X H BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. H L H H H BPAR/B[0:7] → APAR/A[0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. L H L H L Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Gener- ated parity checked against APAR and output as ERRA. L H L H H Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Gener- ated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. L H L L X Generates parity from A latch data based on O/E. Generated parity → BPAR. Generated parity checked against latched APAR and output as ERRA. L H H H L APAR/A[0:7] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. L H H H H APAR/A[0:7] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB.

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3 www.fairchildsemi.com 7 4 A B T 8 9 9 Functional Block Diagram

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www.fairchildsemi.com 4 7 4 A B T 8 9 9 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Note 4: Guaranteed, but not tested. Note 5: Add 3.75 mA for each ERR LOW. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias Plastic −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Any Output in the Disable or Power- Off State −0.5V to +5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Latchup Source Current −500 mA Over Voltage Latchup (I/O) 10V Free Air Ambient Temperature −40°C to +85°C Supply Voltage +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins) VOH Output HIGH 2.5 V Min IOH = −3 mA, (An, Bn, APAR, BPAR) Voltage 2.0 IOH = −32 mA, (An, Bn, APAR, BPAR) VOL Output LOW Voltage 0.55 V Min IOL = 64 mA, (An, Bn, APAR, BPAR) VID Input Leakage Test 4.75 V 0.0 IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded IIH Input HIGH Current 5 µA Max VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) IBVI Input HIGH Current 7 µA Max VIN = 7.0V (Non-I/O Pins) Breakdown Test IBVIT Input HIGH Current 100 µA Max VIN = 5.5V (An, Bn, APAR, BPAR) Breakdown Test (I/O) IIL Input LOW Current −5 µA Max VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) IIH + IOZH Output Leakage Current 50 µA 0V–5.5V VOUT = 2.7V (An, Bn); GAB and GBA = 2.0V IIL + IOZL Output Leakage Current −50 µA 0V–5.5V VOUT = 0.5V (An, Bn); GAB and GBA = 2.0V IOS Output Short-Circuit Current −100 −275 mA Max VOUT = 0V (An, Bn, APAR, BPAR) ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC (An, Bn, APAR, BPAR) IZZ Bus Drainage Test 100 µA 0.0V VOUT = 5.5V (An, Bn, APAR, BPAR); All Others GND ICCH Power Supply Current 250 µA Max All Outputs HIGH ICCL Power Supply Current 34 mA Max All Outputs LOW, ERRA/B = HIGH (Note 5) ICCZ Power Supply Current 250 µA Max Outputs 3-STATE All Others at VCC or GND ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC: No Load 0.4 mA/MHz Max Outputs Open (Note 4) GAB or GBA = GND, LE = HIGH Non-I/O = GND or VCC One bit toggling, 50% duty cycle

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5 www.fairchildsemi.com 7 4 A B T 8 9 9 DC Electrical Characteristics (PLCC package) Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 8: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics (SOIC and PLCC Package) Symbol Parameter Min Typ Max Units VCC Conditions CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 0.8 1.1 V 5.0 TA = 25°C (Note 6) VOLV Quiet Output Minimum Dynamic VOL −1.3 −0.8 V 5.0 TA = 25°C (Note 6) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 8) VIHD Minimum HIGH Level Dynamic Input Voltage 2.2 1.8 V 5.0 TA = 25°C (Note 7) VILD Maximum LOW Level Dynamic Input Voltage 0.8 0.5 V 5.0 TA = 25°C (Note 7) Symbol Parameter TA = +25°C TA = −40°C to +85°C Units VCC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 1.5 3.0 4.8 1.5 4.8 ns tPHL An, to Bn 1.5 3.5 4.8 1.5 4.8 tPLH Propagation Delay 2.5 5.9 9.2 2.5 9.2 ns tPHL An, Bn to BPAR, APAR 2.5 5.8 9.2 2.5 9.2 tPLH Propagation Delay 2.5 5.4 8.5 2.5 8.5 ns tPHL An, Bn to ERRA, ERRB 2.5 5.4 8.5 2.5 8.5 tPLH Propagation Delay 1.5 3.7 6.0 1.5 6.0 ns tPHL APAR, BPAR to ERRA, ERRB 1.5 3.7 6.0 1.5 6.0 tPLH Propagation Delay 2.0 4.4 6.9 2.0 6.9 ns tPHL ODD/EVEN to APAR, BPAR 2.0 4.4 6.9 2.0 6.9 tPLH Propagation Delay 1.8 4.0 6.0 1.8 6.0 ns tPHL ODD/EVEN to ERRA, ERRB 1.8 4.0 6.0 1.8 6.0 tPLH Propagation Delay 1.5 3.8 6.0 1.5 6.0 ns tPHL SEL to APAR, BPAR 1.5 3.8 6.0 1.5 6.0 tPLH Propagation Delay 1.5 3.2 4.6 1.5 4.6 ns tPHL LEA, LEB to Bn, An 1.5 3.2 4.6 1.5 4.6 tPLH Propagation Delay 2.5 5.9 8.8 2.5 8.8 nstPHL LEA, LEB to BPAR, APAR 2.5 5.7 8.8 2.5 8.8 Generate Mode tPLH Propagation Delay 1.5 3.6 5.1 1.5 5.1 ns tPHL LEA, LEB to BPAR, APAR, 1.5 3.6 5.1 1.5 5.1 Feed Thru Mode tPLH Propagation Delay 1.6 5.4 8.4 1.6 8.4 ns tPHL LEA, LEB to ERRA, ERRB 1.6 5.4 8.4 1.6 8.4 tPZH Output Enable Time 1.5 3.6 6.0 1.5 6.0 ns tPZL GBA or GAB to An, 1.5 3.4 6.0 1.5 6.0 APAR or Bn, BPAR tPHZ Output Disable Time 1.0 4.0 6.0 1.0 6.0 ns tPLZ GBA or GAB to An, 1.0 3.3 6.0 1.0 6.0 APAR or Bn, BPAR tPLHtPHL Propagation Delay 1.5 3.3 5.4 1.5 5.4 ns APAR to BPAR, BPAR to APAR 1.5 3.8 5.4 1.5 5.4

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www.fairchildsemi.com 6 7 4 A B T 8 9 9 AC Electrical Characteristics (SSOP Package) AC Operating Requirements Symbol Parameter TA = +25°C TA = −40°C to +85°C Units VCC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 1.5 3.0 5.3 1.5 5.3 ns tPHL An, to Bn 1.5 3.5 5.3 1.5 5.3 tPLH Propagation Delay 2.5 5.9 9.9 2.5 9.9 ns tPHL An, Bn to BPAR, APAR 2.5 5.8 9.9 2.5 9.9 tPLH Propagation Delay 2.5 5.4 9.4 2.5 9.4 ns tPHL An, Bn to ERRA, ERRB 2.5 5.4 9.4 2.5 9.4 tPLH Propagation Delay 1.5 3.7 6.5 1.5 6.5 ns tPHL APAR, BPAR to ERRA, ERRB 1.5 3.7 6.5 1.5 6.5 tPLH Propagation Delay 2.0 4.4 7.4 2.0 7.4 ns tPHL ODD/EVEN to APAR, BPAR 2.0 4.4 7.4 2.0 7.4 tPLH Propagation Delay 1.8 4.0 6.5 1.8 6.5 ns tPHL ODD/EVEN to ERRA, ERRB 1.8 4.0 6.5 1.8 6.5 tPLH Propagation Delay 1.5 3.8 6.5 1.5 6.5 ns tPHL SEL to APAR, BPAR 1.5 3.8 6.5 1.5 6.5 tPLH Propagation Delay 1.5 3.2 5.1 1.5 5.1 ns tPHL LEA, LEB to Bn, An 1.5 3.2 5.1 1.5 5.1 tPLH Propagation Delay 2.5 5.9 9.2 2.5 9.2 nstPHL LEA, LEB to BPAR, APAR 2.5 5.7 9.2 2.5 9.2 Generate Mode tPLH Propagation Delay 1.5 3.6 5.6 1.5 5.6 ns tPHL LEA, LEB to BPAR, APAR, 1.5 3.6 5.6 1.5 5.6 Feed Thru Mode tPLH Propagation Delay 1.6 5.4 8.9 1.6 8.9 ns tPHL LEA, LEB to ERRA, ERRB 1.6 5.4 8.9 1.6 8.9 tPZH Output Enable Time 1.5 3.6 6.5 1.5 6.5 ns tPZL GBA or GAB to An, 1.5 3.4 6.5 1.5 6.5 APAR or Bn, BPAR tPHZ Output Disable Time 1.0 4.0 6.5 1.0 6.5 ns tPLZ GBA or GAB to An, 1.0 3.3 6.5 1.0 6.5 APAR or Bn, BPAR tPLH Propagation Delay 1.5 3.3 5.9 1.5 5.9 ns tPHL APAR to BPAR, BPAR to APAR 1.5 3.8 5.9 1.5 5.9 Symbol Parameter TA = +25°C TA = −40°C to +85°C Units VCC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Max Min Max tS(H) Setup Time, HIGH or LOW An, 1.5 1.5 ns tS(L) APAR to LEA or Bn, BPAR to LEB 1.5 1.5 tH(H) Hold Time, HIGH or LOW An, 1.0 1.0 ns tH(L) APAR to LEA or Bn, BPAR to LEB 1.0 1.0 tW(H) Pulse Width, HIGH 3.0 3.0 ns LEA or LEB

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7 www.fairchildsemi.com 7 4 A B T 8 9 9 Extended AC Electrical Characteristics (SOIC and PLCC Package) Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to- HIGH, HIGH-to-LOW, etc.). Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac- itors in the standard AC load. This specification pertains to single output switching only. Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to- HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load Note 12: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 13: Not applicable for multiple output switching. Symbol Parameter TA = +25°C TA = −40°C to +85°C TA = −40°C to +85°C Units VCC = +5.0V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 9 Outputs Switching 1 Output Switching 9 Outputs Switching (Note 9) (Note 10) (Note 11) Min Typ Max Min Max Min Max fTOGGLE Max Toggle Frequency 100 MHz tPLH Propagation Delay 1.5 6.2 2.0 7.2 2.5 9.5 ns tPHL An to Bn 1.5 6.2 2.0 7.2 2.5 9.5 tPLH Propagation Delay 1.5 6.8 2.0 8.0 2.5 10.0 ns tPHL APAR to BPAR 1.5 6.8 2.0 8.0 2.0 10.0 tPLH Propagation Delay 2.5 10.0 3.0 12.5 3.5 13.5 ns tPHL An, Bn to BPAR, APAR 2.5 10.0 3.0 12.5 3.5 13.5 tPLH Propagation Delay (Note 13) 3.0 12.0 (Note 13) ns tPHL An, Bn to ERRA, ERRB 3.0 12.0 tPLH Propagation Delay (Note 13) 2.0 9.0 (Note 13) ns tPHL APAR, BPAR to ERRA, ERRB 2.0 9.0 tPLH Propagation Delay (Note 13) 2.5 9.9 (Note 13) ns tPHL ODD/EVEN to APAR, BPAR 2.5 9.9 tPLH Propagation Delay (Note 13) 2.0 8.8 (Note 13) ns tPHL ODD/EVEN to ERRA, ERRB 2.0 8.8 tPLH Propagation Delay (Note 13) 2.0 9.5 (Note 13) ns tPHL SEL to APAR, BPAR 2.0 9.5 tPLH Propagation Delay 1.5 5.7 2.0 7.9 2.5 10.0 ns tPHL LEA, LEB to Bn, An 1.5 5.7 2.0 7.9 2.5 10.0 tPLH Propagation Delay 1.5 9.5 2.0 12.0 2.5 13.0 ns tPHL LEA, LEB to BPAR, APAR 1.5 9.5 2.0 12.0 2.5 13.0 tPLH Propagation Delay (Note 13) 2.0 11.5 (Note 13) ns tPHL LEA, LEB to ERRA, ERRB 2.0 11.5 tPZH Output enable time 1.5 7.0 2.0 8.5 2.5 10.5 tPZL GBA or GAB to An, 1.5 7.0 2.0 8.5 2.5 10.5 ns APAR or Bn, BPAR tPHZ Output disable time 1.0 6.5 tPLZ GBA or GAB to An, 1.0 6.5 (Note 12) (Note 12) ns APAR or Bn, BPAR

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www.fairchildsemi.com 8 7 4 A B T 8 9 9 Extended AC Electrical Characteristics (SSOP Package) Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to- HIGH, HIGH-to-LOW, etc.). Note 15: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac- itors in the standard AC load. This specification pertains to single output switching only. Note 16: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to- HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load Note 17: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 18: Not applicable for multiple output switching. Symbol Parameter TA = +25°C TA = −40°C to +85°C TA = −40°C to +85°C Units VCC = +5.0V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 9 Outputs Switching 1 Output Switching 9 Outputs Switching (Note 14) (Note 15) (Note 16) Min Typ Max Min Max Min Max fTOGGLE Max Toggle Frequency 100 MHz tPLH Propagation Delay 1.5 6.7 2.0 7.7 2.5 10.1 ns tPHL An to Bn 1.5 6.7 2.0 7.7 2.5 10.1 tPLH Propagation Delay 1.5 7.3 2.0 8.5 2.5 10.6 ns tPHL APAR to BPAR 1.5 7.3 2.0 8.5 2.0 10.6 tPLH Propagation Delay 2.5 10.7 3.0 13.2 3.5 14.3 ns tPHL An, Bn to BPAR, APAR 2.5 10.7 3.0 13.2 3.5 14.3 tPLH Propagation Delay (Note 18) 3.0 12.9 (Note 18) ns tPHL An, Bn to ERRA, ERRB 3.0 12.9 tPLH Propagation Delay (Note 18) 2.0 9.5 (Note 18) ns tPHL APAR, BPAR to ERRA, ERRB 2.0 9.5 tPLH Propagation Delay (Note 18) 2.5 10.4 (Note 18) ns tPHL ODD/EVEN to APAR, BPAR 2.5 10.4 tPLH Propagation Delay (Note 18) 2.0 9.3 (Note 18) ns tPHL ODD/EVEN to ERRA, ERRB 2.0 9.3 tPLH Propagation Delay (Note 18) 2.0 10.0 (Note 18) ns tPHL SEL to APAR, BPAR 2.0 10.0 tPLH Propagation Delay 1.5 6.2 2.0 8.4 2.5 10.6 ns tPHL LEA, LEB to Bn, An 1.5 6.2 2.0 8.4 2.5 10.6 tPLH Propagation Delay 1.5 10.0 2.0 12.5 2.5 13.6 ns tPHL LEA, LEB to BPAR, APAR 1.5 10.0 2.0 12.5 2.5 13.6 tPLH Propagation Delay (Note 18) 2.0 12.0 (Note 18) ns tPHL LEA, LEB to ERRA, ERRB 2.0 12.0 tPZH Output enable time 1.5 7.5 2.0 9.0 2.5 11.1 tPZL GBA or GAB to An, 1.5 7.5 2.0 9.0 2.5 11.1 ns APAR or Bn, BPAR tPHZ Output disable time 1.0 7.0 tPLZ GBA or GAB to An, 1.0 7.0 (Note 17) (Note 17) ns APAR or Bn, BPAR

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9 www.fairchildsemi.com 7 4 A B T 8 9 9 Skew (PLCC package) (Note 2) Note 19: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to- HIGH, HIGH-to-LOW, etc.). Note 20: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 21: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to LOW (tOST). This specification is guaranteed but not tested. Skew applies to propagation delays individually; i.e., An to Bn separate from LEA to An. Note 22: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 23: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Note 24: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012. Symbol Parameter TA = −40°C to +85°C TA = −40°C to +85°C Units VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 9 Outputs Switching 9 Outputs Switching (Note 19) (Note 20) Max Max tOSHL Pin to Pin Skew 1.0 2.0 ns (Note 21) HL Transitions tOSLH Pin to Pin Skew 1.1 2.1 ns (Note 21) LH Transitions tPS Duty Cycle 2.0 3.5 ns (Note 22) LH–HL Skew tOST Pin to Pin Skew 2.0 3.5 ns (Note 21) LH/HL Transitions tPV Device to Device Skew 3.0 4.0 ns (Note 23) LH/HL Transitions Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Pin Capacitance 5.0 pF VCC = 0V CI/O (Note 24) Output Capacitance 11.0 pF VCC = 5.0V

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