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74AC541SC

74AC541SC

74AC541SC

For Reference Only

Part Number 74AC541SC
Manufacturer ON Semiconductor
Description IC BUFFER NON-INVERT 6V 20SOIC
Datasheet 74AC541SC Datasheet
Package 20-SOIC (0.295", 7.50mm Width)
In Stock 2018 piece(s)
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74AC541SC Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74AC541SC Datasheet
Package20-SOIC (0.295", 7.50mm Width)
Series74AC
Logic TypeBuffer, Non-Inverting
Number of Elements1
Number of Bits per Element8
Output Type3-State
Current - Output High, Low24mA, 24mA
Voltage - Supply2 V ~ 6 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case20-SOIC (0.295", 7.50mm Width)
Supplier Device Package20-SOIC

74AC541SC Datasheet

Page 1

Page 2

To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. Is Now Part of ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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7 4 A C 5 4 1 , 7 4 A C T 5 4 1 — O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC541, 74ACT541 Rev. 1.5.0 January 2008 74AC541, 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs Features ■ I CC and I OZ reduced by 50% ■ 3-STATE outputs ■ Inputs and outputs opposite side of package, allowing easier interface to microprocessors ■ Output source/sink 24mA ■ 74AC541 is a non-inverting option of the 74AC540 ■ 74ACT541 has TTL-compatible inputs General Description The 74AC541 and 74ACT541 are octal buffer/line drivers designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/ receivers. These devices are similar in function to the 74AC244 and 74ACTC244 while providing flow-through architec- ture (inputs on opposite side from outputs). This pinout arrangement makes these devices especially useful as an output port for microprocessors, allowing ease of layout and greater PC board density. Ordering Information Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Package Number Package Description 74AC541SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74AC541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC541PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT541SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Page 4

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC541, 74ACT541 Rev. 1.5.0 2 7 4 A C 5 4 1 , 7 4 A C T 5 4 1 — O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Connection Diagram Logic Symbol IEEE/IEC Truth Table H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance Inputs OutputsOE 1 OE 2 I L L H H H X X Z X H X Z L L L L

Page 5

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC541, 74ACT541 Rev. 1.5.0 3 7 4 A C 5 4 1 , 7 4 A C T 5 4 1 — O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Rating V CC Supply Voltage − 0.5V to + 7.0V I IK DC Input Diode Current V I = − 0.5V − 20mA V I = V CC + 0.5 + 20mA V I DC Input Voltage − 0.5V to V CC + 0.5V I OK DC Output Diode Current V O = − 0.5V − 20mA V O = V CC + 0.5V + 20mA V O DC Output Voltage − 0.5V to V CC + 0.5V I O DC Output Source or Sink Current ± 50mA I CC or I GND DC V CC or Ground Current per Output Pin ± 50mA T STG Storage Temperature − 65 ° C to + 150 ° C T J Junction Temperature 140 ° C Symbol Parameter Rating V CC Supply Voltage AC 2.0V to 6.0V ACT 4.5V to 5.5V V I Input Voltage 0V to V CC V O Output Voltage 0V to V CC T A Operating Temperature − 40 ° C to + 85 ° C ∆ V / ∆ t Minimum Input Edge Rate, AC Devices: V IN from 30% to 70% of V CC , V CC @ 3.3V, 4.5V, 5.5V 125mV/ns ∆ V / ∆ t Minimum Input Edge Rate, ACT Devices: V IN from 0.8V to 2.0V, V CC @ 4.5V, 5.5V 125mV/ns

Page 6

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC541, 74ACT541 Rev. 1.5.0 4 7 4 A C 5 4 1 , 7 4 A C T 5 4 1 — O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts DC Electrical Characteristics for AC Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. I IN and I CC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V CC . 3. Maximum test duration 2.0ms, one output loaded at a time. Symbol Parameter V CC (V) Conditions T A = + 25 ° C T A = − 40 ° C to + 85 ° C UnitsTyp. Guaranteed Limits V IH Minimum HIGH Level Input Voltage 3.0 V OUT = 0.1V or V CC – 0.1V 1.5 2.1 2.1 V 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 V IL Maximum LOW Level Input Voltage 3.0 V OUT = 0.1V or V CC – 0.1V 1.5 0.9 0.9 V 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 V OH Minimum HIGH Level Output Voltage 3.0 I OUT = –50µA 2.99 2.9 2.9 V 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 V IN = V IL or V IH , I OH = –12mA 2.56 2.46 4.5 VIN = VIL or VIH, IOH = –24mA 3.86 3.76 5.5 VIN = VIL or VIH, IOH = –24mA(1) 4.86 4.76 VOL Maximum LOW Level Output Voltage 3.0 IOUT = 50µA 0.002 0.1 0.1 V 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 VIN = VIL or VIH, IOL = 12mA 0.36 0.44 4.5 VIN = VIL or VIH, IOL = 24mA 0.36 0.44 5.5 VIN = VIL or VIH, IOL = 24mA(1) 0.36 0.44 IIN (2) Maximum Input Leakage Current 5.5 VI = VCC, GND ±0.1 ±1.0 µA IOZ Maximum 3-STATE Leakage Current 5.5 VI (OE) = VIL, VIH; VI = VCC, GND; VO = VCC, GND ±0.25 ±2.5 µA IOLD Minimum Dynamic Output Current(3) 5.5 VOLD = 1.65V Max. 75 mA IOHD 5.5 VOHD = 3.85V Min. −75 mA ICC (2) Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 4.0 40.0 µA

Page 7

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC541, 74ACT541 Rev. 1.5.0 5 7 4 A C 5 4 1 , 7 4 A C T 5 4 1 — O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts DC Electrical Characteristics for ACT Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. Symbol Parameter VCC (V) Conditions TA = +25°C TA = −40°C to +85°C UnitsTyp. Guaranteed Limits VIH Minimum HIGH Level Input Voltage 4.5 VOUT = 0.1V or VCC − 0.1V 1.5 2.0 2.0 V 5.5 1.5 2.0 2.0 VIL Maximum LOW Level Input Voltage 4.5 VOUT = 0.1V or VCC − 0.1V 1.5 0.8 0.8 V 5.5 1.5 0.8 0.8 VOH Minimum HIGH Level Output Voltage 4.5 IOUT = −50µA 4.49 4.4 4.4 V 5.5 5.49 5.4 5.4 4.5 VIN = VIL or VIH, IOH = −24mA 3.86 3.76 5.5 VIN = VIL or VIH, IOH = −24mA(4) 4.86 4.76 VOL Maximum LOW Level Output Voltage 4.5 IOUT = 50µA 0.001 0.1 0.1 V 5.5 0.001 0.1 0.1 4.5 VIN = VIL or VIH, IOL = 24mA 0.36 0.44 5.5 VIN = VIL or VIH, IOL = 24mA(4) 0.36 0.44 IIN Maximum Input Leakage Current 5.5 VI = VCC, GND ±0.1 ±1.0 µA IOZ Maximum 3-STATE Leakage Current 5.5 VI = VIL, VIH; VO = VCC, GND ±0.25 ±2.5 µA ICCT Maximum ICC/Input 5.5 VI = VCC − 2.1V 0.6 1.5 mA IOLD Minimum Dynamic Output Current(5) 5.5 VOLD = 1.65V Max. 75 mA IOHD 5.5 VOHD = 3.85V Min. −75 mA ICC Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 4.0 40.0 µA

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©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC541, 74ACT541 Rev. 1.5.0 6 7 4 A C 5 4 1 , 7 4 A C T 5 4 1 — O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts AC Electrical Characteristics for AC Note: 6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V. AC Electrical Characteristics for ACT Note: 7. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter VCC (V) (6) TA = +25°C, CL = 50pF TA = −40°C to +85°C, CL = 50pF UnitsMin. Typ. Max. Min. Max. tPLH Propagation Delay, Data to Output 3.3 2.0 5.5 8.0 1.5 9.0 ns 5.0 1.5 4.0 6.0 1.0 6.5 tPHL Propagation Delay, Data to Output 3.3 2.0 5.5 8.0 1.5 8.5 ns 5.0 1.5 4.0 6.0 1.0 6.5 tPZH Output Enable Time 3.3 3.0 8.0 11.5 3.0 12.5 ns 5.0 2.0 6.0 8.5 1.5 9.5 tPZL Output Enable Time 3.3 2.5 7.0 10.0 2.5 11.5 ns 5.0 1.5 5.5 7.5 1.0 8.5 tPHZ Output Disable Time 3.3 3.5 9.0 12.5 2.5 14.0 ns 5.0 2.0 7.0 9.5 1.0 10.5 tPLZ Output Disable Time 3.3 2.5 6.5 9.5 2.0 10.5 ns 5.0 2.0 5.5 7.5 1.0 8.5 Symbol Parameter VCC (V) (7) TA = +25°C, CL = 50pF TA = −40°C to +85°C, CL = 50pF UnitsMin. Typ. Max. Min Max tPLH Propagation Delay, Data to Output 5.0 2.0 4.5 7.0 2.0 7.5 ns tPHL 2.0 5.5 7.0 2.0 7.5 tPZH Output Enable Time 5.0 2.0 5.0 9.0 2.0 9.5 ns tPZL 2.0 6.5 9.0 2.0 9.5 tPHZ Output Disable Time 5.0 1.5 5.5 7.5 1.5 8.0 ns tPLZ 1.5 5.5 7.5 1.5 8.0 Symbol Parameter Conditions Typ. Units CIN Input Capacitance VCC = OPEN 4.5 pF CPD Power Dissipation Capacitance for AC VCC = 5.0V 30.0 pF Power Dissipation Capacitance for ACT 70.0

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©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC541, 74ACT541 Rev. 1.5.0 7 7 4 A C 5 4 1 , 7 4 A C T 5 4 1 — O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Physical Dimensions Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ 0.10 C C A SEE DETAIL A NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. E) LANDPATTERN STANDARD: SOIC127P1030X265-20L PIN ONE INDICATOR 0.25 1 10 BC AM 20 11 B X 45° 8° 0° SEATING PLANE GAGE PLANE DETAIL A SCALE: 2:1 SEATING PLANE LAND PATTERN RECOMMENDATION F) DRAWING FILENAME: MKT-M20BREV3 0.65 1.27 2.25 9.50 13.00 12.60 11.43 7.60 7.40 10.65 10.00 0.51 0.35 1.27 2.65 MAX 0.30 0.10 0.33 0.20 0.75 0.25 (R0.10) (R0.10) 1.27 0.40 (1.40) 0.25 D) CONFORMS TO ASME Y14.5M-1994

Page 10

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC541, 74ACT541 Rev. 1.5.0 8 7 4 A C 5 4 1 , 7 4 A C T 5 4 1 — O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Physical Dimensions (Continued) Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/

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If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

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