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74ACT1284MSAX

74ACT1284MSAX

74ACT1284MSAX

For Reference Only

Part Number 74ACT1284MSAX
Manufacturer ON Semiconductor
Description TXRX IEEE TTL COMPATIBLE 20SSOP
Datasheet 74ACT1284MSAX Datasheet
Package 20-SSOP (0.209", 5.30mm Width)
In Stock 202 piece(s)
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74ACT1284MSAX

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74ACT1284MSAX Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Specialty Logic
Datasheet 74ACT1284MSAX Datasheet
Package20-SSOP (0.209", 5.30mm Width)
Series74ACT
Logic TypeIEEE STD 1284 Translation Transceiver
Supply Voltage4.5 V ~ 5.5 V
Number of Bits7
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case20-SSOP (0.209", 5.30mm Width)
Supplier Device Package20-SSOP

74ACT1284MSAX Datasheet

Page 1

Page 2

© 2000 Fairchild Semiconductor Corporation DS011683 www.fairchildsemi.com June 1996 Revised November 2000 7 4 A C T 1 2 8 4 IE E E 1 2 8 4 T ra n s c e iv e r 74ACT1284 IEEE 1284 Transceiver General Description The 74ACT1284 contains four non-inverting bidirectional buffers and three non-inverting buffers with open Drain out- puts and high drive capability on the B Ports. It is intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port mode (ECP). The HD (active HIGH) input pin enables the B Ports to switch from open Drain to a high drive totem pole output, capable of sourcing 14 mA on all seven buffers. The DIR input determines the direction of data flow on the bidirec- tional buffers. DIR (active HIGH) enables data flow from A Ports to B Ports. DIR (active LOW) enables data flow from B Ports to A Ports. Features ■TTL-compatible inputs ■A Ports have standard 4 mA totem pole outputs ■Typical input hysteresis of 0.5V ■B Port high drive source/sink capability of 14 mA ■Bidirectional non-inverting buffers ■Supports IEEE P1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals ■B Port outputs in High Impedance mode during power down ■Guaranteed 4000V minimum ESD protection Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Connection Diagram FACT is a trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74ACT1284SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT1284MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ACT1284MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description HD High Drive Enable input (Active HIGH) DIR Direction Control Input A1 - A4 Side A Inputs or Outputs B1 - B4 Side B Inputs or Outputs A5 - A7 Side A Inputs B5 - B7 Side B Outputs

Page 3

www.fairchildsemi.com 2 7 4 A C T 1 2 8 4 Truth Table Note 1: B5 - B7 Open Drain Outputs Note 2: B1 - B7 Open Drain Outputs Logic Diagram Inputs Outputs DIR HD L L B1- B4 Data to A1 - A4, and A5 - A7 Data to B5 - B7 (Note 1) L H B1- B4 Data to A1 - A4, and A5 - A7 Data to B5 - B7 H L A1 - A7 Data to B1 - B7 (Note 2) H H A1 - A7 Data to B1 - B7

Page 4

3 www.fairchildsemi.com 7 4 A C T 1 2 8 4 Absolute Maximum Ratings(Note 3) (Note 4) Recommended Operating Conditions Note 3: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. Note 4: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: This parameter is guaranteed but not tested, characterized only: RD is the measure of the B-Side output impedance with the output in the HIGH state. Supply Voltage (VCC) − 0.5V to + 7.0V DC Input Diode Current (IIK) VI = − 0.5V − 20 mA VI = VCC + 0.5V + 20 mA DC Input Voltage (VI) A Side − 0.5V to VCC + 0.5V DC Input Voltage (VI) B Side − 2V to + 7V DC Output Diode Current (IOK) VO = − 0.5V − 20 mA VO = VCC + 0.5V + 20 mA DC Output Voltage (VO) A Side − 0.5V to VCC + 0.5V DC Output Voltage (VO) B Side − 2V to + 7V DC Output Source or Sink Current (IO) ± 50 mA DC VCC or Ground Current per Output Pin (ICC or IGND) ± 50 mA Storage Temperature (TSTG) − 65° C to + 150° C Supply Voltage (VCC) 4.7V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC Operating Temperature (TA) − 40° C to + 85° C Symbol Parameter VCC Guaranteed Limits Units Conditions (V) TA = + 25° C TA = 0° C to + 70° C TA = − 40° C to + 85° C VIH Minimum HIGH Level 4.7 2.0 2.0 2.0 V Recognized Input Voltage 5.5 2.0 2.0 2.0 High Signal VIL Maximum LOW Level 4.7 0.8 0.8 0.8 V Recognized Input Voltage 5.5 0.8 0.8 0.8 Low Signal VOH Minimum HIGH Level 4.7 4.5 4.5 4.5 V IOUT = − 50 µ A (An) Output Voltage VIN = VIL or VIH (Note 5) 3.7 3.7 3.7 IOH = − 4 mA (An) 2.4 2.4 2.4 IOH = − 14 mA (Bn) VOL Maximum LOW Level 4.7 0.2 0.2 0.2 V IOUT = 50 µ A (An) Output Voltage VIN = VIL or VIH (Note 5) 0.4 0.4 0.4 IOH = 4 mA (An) IOH = 14 mA (Bn) IIN Maximum Input 5.5 ± 0.1 ± 1.0 µ A VI = VCC, GND Leakage Current (DIR, A5, A6, A7, HD) ICCT Maximum ICC/Input 5.5 1.5 1.5 mA VI = VCC − 2.1V ICC Maximum Quiescent 5.5 400 400 500 µ A VIN = VCC or GND Supply Current IOZ Maximum Output 5.5 ± 20 ± 20 ± 20 µ A VO = VCC, GND Leakage Current IOFF Maximum B-Side Power Down 0.0 100 100 100 µ A VOUT = 5.25V Leakage Current ∆ VT Input Hysteresis 5.0 0.4 0.4 0.35 V VT + − VT− RD Maximum Output Impedance 5.0 22 22 24 Ω Bn (Note 6) Minimum Output Impedance 5.0 8 8 6 Ω Bn (Note 6)

Page 5

www.fairchildsemi.com 4 7 4 A C T 1 2 8 4 AC Electrical Characteristics Note 7: Open Drain Note 8: This parameter is guaranteed but not tested, characterized only. Note: Pulse Generator for all pulses; Rate ≤ 1.0 MHz; AO ≤ 50Ω ; tf ≤ 2.5 ns, tr ≤ 2.5 ns. Capacitance Symbol Parameter TA = + 25° C TA = 0° C to + 70° C TA = − 40° C to + 85° C Units Figure Number VCC = 4.7V − 5.5V VCC = 4.7V − 5.5V VCC = 4.7V − 5.5V Min Max Min Max Min Max tPHL A1- A7 to B1 - B7 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 1 tPLH A1- A7 to B1 - B7 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 2 tPHL B1 - B4 to A1 - A4 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 3 tPLH B1 - B4 to A1 - A4 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 3 tpEnable Output Enable Time 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 2 HD to B1 - B7 tpDisable Output Disable Time 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 2 HD to B1 - B7 tSKEW Output Slew Rate 0.05 0.40 0.05 0.40 0.05 0.40 V/ns Figures 1, 2 tPLH B1 - B7 tPHL tr, tf tRISE and tFALL 120 120 120 ns Figure 4 B1 - B7 (Note 7) (Note 8) Symbol Parameter Typ Units Conditions CIN Input Capacitance 4.0 pF VCC = OPEN (HD, DIR A5 - A7) CI/O I/O Pin Capacitance 12.0 pF VCC = 5.0V

Page 6

5 www.fairchildsemi.com 7 4 A C T 1 2 8 4 AC Loading and Waveforms tSLEW measures between 10% to 90% on the tPHL Transition tSLEW measures between 10% to 90% on the tPLH Transition FIGURE 1. Port A to B Propagation Delay Waveforms FIGURE 2. B Output Test Load and Waveforms FIGURE 3. B to A Direction Test Load and Waveforms for Outputs A1 - A4 FIGURE 4. A to B Direction Test Load and Waveforms for Open Drain B1 - B7

Page 7

www.fairchildsemi.com 6 7 4 A C T 1 2 8 4 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20

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We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

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