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74ACTQ04SC

hot 74ACTQ04SC

74ACTQ04SC

For Reference Only

Part Number 74ACTQ04SC
Manufacturer ON Semiconductor
Description IC INVERTER 6CH 6-INP 14SOIC
Datasheet 74ACTQ04SC Datasheet
Package 14-SOIC (0.154", 3.90mm Width)
In Stock 233 piece(s)
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74ACTQ04SC Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Gates and Inverters
Datasheet 74ACTQ04SC Datasheet
Package14-SOIC (0.154", 3.90mm Width)
Series74ACTQ
Logic TypeInverter
Number of Circuits6
Number of Inputs6
Voltage - Supply4.5 V ~ 5.5 V
Current - Quiescent (Max)2µA
Current - Output High, Low24mA, 24mA
Logic Level - Low0.8V
Logic Level - High2V
Max Propagation Delay @ V, Max CL7.5ns @ 5V, 50pF
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Supplier Device Package14-SOIC
Package / Case14-SOIC (0.154", 3.90mm Width)

74ACTQ04SC Datasheet

Page 1

Page 2

© 2001 Fairchild Semiconductor Corporation DS010890 www.fairchildsemi.com August 1990 Revised March 2001 7 4 A C T Q 0 4 Q u ie t S e rie s H e x In v e rte r 74ACTQ04 Quiet Series Hex Inverter General Description The ACTQ04 contains six inverters and utilizes Fairchild Quiet Series technology to guarantee quiet output switch- ing and improved dynamic threshold performance. FACT Quiet Series features GTO output control and under- shoot corrector in addition to a split ground bus for superior ACMOS performance. Features ■ ICC reduced by 50% ■Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Improved latch-up immunity ■Outputs source/sink 24 mA ■Has TTL-compatible inputs Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74ACTQ04SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74ACTQ04SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ04MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ04PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description An Inputs On Outputs

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www.fairchildsemi.com 2 7 4 A C T Q 0 4 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are those values beyond which dam- age to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside of databook specifications. DC Electrical Characteristics for ACTQ Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: DIP package. Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND. Note 6: Max number of data inputs (n) switching. (n− 1) inputs switching 0V to 3V Input-under-test switching: 3V to threshold (V ILD), 0V to threshold (VIHD), f = 1 MHz. Supply Voltage (VCC) − 0.5V to + 7.0V DC Input Diode Current (IIK) VI = − 0.5V − 20 mA VI = VCC + 0.5V + 20 mA DC Input Voltage (VI) − 0.5V to VCC + 0.5V DC Output Diode Current (IOK) VO = − 0.5V − 20 mA VO = VCC + 0.5V + 20 mA DC Output Voltage (VO) − 0.5V to VCC + 0.5V DC Output Source or Sink Current (IO) ± 50 mA DC VCC or Ground Current per Output Pin (ICC or IGND) ± 50 mA Storage Temperature (TSTG) − 65° C to + 150° C DC Latch-up Source or Sink Current ± 300 mA Junction Temperature (TJ) PDIP 140° C Supply Voltage (VCC) 4.5V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC Operating Temperature (TA) − 40° C to + 85° C Minimum Input Edge Rate (∆ V/∆ t) 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Symbol Parameter VCC TA = + 25° C TA = − 40° C to + 85° C Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 V VOUT = 0.1V Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V VIL Maximum LOW Level 4.5 1.5 0.8 0.8 V VOUT = 0.1V Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 V IOUT = − 50 µ A Output Voltage 5.5 5.49 5.4 5.4 VIN = VILor VIH 4.5 3.86 3.76 V IOH = − 24 mA 5.5 4.86 4.76 IOH = − 24 mA (Note 2) VOL Maximum LOW Level 4.5 0.001 0.1 0.1 V IOUT = 50 µ A Output Voltage 5.5 0.001 0.1 0.1 VIN = VILor VIH 4.5 0.36 0.44 V IOL = 24 mA 5.5 0.36 0.44 IOL = 24 mA (Note 2) IIN Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µ A VI = VCC, GND ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 − 75 mA VOHD = 3.85V Min ICC Maximum Quiescent Supply Current 5.5 2.0 20.0 µ A VIN = VCC or GND VOLP Quiet Output Maximum Dynamic VOL 5.0 1.1 1.5 V Figure 1, Figure 2 (Note 4)(Note 5) VOLV Quiet Output Minimum Dynamic VOL 5.0 − 0.6 − 1.2 V Figure 1, Figure 2 (Note 4)(Note 5) VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 4)(Note 6) VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 4)(Note 6)

Page 4

3 www.fairchildsemi.com 7 4 A C T Q 0 4 AC Electrical Characteristics Note 7: Voltage Range 5.0 is 5.0V ± 0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance VCC TA = + 25° C TA = − 40° C to + 85° C Symbol Parameter (V) CL = 50 pF CL = 50 pF Units (Note 7) Min Typ Max Min Max tPLH Propagation Delay 5.0 2.0 6.5 7.5 2.0 8.0 ns Data to Output tPHL Propagation Delay 5.0 2.0 6.5 7.5 2.0 8.0 ns Data to Output tOSHL Output to Output 5.0 0.5 1.0 1.0 ns tOSLH Skew (Note 8) Symbol Parameter Typ Units Conditions CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 75 pF VCC = 5.0V

Page 5

www.fairchildsemi.com 4 7 4 A C T Q 0 4 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT . Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω . 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper load- ing of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measure- ment. VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. VOLP/VOLV and VOHP/V OHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output volt- ages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case transition.for active and enable • Verify that the GND reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as V IHD. • Verify that the GND reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. FIGURE 2. Simultaneous Switching Test Circuit

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5 www.fairchildsemi.com 7 4 A C T Q 0 4 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M14A

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www.fairchildsemi.com 6 7 4 A C T Q 0 4 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

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7 www.fairchildsemi.com 7 4 A C T Q 0 4 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14

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