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74ACTQ16541SSC

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74ACTQ16541SSC

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Part Number 74ACTQ16541SSC
Manufacturer ON Semiconductor
Description IC BUF NON-INVERT 5.5V 48SSOP
Datasheet 74ACTQ16541SSC Datasheet
Package 48-BSSOP (0.295", 7.50mm Width)
In Stock 751 piece(s)
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Lead Time Can Ship Immediately
Estimated Delivery Time Nov 2 - Nov 7 (Choose Expedited Shipping)
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Part Number # 74ACTQ16541SSC (Logic - Buffers, Drivers, Receivers, Transceivers) is manufactured by ON Semiconductor and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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74ACTQ16541SSC Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74ACTQ16541SSCDatasheet
Package48-BSSOP (0.295", 7.50mm Width)
Series74ACTQ
Logic TypeBuffer, Non-Inverting
Number of Elements2
Number of Bits per Element8
Input Type-
Output Type3-State
Current - Output High, Low24mA, 24mA
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case48-BSSOP (0.295", 7.50mm Width)
Supplier Device Package48-SSOP

74ACTQ16541SSC Datasheet

Page 1

Page 2

© 2005 Fairchild Semiconductor Corporation DS010936 www.fairchildsemi.com June 1991 Revised May 2005 7 4 A C T Q 1 6 5 4 1 1 6 -B it B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts 74ACTQ16541 16-Bit Buffer/Line Driver with 3-STATE Outputs General Description The ACTQ16541 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a mem- ory and address driver, clock driver, or bus oriented trans- mitter/receiver. The device is byte controlled. Each byte has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ACTQ16541 utilizes Fairchild Quiet Series¥ technol- ogy to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series¥ fea- tures GTO¥ output control for superior performance. Features ■Utilizes Fairchild FACT Quiet Series technology ■Guaranteed simultaneous switching noise level and dynamic threshold performance ■Guaranteed pin-to-pin output skew ■Separate control logic for each byte ■16-bit version of the ACTQ541 ■Outputs source/sink 24 mA ■Additional specs for Multiple Output Switching ■Output loading specs for both 50 pF and 250 pF loads Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Connection Diagram FACT¥, Quiet Series¥, FACT Quiet Series¥ and GTO¥ are trademarks of Fairchild Semiconductor Corporation Order Number Package Number Package Description 74ACTQ16541SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74ACTQ16541MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description OEn Output Enable Input (Active LOW) I0–I15 Inputs O0–O15 Outputs

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www.fairchildsemi.com 2 7 4 A C T Q 1 6 5 4 1 Functional Description The ACTQ16541 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is byte con- trolled with each byte functioning identically, but indepen- dent of the other. The control pins can be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each byte. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Inputs Outputs OE1 OE2 I0–I7 O0–O7 L L H H H X X Z X H X Z L L L L Inputs Outputs OE3 OE4 I8–I15 O8–O15 L L H H H X X Z X H X Z L L L L

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3 www.fairchildsemi.com 7 4 A C T Q 1 6 5 4 1 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT¥ circuits outside databook specifications. DC Electrical Characteristics Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package. Note 5: Maximum number of outputs that can switch simultaneously is n. (n  1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n  1) outputs are switched HIGH and one output held HIGH. Note 7: Maximum number of data inputs (n) switching. (n  1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD). Supply Voltage (VCC) 0.5V to +7.0V DC Input Diode Current (IIK) VI = 0.5V 20 mA VI = VCC + 0.5V +20 mA DC Output Diode Current (IOK) VO = 0.5V 20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 0.5V to VCC + 0.5V DC Output Source/Sink Current (IO) r50 mA DC VCC or Ground Current per Output Pin r50 mA Storage Temperature 65qC to +150qC Supply Voltage (VCC) 4.5V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC Operating Temperature (TA) 40qC to +85qC Minimum Input Edge Rate ('V/'t) 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Symbol Parameter VCC TA = +25qC TA = 40qC to +85qC Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH 4.5 1.5 2.0 2.0 V VOUT = 0.1V Input Voltage 5.5 1.5 2.0 2.0 or VCC  0.1V VIL Maximum LOW 4.5 1.5 0.8 0.8 V VOUT = 0.1V Input Voltage 5.5 1.5 0.8 0.8 or VCC  0.1V VOH Minimum HIGH 4.5 4.49 4.4 4.4 V IOUT = 50 PA Output Voltage 5.5 5.49 5.4 5.4 VIN = VIL or VIH 4.5 3.86 3.76 V IOH = 24 mA 5.5 4.86 4.76 IOH = 24 mA (Note 2) VOL Maximum LOW 4.5 0.001 0.1 0.1 V IOUT = 50 PA Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH 4.5 0.36 0.44 V IOL = 24 mA 5.5 0.36 0.44 IOL = 24 mA (Note 2) IOZ Maximum 3-STATE 5.5 r0.5 r5.0 PA VI = VIL, VIH Leakage Current VO = VCC, GND IIN Maximum Input Leakage Current 5.5 r0.1 r1.0 PA VI = VCC, GND ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC  2.1V ICC Max Quiescent Supply Current 5.5 8.0 80.0 PA VIN = VCC or GND IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 75 mA VOHD = 3.85V Min VOLP Quiet Output 5.0 0.5 0.8 V Figure 1, Figure 2 Maximum Dynamic VOL (Note 5)(Note 6) VOLV Quiet Output 5.0 0.5 1.0 V Figure 1, Figure 2 Minimum Dynamic VOL (Note 5)(Note 6) VOHP Maximum 5.0 VOH + 1.0 VOH + 1.5 V Figure 1, Figure 2 Overshoot (Note 4)(Note 6) VOHV Minimum 5.0 VOH  1.0 VOH  1.8 V Figure 1, Figure 2 VCC Droop (Note 4)(Note 6) VIHD Minimum HIGH Dynamic Input Voltage Level 5.0 1.7 2.0 V (Note 4)(Note 7) VILD Maximum LOW Dynamic Input Voltage Level 5.0 1.2 0.8 V (Note 4)(Note 7)

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www.fairchildsemi.com 4 7 4 A C T Q 1 6 5 4 1 AC Electrical Characteristics Note 8: Voltage Range 5.0 is 5.0V r 0.5V. Extended AC Electrical Characteristics Note 9: Voltage Range 5.0 is 5.0V r 0.5V. Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH- to-LOW (tOST). Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 14: The Output Disable Time is dominated by the RC Network (500:, 250 pF) on the output and has been excluded from the datasheet. Capacitance VCC TA = +25qC TA = 40qC to +85qC Symbol Parameter (V) CL = 50 pF CL = 50 pF Units (Note 8) Min Typ Max Min Max tPLH Propagation Delay 5.0 3.0 5.2 7.3 3.0 7.8 ns tPHL Data to Output 2.5 4.8 7.3 2.5 7.8 tPZH Output Enable Time 5.0 2.6 5.0 7.4 2.6 7.9 ns tPZL 2.7 5.4 8.0 2.7 8.5 tPHZ Output Disable Time 5.0 2.7 5.6 8.3 2.7 8.7 ns tPLZ 2.4 5.2 7.9 2.4 8.4 TA = 40qC to +85qC CL = 50 pF TA = 40qC to +85qC Symbol Parameter VCC 16 Outputs Switching CL = 250 pF Units (V) (Note 11) (Note 12) (Note 9) Min Typ Max Min Max tPLH Propagation Delay, 5.0 4.0 11.6 5.6 14.3 ns tPHL Data to Output 3.4 9.6 4.8 13.1 tPZH Output Enable Time 5.0 3.3 10.1 (Note 13) ns tPZL 3.3 10.0 tPHZ Output Disable Time 5.0 4.3 10.1 (Note 14) ns tPLZ 3.8 9.6 tOSHL Pin to Pin Skew, HL 5.0 1.2 ns (Note 10) Data to Output tOSLH Pin to Pin Skew, LH 5.0 2.5 ns (Note 10) Data to Output tOST Pin to Pin Skew, 5.0 4.3 ns (Note 10) LH/HL Data to Output Symbol Parameter Typ Units Conditions CIN Input Capacitance 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 30 pF VCC = 5.0V

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5 www.fairchildsemi.com 7 4 A C T Q 1 6 5 4 1 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500:. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper load- ing of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measure- ment. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. Note A: VOHV and VOLP are measured with respect to ground reference. Note B: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew  150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output volt- ages using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • Measure VOLP and VOLVon the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case for active and enable transition. • Verify that the GND reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. VILD and VIHD: • Monitor one of the switching outputs using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. FIGURE 2. Simultaneous Switching Test Circuit

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www.fairchildsemi.com 6 7 4 A C T Q 1 6 5 4 1 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A

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August 21, 2020

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August 10, 2020

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August 8, 2020

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August 6, 2020

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July 25, 2020

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July 22, 2020

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July 12, 2020

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July 11, 2020

Sure appreciate your quality, expertise and professional service. Thank you so much!!!

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