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74ACTQ245SC

74ACTQ245SC

74ACTQ245SC

For Reference Only

Part Number 74ACTQ245SC
Manufacturer ON Semiconductor
Description IC TXRX NON-INVERT 5.5V 20SOIC
Datasheet 74ACTQ245SC Datasheet
Package 20-SOIC (0.295", 7.50mm Width)
In Stock 226 piece(s)
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74ACTQ245SC Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74ACTQ245SC Datasheet
Package20-SOIC (0.295", 7.50mm Width)
Series74ACTQ
Logic TypeTransceiver, Non-Inverting
Number of Elements1
Number of Bits per Element8
Output Type3-State
Current - Output High, Low24mA, 24mA
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case20-SOIC (0.295", 7.50mm Width)
Supplier Device Package20-SOIC

74ACTQ245SC Datasheet

Page 1

Page 2

© 2005 Fairchild Semiconductor Corporation DS010236 www.fairchildsemi.com July 1989 Revised March 2005 7 4 A C Q 2 4 5 • 7 4 A C T Q 2 4 5 Q u ie t S e rie s  O c ta l B id ire c tio n a l T ra n s c e iv e r w ith 3 -S T A T E In p u ts /O u tp u ts 74ACQ245 • 74ACTQ245 Quiet Series Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs General Description The ACQ/ACTQ245 contains eight non-inverting bidirec- tional buffers with 3-STATE outputs and is intended for bus- oriented applications. Current sinking capability is 24 mA at both the A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirec- tional transceiver. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition. The ACQ/ACTQ utilizes Fairchild Quiet Series¥ technol- ogy to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series¥ fea- tures GTO¥ output control and undershoot corrector in addition to a split ground bus for superior performance. Features ■ ICC and IOZ reduced by 50% ■Guaranteed simultaneous switching noise level and dynamic threshold performance ■Guaranteed pin-to-pin skew AC performance ■ Improved latch-up immunity ■3-STATE outputs drive bus lines or buffer memory address registers ■Outputs source/sink 24 mA ■Faster prop delays than the standard ACT245 Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. FACT¥, Quiet Series¥, FACT Quiet Series¥, and GTO¥ are trademarks of Fairchild Semiconductor Corporation. Order Number Package Package Description Number 74ACQ245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACQ245SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACQ245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACTQ245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACTQ245SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ245QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 74ACTQ245MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ACTQ245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ245MTCX_NL (Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Page 3

www.fairchildsemi.com 2 7 4 A C Q 2 4 5 • 7 4 A C T Q 2 4 5 Connection Diagram Logic Symbols IEEE/IEC Pin Descriptions Truth Table H HIGH Voltage Level L LOW Voltage Level X Immaterial Pin Names Description OE Output Enable Input T/R Transmit/Receive Input A0–A7 Side A 3-STATE Inputs or 3-STATE Outputs B0–B7 Side B 3-STATE Inputs or 3-STATE Outputs Inputs Outputs OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State

Page 4

3 www.fairchildsemi.com 7 4 A C Q 2 4 5 • 7 4 A C T Q 2 4 5 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT¥ circuits outside databook specifications. DC Electrical Characteristics for ACQ Supply Voltage (VCC) 0.5V to 7.0V DC Input Diode Current (IIK) VI 0.5V 20 mA VI VCC  0.5V 20 mA DC Input Voltage (VI) 0.5V to VCC  0.5V DC Output Diode Current (IOK) VO 0.5V 20 mA VO VCC  0.5V 20 mA DC Output Voltage (VO) 0.5V to VCC  0.5V DC Output Source or Sink Current (IO) r50 mA DC VCC or Ground Current per Output Pin (ICC or IGND) r50 mA Storage Temperature (TSTG) 65qC to 150qC DC Latch-Up Source or Sink Current r300 mA Junction Temperature (TJ) PDIP 140qC Supply Voltage (VCC) ACQ 2.0V to 6.0V ACTQ 4.5V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC Operating Temperature (TA) 40qC to 85qC Minimum Input Edge Rate 'V/'t ACQ Devices VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V 125 mV/ ns Minimum Input Edge Rate 'V/'t ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Symbol Parameter VCC TA 25qC TA 40qC to 85qC Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT 0.1V Input Voltage 4.5 2.25 3.15 3.15 V or VCC  0.1V 5.5 2.75 3.85 3.85 VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT 0.1V Input Voltage 4.5 2.25 1.35 1.35 V or VCC  0.1V 5.5 2.75 1.65 1.65 VOH Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V IOUT 50 PA 5.5 5.49 5.4 5.4 VIN VIL or VIH 3.0 2.56 2.46 IOH 12 mA 4.5 3.86 3.76 V IOH 24 mA 5.5 4.86 4.76 IOH 24 mA (Note 3) VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V IOUT 50 PA 5.5 0.001 0.1 0.1 VIN VIL or VIH 3.0 0.36 0.44 IOL 12 mA 4.5 0.36 0.44 V IOL 24 mA 5.5 0.36 0.44 IOL 24 mA (Note 3) IIN Maximum Input 5.5 r0.1 r1.0 PA VI VCC, GND (Note 5) Leakage Current IOLD Minimum Dynamic 5.5 75 mA VOLD 1.65V Max IOHD Output Current (Note 4) 5.5 75 mA VOHD 3.85V Min ICC Maximum Quiescent 5.5 4.0 40.0 PA VIN VCC (Note 5) Supply Current or GND IOZT Maximum I/O VI (OE) VIL, VIH Leakage Current 5.5 r0.3 r3.0 PA VI VCC, GND VO VCC, GND

Page 5

www.fairchildsemi.com 4 7 4 A C Q 2 4 5 • 7 4 A C T Q 2 4 5 DC Electrical Characteristics for ACQ (Continued) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 6: DIP package. Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V; one output @ GND. Note 8: Max number of Data Inputs (n) switching. (n1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f 1 MHz. DC Electrical Characteristics for ACTQ Note 9: All outputs loaded; thresholds on input associated with output under test. Note 10: Maximum test duration 2.0 ms, one output loaded at a time. Note 11: DIP package. Note 12: Max number of outputs defined as (n). n1 Data Inputs are driven 0V to 3V; one output @ GND. Note 13: Max number of Data Inputs (n) switching. (n1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD) f 1 MHz. Symbol Parameter VCC TA 25qC TA 40qC to 85qC Units Conditions (V) Typ Guaranteed Limits VOLP Quiet Output 5.0 1.1 1.5 V Figure 1, Figure 2 Maximum Dynamic VOL (Note 6)(Note 7) VOLV Quiet Output 5.0 0.6 1.2 V Figure 1, Figure 2 Minimum Dynamic VOL (Note 6)(Note 7) VIHD Minimum HIGH Level 5.0 3.1 3.5 V (Note 6)(Note 8) Dynamic Input Voltage VILD Maximum LOW Level 5.0 1.9 1.5 V (Note 6)(Note 8) Dynamic Input Voltage Symbol Parameter VCC TA 25qC TA 40qC to 85qC Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 V VOUT 0.1V Input Voltage 5.5 1.5 2.0 2.0 or VCC  0.1V VIL Maximum LOW Level 4.5 1.5 0.8 0.8 V VOUT 0.1V Input Voltage 5.5 1.5 0.8 0.8 or VCC  0.1V VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 V IOUT 50 PA Output Voltage 5.5 5.49 5.4 5.4 VIN VIL or VIH 4.5 3.86 3.76 V IOH 24 mA 5.5 4.86 4.76 IOH 24 mA (Note 9) VOL Maximum LOW Level 4.5 0.001 0.1 0.1 V IOUT 50 PA Output Voltage 5.5 0.001 0.1 0.1 VIN VIL or VIH 4.5 0.36 0.44 V IOL 24 mA 5.5 0.36 0.44 IOL 24 mA (Note 9) IIN Maximum Input Leakage Current 5.5 r0.1 r1.0 PA VI VCC, GND IOZT Maximum 3-STATE 5.5 r0.3 r3.0 PA VI VIL, VIH Leakage Current VO VCC, GND ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI VCC  2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD 1.65V Max IOHD Output Current (Note 10) 5.5 75 mA VOHD 3.85V Min ICC Maximum Quiescent Supply Current 5.5 4.0 40.0 PA VIN VCC or GND VOLP Quiet Output 5.0 1.1 1.5 V Figure 1, Figure 2 Maximum Dynamic VOL (Note 11)(Note 12) VOLV Quiet Output 5.0 0.6 1.2 V Figure 1, Figure 2 Minimum Dynamic VOL (Note 11)(Note 12) VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 11)(Note 13) VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 11)(Note 13)

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5 www.fairchildsemi.com 7 4 A C Q 2 4 5 • 7 4 A C T Q 2 4 5 AC Electrical Characteristics for ACQ Note 14: Voltage Range 5.0 is 5.0V r 0.5V Voltage Range 3.3 is 3.3V r 0.3V Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Electrical Characteristics for ACTQ Note 16: Voltage Range 5.0 is 5.0V r 0.5V Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance VCC TA 25qC TA 40qC to 85qC Symbol Parameter (V) CL 50 pF CL 50 pF Units (Note 14) Min Typ Max Min Max tPHL Propagation Delay 3.3 2.0 7.5 10.0 2.0 10.5 ns tPLH Data to Output 5.0 1.5 5.0 6.5 1.5 7.0 tPZL Output Enable Time 3.3 3.0 8.5 13.0 3.0 13.5 ns tPZH 5.0 2.0 6.0 8.5 2.0 9.0 tPHZ Output Disable Time 3.3 1.0 8.5 14.5 1.0 15.0 ns tPLZ 5.0 1.0 7.5 9.5 1.0 10.0 tOSHL Output to Output Skew (Note 15) 3.3 1.0 1.5 1.5 ns tOSLH Data to Output 5.0 0.5 1.0 1.0 VCC TA 25qC TA 40qC to 85qC Symbol Parameter (V) CL 50 pF CL 50 pF Units (Note 16) Min Typ Max Min Max tPHL Propagation Delay 5.0 1.5 5.5 7.0 1.5 7.5 ns tPLH Data to Output tPZL, tPZH Output Enable Time 5.0 2.0 7.0 9.0 2.0 9.5 ns tPHZ, tPLZ Output Disable Time 5.0 1.0 8.0 10.0 1.0 10.5 ns tOSHL Output to Output Skew (Note 17) 5.0 0.5 1.0 1.0 ns tOSLH Data to Output Symbol Parameter Typ Units Conditions CIN Input Capacitance 4.5 pF VCC OPEN CI/O Input/Output Capacitance 15 pF VCC 5.0V CPD Power Dissipation Capacitance 80.0 pF VCC 5.0V

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www.fairchildsemi.com 6 7 4 A C Q 2 4 5 • 7 4 A C T Q 2 4 5 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500:. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper load- ing of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measure- ment. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. FIGURE 1. Quiet Output Noise Voltage Waveforms Note 18: VOHV and VOLP are measured with respect to ground reference. Note 19: Input pulses have the following characteristics: f 1 MHz, tr 3 ns, tf 3 ns, skew  150 ps. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output volt- ages using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. • Verify that the GND reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. VILD and VIHD: • Monitor one of the switching outputs using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. FIGURE 2. Simultaneous Switching Test Circuit

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7 www.fairchildsemi.com 7 4 A C Q 2 4 5 • 7 4 A C T Q 2 4 5 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B

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www.fairchildsemi.com 8 7 4 A C Q 2 4 5 • 7 4 A C T Q 2 4 5 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

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9 www.fairchildsemi.com 7 4 A C Q 2 4 5 • 7 4 A C T Q 2 4 5 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20

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