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74F109SJ

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74F109SJ

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Part Number 74F109SJ
Manufacturer Fairchild/ON Semiconductor
Description IC JK TYPE POS TRG DUAL 16SOP
Datasheet 74F109SJ Datasheet
Package 16-SOIC (0.209", 5.30mm Width)
In Stock 1,072 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 15 - Jul 20 (Choose Expedited Shipping)
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Part Number # 74F109SJ (Logic - Flip Flops) is manufactured by Fairchild/ON Semiconductor and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

For 74F109SJ specifications/configurations, quotation, lead time, payment terms of further enquiries please have no hesitation to contact us. To process your RFQ, please add 74F109SJ with quantity into BOM. Heisener.com does NOT require any registration to request a quote of 74F109SJ.

74F109SJ Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Flip Flops
Datasheet 74F109SJDatasheet
Package16-SOIC (0.209", 5.30mm Width)
Series74F
FunctionSet(Preset) and Reset
TypeJK Type
Output TypeDifferential
Number of Elements2
Number of Bits per Element1
Clock Frequency125MHz
Max Propagation Delay @ V, Max CL8ns @ 5V, 50pF
Trigger TypePositive Edge
Current - Output High, Low1mA, 20mA
Voltage - Supply4.5 V ~ 5.5 V
Current - Quiescent (Iq)17mA
Input Capacitance-
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeSurface Mount
Package / Case16-SOIC (0.209", 5.30mm Width)

74F109SJ Datasheet

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© 2000 Fairchild Semiconductor Corporation DS009471 www.fairchildsemi.com April 1988 Revised September 2000 7 4 F 1 0 9 D u a l J K P o s itiv e E d g e -T rig g e re d F lip -F lo p 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely indepen- dent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Page 3

www.fairchildsemi.com 2 7 4 F 1 0 9 Truth Table H (h) = HIGH Voltage Level L (l) = LOW Voltage Level  = LOW-to-HIGH Transition X = Immaterial Q0 (Q0) = Before LOW-to-HIGH Transition of Clock Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition. Unit Loading/Fan Out Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Outputs SD CD CP J K Q Q L H X X X H L H L X X X L H L L X X X H H H H  I I L H H H  h I Toggle H H  I h Q Q H H  h h H L H H L X X Q Q Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL J1, J2, K1, K2 Data Inputs 1.0/1.0 20 µ A/− 0.6 mA CP1, CP2 Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µ A/− 0.6 mA CD1, CD2 Direct Clear Inputs (Active LOW) 1.0/3.0 20 µ A/− 1.8 mA SD1, SD2 Direct Set Inputs (Active LOW) 1.0/3.0 20 µ A/− 1.8 mA Q1, Q2, Q1, Q2 Outputs 50/33.3 − 1 mA/20 mA

Page 4

3 www.fairchildsemi.com 7 4 F 1 0 9 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Storage Temperature − 65° C to + 150° C Ambient Temperature under Bias − 55° C to + 125° C Junction Temperature under Bias − 55° C to + 175° C VCC Pin Potential to Ground Pin − 0.5V to + 7.0V Input Voltage (Note 2) − 0.5V to + 7.0V Input Current (Note 2) − 30 mA to + 5.0 mA Voltage Applied to Output in HIGH State (with Vcc = 0V) Standard Output − 0.5V to VCC 3-STATE Output − 0.5V to + 5.5V Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Free Air Ambient Temperature 0° C to + 70° C Supply Voltage + 4.5V to + 5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage − 1.2 V Min IIN = − 18 mA VOH Output HIGH Voltage 10% VCC 2.5 V Min IOH = − 1 mA 5% VCC 2.7 IOH = − 1 mA VOL Output LOW Voltage 10% VCC 0.5 V Min IOL = 20 mA IIH Input HIGH Current 5.0 µ A Max VIN = 2.7V IBVI Input HIGH Current Breakdown Test 7.0 µ A Max VIN = 7.0V ICEX Output HIGH Leakage Current 50 µ A Max VOUT = VCC VID Input Leakage Test 4.75 V 0.0 IID = 1.9 µ A All Other Pins Grounded IOD Output Leakage 3.75 µ A 0.0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current − 0.6 mA Max VIN = 0.5V (Jn, Kn) − 1.8 mA Max VIN = 0.5V (CDn, SDn) IOS Output Short-Circuit Current − 60 − 150 mA Max VOUT = 0V ICC Power Supply Current 11.7 17.0 mA Max CP = 0V

Page 5

www.fairchildsemi.com 4 7 4 F 1 0 9 AC Electrical Characteristics AC Operating Requirements Symbol Parameter TA = + 25° C TA = 0° C to + 70° C Units VCC = + 5.0V VCC = + 5.0V CL = 50 pF CL = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 100 125 90 MHz tPLH Propagation Delay 3.8 5.3 7.0 3.8 8.0 ns tPHL CPn to Qn or Qn 4.4 6.2 8.0 4.4 9.2 tPLH Propagation Delay 3.2 5.2 7.0 3.2 8.0 ns tPHL CDn or SDn to 3.5 7.0 9.0 3.5 10.5 ns Qn or Qn Symbol Parameter TA = + 25° C TA = 0° C to + 70° C UnitsVCC = + 5.0V VCC = + 5.0V Min Max Min Max tS(H) Setup Time, HIGH or LOW 3.0 3.0 ns tS(L) Jn or Kn to CPn 3.0 3.0 tH(H) Hold Time, HIGH or LOW 1.0 1.0 tH(L) Jn or Kn to CPn 1.0 1.0 tW(H) CPn Pulse Width 4.0 4.0 ns tW(L) HIGH or LOW 5.0 5.0 tW(L) CDn or SDn Pulse Width LOW 4.0 4.0 ns tREC Recovery Time 2.0 2.0 ns CDn or SDn to CP

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5 www.fairchildsemi.com 7 4 F 1 0 9 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

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www.fairchildsemi.com 6 7 4 F 1 0 9 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

74F109SJ Reviews

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June 30, 2020

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June 24, 2020

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June 23, 2020

To be honest, I think you are doing an outstanding job.

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June 17, 2020

I've had no issues. Good product, would buy again.

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June 7, 2020

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May 31, 2020

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May 22, 2020

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Euge*****arma

May 21, 2020

Worked wonderfully. Went through the instructions to the tea to make sure it was done correctly.

Joli*****bride

May 17, 2020

Heisener is on a very short list of companies I highly recommend without any hesitation. From stock, pricing, ease of ordering and great service, they have it all.

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May 13, 2020

Very happy for the fast shipping and good price!

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