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74F373SJX

hot 74F373SJX

74F373SJX

For Reference Only

Part Number 74F373SJX
Manufacturer Fairchild/ON Semiconductor
Description IC LATCH TRANSP OCT 3ST 20SOP
Datasheet 74F373SJX Datasheet
Package 20-SOIC (0.209", 5.30mm Width)
In Stock 20028 piece(s)
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Lead Time Can Ship Immediately
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74F373SJX

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74F373SJX Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Latches
Datasheet 74F373SJX Datasheet
Package20-SOIC (0.209", 5.30mm Width)
Series74F
Logic TypeD-Type Transparent Latch
Circuit8:8
Output TypeTri-State
Voltage - Supply4.5 V ~ 5.5 V
Independent Circuits1
Delay Time - Propagation5.3ns
Current - Output High, Low3mA, 24mA
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mount
Package / Case20-SOIC (0.209", 5.30mm Width)
Supplier Device Package20-SOP

74F373SJX Datasheet

Page 1

Page 2

© 2000 Fairchild Semiconductor Corporation DS009523 www.fairchildsemi.com May 1988 Revised September 2000 7 4 F 3 7 3 O c ta l T ra n s p a re n t L a tc h w ith 3 -S T A T E O u tp u ts 74F373 Octal Transparent Latch with 3-STATE Outputs General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. Features ■Eight latches in a single package ■3-STATE outputs for bus interfacing ■Guaranteed 4000V minimum ESD protection Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F373MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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www.fairchildsemi.com 2 7 4 F 3 7 3 Unit Loading/Fan Out Functional Description The 74F373 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance State Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL D0–D7 Data Inputs 1.0/1.0 20 µ A/− 0.6 mA LE Latch Enable Input (Active HIGH) 1.0/1.0 20 µ A/− 0.6 mA OE Output Enable Input (Active LOW) 1.0/1.0 20 µ A/− 0.6 mA O0–O7 3-STATE Latch Outputs 150/40 (33.3) − 3 mA/24 mA (20 mA) Inputs Output LE OE Dn On H L H H H L L L L L X On (no change) X H X Z

Page 4

3 www.fairchildsemi.com 7 4 F 3 7 3 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Storage Temperature − 65° C to + 150° C Ambient Temperature under Bias − 55° C to + 125° C Junction Temperature under Bias − 55° C to + 150° C VCC Pin Potential to Ground Pin − 0.5V to + 7.0V Input Voltage (Note 2) − 0.5V to + 7.0V Input Current (Note 2) − 30 mA to + 5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output − 0.5V to VCC 3-STATE Output − 0.5V to + 5.5V Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0° C to + 70° C Supply Voltage + 4.5V to + 5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage − 1.2 V Min IIN = − 18 mA VOH Output HIGH 10% VCC 2.5 V Min IOH = − 1 mA Voltage 10% VCC 2.4 IOH = − 3 mA 5% VCC 2.7 IOH = − 1 mA 5% VCC 2.7 IOH = − 3 mA VOL Output LOW Voltage 10% VCC 0.5 V Min IOL = 24 mA IIH Input HIGH 5.0 µ A Max VIN = 2.7V Current IBVI Input HIGH Current 7.0 µ A Max VIN = 7.0V Breakdown Test ICEX Output HIGH 50 µ A Max VOUT = VCC Leakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µ A Test All Other Pins Grounded IOD Output Leakage 3.75 µ A 0.0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current − 0.6 mA Max VIN = 0.5V IOZH Output Leakage Current 50 µ A Max VOUT = 2.7V IOZL Output Leakage Current − 50 µ A Max VOUT = 0.5V IOS Output Short-Circuit Current − 60 − 150 mA Max VOUT = 0V IZZ Bus Drainage Test 500 µ A 0.0V VOUT = 5.25V ICCZ Power Supply Current 38 55 mA Max VO = HIGH Z

Page 5

www.fairchildsemi.com 4 7 4 F 3 7 3 AC Electrical Characteristics AC Operating Requirements Symbol Parameter TA = + 25° C TA = − 55° C to + 125° C TA = 0° C to + 70° C Units VCC = + 5.0V VCC = + 5.0V VCC = + 5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 3.0 5.3 7.0 3.0 8.5 3.0 8.0 ns tPHL Dn to On 2.0 3.7 5.0 2.0 7.0 2.0 6.0 tPLH Propagation Delay 5.0 9.0 11.5 5.0 15.0 5.0 13.0 ns tPHL LE to On 3.0 5.2 7.0 3.0 8.5 3.0 8.0 tPZH Output Enable Time 2.0 5.0 11.0 2.0 13.5 2.0 12.0 ns tPZL 2.0 5.6 7.5 2.0 10.0 2.0 8.5 tPHZ Output Disable Time 1.5 4.5 6.5 1.5 10.0 1.5 7.5 ns tPLZ 1.5 3.8 5.0 1.5 7.0 1.5 6.0 Symbol Parameter TA = + 25° C TA = − 55° C to + 125° C TA = 0° C to + 70° C UnitsVCC = + 5.0V VCC = + 5.0V VCC = + 5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 2.0 2.0 2.0 ns tS(L) Dn to LE 2.0 2.0 2.0 tH(H) Hold Time, HIGH or LOW 3.0 3.0 3.0 tH(L) Dn to LE 3.0 4.0 3.0 tW(H) LE Pulse Width, HIGH 6.0 6.0 6.0 ns

Page 6

5 www.fairchildsemi.com 7 4 F 3 7 3 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B

Page 7

www.fairchildsemi.com 6 7 4 F 3 7 3 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

Page 8

7 www.fairchildsemi.com 7 4 F 3 7 3 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20

74F373SJX Guarantees

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If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

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