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74LCX125SJX

hot 74LCX125SJX

74LCX125SJX

For Reference Only

Part Number 74LCX125SJX
Manufacturer ON Semiconductor
Description IC BUFFER NON-INVERT 3.6V 14SOP
Datasheet 74LCX125SJX Datasheet
Package 14-SOIC (0.209", 5.30mm Width)
In Stock 486 piece(s)
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74LCX125SJX

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74LCX125SJX Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74LCX125SJX Datasheet
Package14-SOIC (0.209", 5.30mm Width)
Series74LCX
Logic TypeBuffer, Non-Inverting
Number of Elements4
Number of Bits per Element1
Output Type3-State
Current - Output High, Low24mA, 24mA
Voltage - Supply2 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case14-SOIC (0.209", 5.30mm Width)
Supplier Device Package14-SOP

74LCX125SJX Datasheet

Page 1

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To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. Is Now Part of ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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7 4 L C X 1 2 5 — L o w V o lta g e Q u a d B u ffe r w ith 5 V T o le ra n t In p u ts a n d O u tp u ts ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX125 Rev. 1.7.1 74LCX125 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs Features ■ 5V tolerant inputs and outputs ■ 2.3V–3.6V V CC specifications provided ■ 6.0ns t PD max. (V CC = 3.3V), 10µA I CC max. ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (1) ■ ±24mA output drive (V CC = 3.0V) ■ ■ Latch-up performance exceeds JEDEC 78 conditions ■ ESD performance: – Human body model > 2000V – Machine model > 100V ■ Leadless DQFN package Note: 1. To ensure the high-impedance state during power up or down, OE should be tied to V CC through a pull-up resistor: the minimum value of the resistor is determined by the current-sourcing capability of the driver. General Description The LCX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate volt- ages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX125 is fabricated with an advanced CMOS technology to achieve high speed operation while main- taining CMOS low power dissipation. Ordering Information Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Package Number Package Description 74LCX125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LCX125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX125BQX (2) MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm 74LCX125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Implements proprietary noise/EMI reduction circuitry December 2013

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX125 Rev. 1.7.1 2 7 4 L C X 1 2 5 — L o w V o lta g e Q u a d B u ffe r w ith 5 V T o le ra n t In p u ts a n d O u tp u ts Connection Diagrams Pin Assignments for SOIC, SOP, and TSSOP (Top View) Pad Assignments for DQFN (Top Through View) Pin Description Logic Symbol IEEE/IEC Truth Table H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial Pin Names Description A n Inputs OE n Output Enable Inputs O n Outputs Inputs Output OE n A n O n L L L L H H H X Z (Bottom View) DAP No Connect Note: DAP (Die Attach Pad)

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 7 4 L C X 1 2 5 — L o w V o lta g e Q u a d B u ffe r w ith 5 V T o le ra n t In p u ts a n d O u tp u ts Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Note: 3. I O Absolute Maximum Rating must be observed. Recommended Operating Conditions (4) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Note: 4. Unused inputs must be held HIGH or LOW. They may not float. Symbol Parameter Rating V CC Supply Voltage –0.5V to +7.0V V I DC Input Voltage –0.5V to +7.0V V O DC Output Voltage, Output in 3-STATE –0.5V to +7.0V Output in HIGH or LOW State (3) –0.5V to V CC + 0.5V I IK DC Input Diode Current, V I < GND –50mA I OK DC Output Diode Current V O < GND –50mA V O > V CC +50mA I O DC Output Source/Sink Current ±50mA I CC DC Supply Current per Supply Pin ±100mA I GND DC Ground Current per Ground Pin ±100mA T STG Storage Temperature –65°C to +150°C Symbol Parameter Min. Max. Units V CC Supply Voltage Operating 2.0 3.6 V Data Retention 1.5 3.6 V I Input Voltage 0 5.5 V V O Output Voltage HIGH or LOW State 0 V CC V 3-STATE 0 5.5 I OH / I OL Output Current V CC = 3.0V–3.6V ±24 mA V CC = 2.7V–3.0V ±12 V CC = 2.3V–2.7V ±8 T A Free-Air Operating Temperature –40 85 °C ∆ t / ∆ V Input Edge Rate, V IN = 0.8V–2.0V, V CC = 3.0V 0 10 ns / V 74LCX125 Rev. 1.7.1 3

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 7 4 L C X 1 2 5 — L o w V o lta g e Q u a d B u ffe r w ith 5 V T o le ra n t In p u ts a n d O u tp u ts DC Electrical Characteristics Note: 5. Outputs disabled or 3-STATE only. AC Electrical Characteristics Note: 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ). Symbol Parameter V CC (V) Conditions T A = –40°C to +85°C UnitsMin. Max. V IH HIGH Level Input Voltage 2.3–2.7 1.7 V 2.7–3.6 2.0 V IL LOW Level Input Voltage 2.3–2.7 0.7 V 2.7–3.6 0.8 V OH HIGH Level Output Voltage 2.3–3.6 I OH = –100µA V CC – 0.2 V 2.3 I OH = –8mA 1.8 2.7 I OH = –12mA 2.2 3.0 I OH = –18mA 2.4 I OH = –24mA 2.2 V OL LOW Level Output Voltage 2.3–3.6 I OL = 100µA 0.2 V 2.3 I OL = 8mA 0.6 2.7 I OL = 12mA 0.4 3.0 I OL = 16mA 0.4 I OL = 24mA 0.55 I I Input Leakage Current 2.3–3.6 0 ≤ VI ≤ 5.5V ±5.0 µA IOZ 3-STATE Output Leakage 2.3–3.6 0 ≤ VO ≤ 5.5V, VI = VIH or VIL ±5.0 µA IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA ICC Quiescent Supply Current 2.3–3.6 VI = VCC or GND 10 µA 3.6V ≤ VI, VO ≤ 5.5V(5) ±10 ∆ICC Increase in ICC per Input 2.3–3.6 VIH = VCC – 0.6V 500 µA Symbol Parameter TA = –40°C to +85°C, RL = 500Ω Units VCC = 3.3V ± 0.3V, CL = 50 pF VCC = 2.7V, CL = 50 pF VCC = 2.5V ± 0.2V, CL = 30 pF Min. Max. Min. Max. Min. Max. tPHL, tPLH Propagation Delay 1.5 6.0 1.5 6.5 1.5 7.2 ns tPZL, tPZH Output Enable Time 1.5 7.0 1.5 8.0 1.5 9.1 ns tPLZ, tPHZ Output Disable Time 1.5 6.0 1.5 7.0 1.5 7.2 ns tOSHL, tOSLH Output to Output Skew (6) 1.0 ns 74LCX125 Rev. 1.7.1 4

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 7 4 L C X 1 2 5 — L o w V o lta g e Q u a d B u ffe r w ith 5 V T o le ra n t In p u ts a n d O u tp u ts Dynamic Switching Characteristics Capacitance Symbol Parameter VCC (V) Conditions TA = 25°C UnitTypical VOLP Quiet Output Dynamic Peak VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6 VOLV Quiet Output Dynamic Valley VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 V 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6 Symbol Parameter Conditions Typical Units CIN Input Capacitance VCC = Open, VI = 0V or VCC 7.0 pF COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8.0 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10MHz 25.0 pF 74LCX125 Rev. 1.7.1 5

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 7 4 L C X 1 2 5 — L o w V o lta g e Q u a d B u ffe r w ith 5 V T o le ra n t In p u ts a n d O u tp u ts AC Loading and Waveforms (Generic for LCX Family) Figure 1. AC Test Circuit (CL includes probe and jig capacitance) Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and trec Waveforms 3-STATE Output Low Enable and Disable Times for Logic 3-STATE Output High Enable and Disable Times for Logic Setup Time, Hold Time and Recovery Time for Logic trise and tfall Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH, tPHZ GND Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC / 2 Vmo 1.5V 1.5V VCC / 2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH – 0.3V VOH – 0.3V VOH – 0.15V 74LCX125 Rev. 1.7.1 6

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 7 4 L C X 1 2 5 — L o w V o lta g e Q u a d B u ffe r w ith 5 V T o le ra n t In p u ts a n d O u tp u ts Schematic Diagram (Generic for LCX Family) 74LCX125 Rev. 1.7.1 7

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 7 4 L C X 1 2 5 — L o w V o lta g e Q u a d B u ffe r w ith 5 V T o le ra n t In p u ts a n d O u tp u ts Tape and Reel Specification Tape Format for DQFN Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status BQX Leader (Start End) 125 (Typ.) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typ.) Empty Sealed Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) 74LCX125 Rev. 1.7.1 8

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