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74LVTH240MTCX

hot 74LVTH240MTCX

74LVTH240MTCX

For Reference Only

Part Number 74LVTH240MTCX
Manufacturer ON Semiconductor
Description IC BUFFER INVERT 3.6V 20TSSOP
Datasheet 74LVTH240MTCX Datasheet
Package 20-TSSOP (0.173", 4.40mm Width)
In Stock 1414 piece(s)
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74LVTH240MTCX

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74LVTH240MTCX Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74LVTH240MTCX Datasheet
Package20-TSSOP (0.173", 4.40mm Width)
Series74LVTH
Logic TypeBuffer, Inverting
Number of Elements2
Number of Bits per Element4
Output Type3-State
Current - Output High, Low32mA, 64mA
Voltage - Supply2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case20-TSSOP (0.173", 4.40mm Width)
Supplier Device Package20-TSSOP

74LVTH240MTCX Datasheet

Page 1

Page 2

To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. Is Now Part of ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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7 4 L V T 2 4 0 , 7 4 L V T H 2 4 0 — L o w V o lta g e O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT240, 74LVTH240 Rev. 1.5.0 January 2008 74LVT240, 74LVTH240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs Features ■ Input and output interface capability to systems at 5V V CC ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH240), also available without bushold feature (74LVT240) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink –32mA/+64mA ■ Functionally compatible with the 74 series 240 ■ Latch-up performance exceeds 500mA ■ ESD performance: – Human-body model > 2000V – Machine model > 200V – Charged-device model > 1000V General Description The LVT240 and LVTH240 are inverting octal buffers and line drivers designed to be employed as memory address drivers, clock drivers and bus oriented transmit- ters or receivers which provides improved PC board density. The LVTH240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal buffers and line drivers are designed for low- voltage (3.3V) V CC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT240 and LVTH240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Ordering Information Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Package Number Package Description 74LVT240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVT240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVT240MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LVT240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVTH240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH240MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LVTH240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Page 4

©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT240, 74LVTH240 Rev. 1.5.0 2 7 4 L V T 2 4 0 , 7 4 L V T H 2 4 0 — L o w V o lta g e O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Connection Diagrams Pin Descriptions Logic Symbols IEEE/IEC Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Pin Names Description OE 1 , OE 2 3-STATE Output Enable Inputs I 0 –I 7 Inputs O 0 –O 7 3-STATE Outputs Inputs Outputs (Pins 12, 14, 16, 18)OE 1 I n L L H L H L H X Z Inputs Outputs (Pins 3, 5, 7, 9)OE 2 I n L L H L H L H X Z

Page 5

©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT240, 74LVTH240 Rev. 1.5.0 3 7 4 L V T 2 4 0 , 7 4 L V T H 2 4 0 — L o w V o lta g e O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Note: 1. I O Absolute Maximum Rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Rating V CC Supply Voltage –0.5V to +4.6V V I DC Input Voltage –0.5V to +7.0V V O DC Output Voltage Output in 3-STATE –0.5V to +7.0V Output in HIGH or LOW State (1) –0.5V to +7.0V I IK DC Input Diode Current, V I < GND –50mA I OK DC Output Diode Current, V O < GND –50mA I O DC Output Current, V O > V CC Output at HIGH State 64mA Output at LOW State 128mA I CC DC Supply Current per Supply Pin ±64mA I GND DC Ground Current per Ground Pin ±128mA T STG Storage Temperature –65°C to +150°C Symbol Parameter Min Max Units V CC Supply Voltage 2.7 3.6 V V I Input Voltage 0 5.5 V I OH HIGH-Level Output Current –32 mA I OL LOW-Level Output Current 64 mA T A Free-Air Operating Temperature –40 85 °C ∆ t / ∆ V Input Edge Rate, V IN = 0.8V–2.0V, V CC = 3.0V 0 10 ns/V

Page 6

©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT240, 74LVTH240 Rev. 1.5.0 4 7 4 L V T 2 4 0 , 7 4 L V T H 2 4 0 — L o w V o lta g e O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts DC Electrical Characteristics Notes: 2. All typical values are at V CC = 3.3V, T A = 25°C. 3. Applies to bushold versions only (74LVTH240). 4. An external driver must source at least the specified current to switch from LOW-to-HIGH. 5. An external driver must sink at least the specified current to switch from HIGH-to-LOW. 6. This is the increase in supply current for each input that is at the specified voltage level rather than V CC or GND. Symbol Parameter V CC (V) Conditions T A = –40°C to +85°C UnitsMin. Typ. (2) Max. V IK Input Clamp Diode Voltage 2.7 I I = –18mA –1.2 V V IH Input HIGH Voltage 2.7–3.6 V O ≤ 0.1V or V O ≥ V CC – 0.1V 2.0 V V IL Input LOW Voltage 2.7–3.6 0.8 V V OH Output HIGH Voltage 2.7–3.6 I OH = –100µA V CC –0.2 V 2.7 I OH = –8mA 2.4 3.0 I OH = –32mA 2.0 V OL Output LOW Voltage 2.7 I OL = 100µA 0.2 V I OL = 24mA 0.5 3.0 I OL = 16mA 0.4 I OL = 32mA 0.5 I OL = 64mA 0.55 I I(HOLD) (3) Bushold Input Minimum Drive 3.0 V I = 0.8V 75 µA V I = 2.0V –75 I I(OD) (3) Bushold Input Over-Drive Current to Change State 3.0 (4) 500 µA (5) –500 I I Input Current 3.6 V I = 5.5V 10 µA Control Pins 3.6 V I = 0V or V CC ±1 Data Pins 3.6 V I = 0V –5 VI = VCC 1 IOFF Power Off Leakage Current 0 0V ≤ VI or VO ≤ 5.5V ±100 µA IPU/PD Power up/down 3-STATE Output Current 0–1.5V VO = 0.5V to 3.0V, VI = GND or VCC ±100 µA IOZL 3-STATE Output Leakage Current 3.6 VO = 0.5V –5 µA IOZH 3-STATE Output Leakage Current 3.6 VO = 3.0V 5 µA IOZH+ 3-STATE Output Leakage Current 3.6 VCC < VO ≤ 5.5V 10 µA ICCH Power Supply Current 3.6 Outputs HIGH 0.19 mA ICCL Power Supply Current 3.6 Outputs LOW 5 mA ICCZ Power Supply Current 3.6 Outputs Disabled 0.19 mA ICCZ+ Power Supply Current 3.6 VCC ≤ VO ≤ 5.5V, Outputs Disabled 0.19 mA ∆ICC Increase in Power Supply Current(6) 3.6 One Input at VCC – 0.6V, Other Inputs at VCC or GND 0.2 mA

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©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT240, 74LVTH240 Rev. 1.5.0 5 7 4 L V T 2 4 0 , 7 4 L V T H 2 4 0 — L o w V o lta g e O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Dynamic Switching Characteristics(7) Notes: 7. Characterized in SOIC package. Guaranteed parameter, but not tested. 8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics Notes: 9. All typical values are at VCC = 3.3V, TA = 25°C. 10. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance(11) Note: 11. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. Symbol Parameter VCC (V) Conditions TA = 25°C UnitsCL = 50pF, RL = 500Ω Min. Typ. Max. VOLP Quiet Output Maximum Dynamic VOL 3.3 (8) 0.8 V VOLV Quiet Output Minimum Dynamic VOL 3.3 (8) –0.8 V Symbol Parameter TA = –40°C to +85°C CL = 50pF, RL = 500Ω Units VCC = 3.3V ±0.3V VCC = 2.7V Min. Typ.(9) Max. Min. Max. tPLH Propagation Delay, Data to Output 1.1 3.8 1.1 4.6 ns tPHL 1.3 4.0 1.3 4.2 tPZH Output Enable Time 1.1 4.6 1.1 5.6 ns tPZL 1.4 4.4 1.4 5.1 tPHZ Output Disable Time 2.0 4.5 2.0 4.7 ns tPLZ 1.8 4.3 1.8 4.3 tOSHL, tOSLH Output to Output Skew (10) 1.0 1.0 ns Symbol Parameter Conditions Typical Units CIN Input Capacitance VCC = 0V, VI = 0V or VCC 3 pF COUT Output Capacitance VCC = 3.0V, VO = 0V or VCC 6 pF

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©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT240, 74LVTH240 Rev. 1.5.0 6 7 4 L V T 2 4 0 , 7 4 L V T H 2 4 0 — L o w V o lta g e O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Physical Dimensions Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ 0.10 C C A SEE DETAIL A NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. E) LANDPATTERN STANDARD: SOIC127P1030X265-20L PIN ONE INDICATOR 0.25 1 10 BC AM 20 11 B X 45° 8° 0° SEATING PLANE GAGE PLANE DETAIL A SCALE: 2:1 SEATING PLANE LAND PATTERN RECOMMENDATION F) DRAWING FILENAME: MKT-M20BREV3 0.65 1.27 2.25 9.50 13.00 12.60 11.43 7.60 7.40 10.65 10.00 0.51 0.35 1.27 2.65 MAX 0.30 0.10 0.33 0.20 0.75 0.25 (R0.10) (R0.10) 1.27 0.40 (1.40) 0.25 D) CONFORMS TO ASME Y14.5M-1994

Page 9

©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT240, 74LVTH240 Rev. 1.5.0 7 7 4 L V T 2 4 0 , 7 4 L V T H 2 4 0 — L o w V o lta g e O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Physical Dimensions (Continued) Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/

Page 10

©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT240, 74LVTH240 Rev. 1.5.0 8 7 4 L V T 2 4 0 , 7 4 L V T H 2 4 0 — L o w V o lta g e O c ta l B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts Physical Dimensions (Continued) Figure 3. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/

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