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74VCX16373MTDX

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74VCX16373MTDX

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Part Number 74VCX16373MTDX
Manufacturer Fairchild/ON Semiconductor
Description IC LATCH TRANSP 16BIT LV 48TSSOP
Datasheet 74VCX16373MTDX Datasheet
Package 48-TFSOP (0.240", 6.10mm Width)
In Stock 2,000 piece(s)
Unit Price $ 0.6663 *
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 7 - Aug 12 (Choose Expedited Shipping)
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Part Number # 74VCX16373MTDX (Logic - Latches) is manufactured by Fairchild/ON Semiconductor and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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74VCX16373MTDX Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Latches
Datasheet 74VCX16373MTDXDatasheet
Package48-TFSOP (0.240", 6.10mm Width)
Series74VCX
Logic TypeD-Type Transparent Latch
Circuit8:8
Output TypeTri-State
Voltage - Supply1.2 V ~ 3.6 V
Independent Circuits2
Delay Time - Propagation1.5ns
Current - Output High, Low24mA, 24mA
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case48-TFSOP (0.240", 6.10mm Width)
Supplier Device Package48-TSSOP

74VCX16373MTDX Datasheet

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To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. Is Now Part of ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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© 2005 Fairchild Semiconductor Corporation DS500065 www.fairchildsemi.com October 1997 Revised June 2005 7 4 V C X 1 6 3 7 3 L o w V o lta g e 1 6 -B it T ra n s p a re n t L a tc h w ith 3 .6 V T o le ra n t In p u ts a n d O u tp u ts 74VCX16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs General Description The VCX16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applica- tions. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The 74VCX16373 is designed for low voltage (1.2V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation. Features ■1.2V to 3.6V VCC supply operation ■3.6V tolerant inputs and outputs ■ tPD (In to On) 3.0 ns max for 3.0V to 3.6V VCC ■Power-off high impedance inputs and outputs ■Support live insertion and withdrawal (Note 1) ■Static Drive (IOH/IOL) r24 mA @ 3.0V VCC ■Latch-up performance exceeds 300 mA ■ESD performance: Human body model ! 2000V Machine model ! 200V ■Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Note 2: Ordering Code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Order Number Package Number Package Description 74VCX16373G (Note 2)(Note 3) BGA54A (Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74VCX16373MTD (Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide ■Uses proprietary noise/EMI reduction circuitry

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www.fairchildsemi.com 2 7 4 V C X 1 6 3 7 3 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) Pin Descriptions FBGA Pin Assignments Truth Tables H HIGH Voltage Level L LOW Voltage Level X Immaterial (HIGH or LOW, inputs may not float) Z High Impedance O0 Previous O0 before HIGH-to-LOW of Latch Enable Pin Names Description OEn Output Enable Input (Active LOW) LEn Latch Enable Input I0–I15 Inputs O0–O15 Outputs NC No Connect 1 2 3 4 5 6 A O0 NC OE1 LE1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 G O12 O11 VCC VCC I11 I12 H O14 O13 NC NC I13 I14 J O15 NC OE2 LE2 NC I15 Inputs Outputs LE1 OE1 I0–I7 O0–O7 X H X Z H L L L H L H H L L X O0 Inputs Outputs LE2 OE2 I8–I15 O8–O15 X H X Z H L L L H L H H L L X O0

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3 www.fairchildsemi.com 7 4 V C X 1 6 3 7 3 Functional Description The 74VCX16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable (OEn) input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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www.fairchildsemi.com 4 7 4 V C X 1 6 3 7 3 Absolute Maximum Ratings(Note 4) Recommended Operating Conditions (Note 6) Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat- ings. The “Recommended Operating Conditions” table will define the condi- tions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused inputs must be held HIGH or LOW. DC Electrical Characteristics Supply Voltage (VCC) 0.5V to 4.6V DC Input Voltage (VI) 0.5V to 4.6V Output Voltage (VO) Outputs 3-STATED 0.5V to 4.6V Outputs Active (Note 5) 0.5V to VCC 0.5V DC Input Diode Current (IIK) VI  0V 50 mA DC Output Diode Current (IOK) VO  0V 50 mA VO ! VCC 50 mA DC Output Source/Sink Current (IOH/IOL) r50 mA DC VCC or GND Current per Supply Pin (ICC or GND) r100 mA Storage Temperature Range (TSTG) 65qC to 150qC Power Supply Operating 1.2V to 3.6V Input Voltage 0.3V to 3.6V Output Voltage (VO) Output in Active States 0.0V to VCC Output in “OFF” State 0.0V to 3.6V Output Current in IOH/IOL VCC 3.0V to 3.6V r24 mA VCC 2.3V to 2.7V r18 mA VCC 1.65V to 2.3V r6 mA VCC 1.4V to 1.6V r2 mA VCC 1.2V r100 mA Free Air Operating Temperature (TA) 40qC to 85qC Minimum Input Edge Rate ('t/'V) VIN 0.8V to 2.0V, VCC 3.0V 10 ns/V Symbol Parameter Conditions VCC Min Max Units (V) VIH HIGH Level Input Voltage 2.7 - 3.6 2.0 V 2.3 - 2.7 1.6 1.65 - 2.3 0.65 u VCC 1.4 - 1.6 0.65 u VCC 1.2 0.65 u VCC VIL LOW Level Input Voltage 2.7 - 3.6 0.8 V 2.3 - 2.7 0.7 1.65 - 2.3 0.35 u VCC 1.4 - 1.6 0.35 u VCC 1.2 0.15 x VCC VOH HIGH Level Output Voltage IOH 100 PA 2.7 - 3.6 VCC  0.2 V IOH 12 mA 2.7 2.2 IOH 18 mA 3.0 2.4 IOH 24 mA 3.0 2.2 IOH 100 PA 2.3 - 2.7 VCC  0.2 IOH 6 mA 2.3 2.0 IOH 12 mA 2.3 1.8 IOH 18 mA 2.3 1.7 IOH 100 PA 1.65 - 2.3 VCC  0.2 IOH 6 mA 1.65 1.25 IOH 100 PA 1.4 - 1.6 VCC  0.2 IOH 2 mA 1.4 1.05 IOH 100 PA 1.2 VCC  0.2

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5 www.fairchildsemi.com 7 4 V C X 1 6 3 7 3 DC Electrical Characteristics (Continued) Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics (Note 8) Symbol Parameter Conditions VCC Min Max Units (V) VOL LOW Level Output Voltage IOL 100 PA 2.7 - 3.6 0.2 V IOL 12 mA 2.7 0.4 IOL 18 mA 3.0 0.4 IOL 24 mA 3.0 0.55 IOL 100 PA 2.3 - 2.7 0.2 IOL 12 mA 2.3 0.4 IOL 18 mA 2.3 0.6 IOL 100 PA 1.65 - 2.3 0.2 IOL 6 mA 1.65 0.3 IOL 100 PA 1.4 - 1.6 0.2 IOL 2 mA 1.4 0.35 IOL 100 PA 1.2 0.05 II Input Leakage Current 0 d VI d 3.6V 1.2 - 3.6 r5.0 PA IOZ 3-STATE Output Leakage 0 d VO d 3.6V 1.2 - 3.6 r10.0 PA VI VIH or VIL IOFFI Power-OFF Leakage Current 0 d (VI, VO) d 3.6V 0 10.0 PA ICC Quiescent Supply Current VI VCC or GND 1.2 - 3.6 20.0 PA VCC d (VI, VO) d 3.6V (Note 7) 1.2 - 3.6 r20.0 'ICC Increase in ICC per Input VIH VCC 0.6V 2.7 - 3.6 750 PA Symbol Parameter Conditions VCC TA 40qC to 85qC, Units Figure (V) Min Max Number tPHL, tPLH Propagation Delay CL 30 pF, RL 500: 3.3 r 0.3 0.8 3.0 ns Figures 1, 2 LE to On 2.5 r 0.2 1.0 3.9 1.8 r 0.15 1.5 7.8 CL 15 pF, RL 2k: 1.5 r 0.1 1.0 15.6 ns Figures 7, 81.2 1.5 39.0 tPHL, tPLH Propagation Delay CL 30 pF, RL 500: 3.3 r 0.3 0.8 3.0 ns Figures 1, 2 In to On 2.5 r 0.2 1.0 3.4 1.8 r 0.15 1.5 6.8 CL 15 pF, RL 2k: 1.5 r 0.1 1.0 13.6 ns Figures 7, 81.2 1.5 34.0 tPZL, tPZH Output Enable Time CL 30 pF, RL 500: 3.3 r 0.3 0.8 3.5 ns Figures 1, 3, 4 2.5 r 0.2 1.0 4.6 1.8 r 0.15 1.5 9.2 CL 15 pF, RL 2k: 1.5 r 0.1 1.0 18.4 ns Figures 7, 9, 101.2 1.5 46.0 tPLZ, tPHZ Output Disable Time CL 30 pF, RL 500: 3.3 r 0.3 0.8 3.5 ns Figures 1, 3, 4 2.5 r 0.2 1.0 3.8 1.8 r 0.15 1.5 6.8 CL 15 pF, RL 2k: 1.5 r 0.1 1.0 13.6 ns Figures 7, 9, 101.2 1.5 34.0 TS Setup Time CL 30 pF, RL 500: 3.3 r 0.3 1.5 ns Figures 1, 6 2.5 r 0.2 1.5 1.8 r 0.15 2.5 CL 15 pF, RL 2k: 1.5 r 0.1 3.0 ns Figures 6, 71.2 6.0

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www.fairchildsemi.com 6 7 4 V C X 1 6 3 7 3 AC Electrical Characteristics (Continued) Note 8: For CL 50PF, add approximately 300 ps to the AC maximum specification. Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Capacitance Symbol Parameter Conditions VCC TA 40qC to 85qC, Units Figure (V) Min Max Number TH Hold Time CL 30 pF, RL 500: 3.3 r 1.0 1.0 ns Figures 1, 6 2.5 r 0.2 1.0 1.8 r 0.15 1.0 CL 15 pF, RL 2k: 1.5 r 0.1 1.2 ns Figures 6, 71.2 3.6 TW Pulse Width CL 30 pF, RL 500: 3.3 r 0.3 1.5 ns Figures 1, 4 2.5 r 0.2 1.5 1.8 r 0.15 4.0 CL 15 pF, RL 2k: 1.5 r 0.1 4.0 ns Figures 4, 71.2 8.0 tOSHL Output to Output Skew CL 30 pF, RL 500: 3.3 r 0.3 0.5 ns tOSLH (Note 9) 2.5 r 0.2 0.5 1.8 r 0.15 0.75 CL 15 pF, RL 2k: 1.5 r 0.1 1.5 1.2 1.5 Symbol Parameter Conditions VCC TA 25qC Units (V) Typical VOLP Quiet Output Dynamic Peak VOL CL 30 pF, VIH VCC, VIL 0V 1.8 0.25 V2.5 0.6 3.3 0.8 VOLV Quiet Output Dynamic Valley VOL CL 30 pF, VIH VCC, VIL 0V 1.8 0.25 V2.5 0.6 3.3 0.8 VOHV Quiet Output Dynamic Valley VOH CL 30 pF, VIH VCC, VIL 0V 1.8 1.5 V2.5 1.9 3.3 2.2 Symbol Parameter Conditions TA 25qC Units Typical CIN Input Capacitance VCC 1.8V, 2.5V or 3.3V, VI 0V or VCC 6.0 pF COUT Output Capacitance VI 0V or VCC, VCC 1.8V, 2.5V or 3.3V 7.0 pF CPD Power Dissipation Capacitance VI 0V or VCC, f 10 MHz, 20.0 pF VCC 1.8V, 2.5V or 3.3V

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7 www.fairchildsemi.com 7 4 V C X 1 6 3 7 3 AC Loading and Waveforms (VCC 3.3V  0.3V to 1.8V  0.15V) FIGURE 1. AC Test Circuit FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC 3.3 r 0.3V; VCC x 2 at VCC 2.5 r 0.2V; 1.8V r 0.15V tPZH, tPHZ GND Symbol VCC 3.3V r 0.3V 2.5V r 0.2V 1.8V r 0.15V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VX VOL  0.3V VOL  0.15V VOL  0.15V VY VOH  0.3V VOH  0.15V VOH  0.15V

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www.fairchildsemi.com 8 7 4 V C X 1 6 3 7 3 AC Loading and Waveforms (VCC 1.5  0.1V to 1.2V) FIGURE 7. AC Test Circuit FIGURE 8. Waveform for Inverting and Non-Inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VCC x 2 at VCC 1.5 r 0.1V tPZH, tPHZ GND Symbol VCC 1.5V r 0.1V Vmi VCC/2 Vmo VCC/2 VX VOL  0.1V VY VOH  0.1V

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Uri*****Olson

July 10, 2020

I tested some and all look good.

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June 19, 2020

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June 18, 2020

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June 13, 2020

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June 12, 2020

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June 11, 2020

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June 4, 2020

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May 30, 2020

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May 30, 2020

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