74VHC132M

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7 4 V H C 1 3 2 — Q u a d 2 -In p u t N A N D S c h m itt T rig g e r ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC132 Rev. 1.5.0 December 2007 74VHC132 Quad 2-Input NAND Schmitt Trigger Features ■ High Speed: t PD = 3.9ns (Typ.) at V CC = 5V ■ Power down protection is provided on all inputs ■ Low power dissipation: I CC = 2µA (Max.) at T A = 25°C ■ Low noise: V OLP = 0.8V (Max.) ■ Pin and function compatible with 74HC132 General Description The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the VHC00 but the inputs have hysteresis between the positive-going and negative- going input thresholds, which are capable of transform- ing slowly changing input signals into sharply defined, jitter-free output signals. Thus greater noise margin then conventional gates is provided. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Package Number Package Description 74VHC132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC132 Rev. 1.5.0 2 7 4 V H C 1 3 2 — Q u a d 2 -In p u t N A N D S c h m itt T rig g e r Connection Diagram Pin Description Logic Diagram Truth Table Pin Names Description A n , B n Inputs Y n Outputs A B Y L L H L H H H L H H H L

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC132 Rev. 1.5.0 3 7 4 V H C 1 3 2 — Q u a d 2 -In p u t N A N D S c h m itt T rig g e r Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Recommended Operating Conditions (1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Note: 1. Unused inputs must be held HIGH or LOW. They may not float. Symbol Parameter Rating V CC Supply Voltage –0.5V to +7.0V V IN DC Input Voltage –0.5V to +7.0V V OUT DC Output Voltage –0.5V to V CC + 0.5V I IK Input Diode Current –20mA I OK Output Diode Current ±20mA I OUT DC Output Current ±25mA I CC DC V CC / GND Current ±50mA T STG Storage Temperature –65°C to +150°C T L Lead Temperature (Soldering, 10 seconds) 260°C Symbol Parameter Rating V CC Supply Voltage 2.0V to +5.5V V IN Input Voltage 0V to +5.5V V OUT Output Voltage 0V to V CC T OPR Operating Temperature –40°C to +85°C

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC132 Rev. 1.5.0 4 7 4 V H C 1 3 2 — Q u a d 2 -In p u t N A N D S c h m itt T rig g e r DC Electrical Characteristics Noise Characteristics Note: 2. Parameter guaranteed by design. Symbol Parameter V CC (V) Conditions T A = 25°C T A = –40°C to +85°C UnitsMin. Typ. Max. Min. Max. V P Positive Threshold Voltage 3.0 2.20 2.20 V 4.5 3.15 3.15 5.5 3.85 3.85 V N Negative Threshold Voltage 3.0 0.90 0.90 V 4.5 1.35 1.35 5.5 1.65 1.65 V H Hysteresis Output Voltage 3.0 0.30 1.20 0.30 1.20 V 4.5 0.40 1.40 0.40 1.40 5.5 0.50 1.60 0.50 1.60 V OH HIGH Level Output Voltage 2.0 V IN = V IH or V IL I OH = –50µA 1.9 2.0 1.9 V 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 I OH = –4mA 2.58 2.48 4.5 I OH = –8mA 3.94 3.80 V OL LOW Level Output Voltage 2.0 V IN = V IH or V IL I OL = 50µA 0.0 0.1 0.1 V 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 3.0 I OL = 4mA 0.36 0.44 4.5 I OL = 8mA 0.36 0.44 I IN Input Leakage Current 0–5.5 V IN = 5.5V or GND ±0.1 ±1.0 µA I CC Quiescent Supply Current 5.5 V IN = V CC or GND 2.0 20.0 µA Symbol Parameter V CC (V) Conditions T A = 25°C UnitsTyp. Limits V OLP (2) Quiet Output Maximum Dynamic V OL 5.0 C L = 50pF 0.3 0.8 V V OLV (2) Quiet Output Maximum Dynamic V OL 5.0 C L = 50pF –0.3 –0.8 V V IHD (2) Maximum HIGH Level Dynamic Input Voltage 5.0 C L = 50pF 3.5 V V ILD (2) Maximum LOW Level Dynamic Input Voltage 5.0 C L = 50pF 1.5 V

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©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC132 Rev. 1.5.0 5 7 4 V H C 1 3 2 — Q u a d 2 -In p u t N A N D S c h m itt T rig g e r AC Electrical Characteristics Note: 3. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: I CC (Opr.) = C PD • V CC • I IN + I CC / 4 (per gate) Symbol Parameter V CC (V) Conditions T A = 25°C T A = –40°C to +85°C UnitsMin. Typ. Max. Min. Max. t PHL , t PLH Propagation Delay 3.3 ± 0.3 C L = 15pF 6.1 11.9 1.0 14.0 ns C L = 50pF 8.0 15.4 1.0 17.5 5.0 ± 0.5 C L = 15pF 3.9 7.7 1.0 9.0 CL = 50pF 5.9 9.7 1.0 11.0 CIN Input Capacitance VCC = Open 4 10 10 pF CPD Power Dissipation Capacitance (3) 16 pF

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FRONT VIEW TOP VIEW ALL LEAD TIPS NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 2009. E. LANDPATTERN STANDARD: SOP65P640X110-14M. F. DRAWING FILE NAME: MKT-MTC14rev7. 0.43TYP 0.2 C B A 8 1 7 14 A B 3.2 6.4 PIN#1 IDENT 1.2 MAX 0.1 C ALL LEAD TIPS C 0.65 0.30 0.19 0.13 A B C 0.90 +0.15 -0.10 0.20 0.09 SEE DETAIL A GAGE PLANE 0.25 SEATING PLANE 0.09 MIN 0.09 MIN 1.00 DETAIL A RECOMMENDED LAND PATTERN 6.10 0.65 1.65 0.45

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1.70 5.60 1.27 0.65 1.501.25 1.75 MAX 0.250.10 C 4.003.80 8.758.50 6.00 (0.33) 0.510.35 7.62 1.27 1 PIN #1 IDENT. A B 0.250.19 A 0.500.25 x 45 R0.10 R0.10 (1.04) 0.36 8°0° 0.900.50 DETAIL A SCALE 16 : 1 GAGE PLANE SEATING PLANE TOP VIEW FRONT VIEW SIDE VIEW 14 7 8 1 7 8 LAND PATTERN RECOMMENDATION NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS D. LAND PATTERN STANDARD: SOIC127P600X145-14M E. CONFORMS TO ASME Y14.5M, 2009 D. DRAWING FILENAME: MKT-M14Arev14 14 0.10 C 0.25 M C B A