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A1020B-PL84I

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A1020B-PL84I

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Part Number A1020B-PL84I
Manufacturer Microsemi Corporation
Description IC FPGA 69 I/O 84PLCC
Datasheet A1020B-PL84I Datasheet
Package 84-LCC (J-Lead)
In Stock 563 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 26 - Oct 1 (Choose Expedited Shipping)
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Part Number # A1020B-PL84I (Embedded - FPGAs (Field Programmable Gate Array)) is manufactured by Microsemi Corporation and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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A1020B-PL84I Specifications

ManufacturerMicrosemi Corporation
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet A1020B-PL84IDatasheet
Package84-LCC (J-Lead)
SeriesACT? 1
Number of LABs/CLBs547
Number of Logic Elements/Cells-
Total RAM Bits-
Number of I/O69
Number of Gates2000
Voltage - Supply4.5 V ~ 5.5 V
Mounting TypeSurface Mount
Operating Temperature-40°C ~ 85°C (TA)
Package / Case84-LCC (J-Lead)
Supplier Device Package84-PLCC (29.31x29.31)

A1020B-PL84I Datasheet

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ACT™ 1 Series FPGAsFeatures • 5V and 3.3V Families fully compatible with JEDEC specifications • Up to 2000 Gate Array Gates (6000 PLD equivalent gates) • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL® Packages • Design Library with over 250 Macro Functions • Gate Array Architecture Allows Completely Automatic Place and Route • Up to 547 Programmable Logic Modules • Up to 273 Flip-Flops • Data Rates to 75 MHz • Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 25 MHz • Built-In High Speed Clock Distribution Network • I/O Drive to 10 mA (5 V), 6 mA (3.3 V) • Nonvolatile, User Programmable • Fabricated in 1.0 micron CMOS technology Description The ACT™ 1 Series of field programmable gate arrays (FPGAs) offers a variety of package, speed, and application combinations. Devices are implemented in silicon gate, 1-micron two-level metal CMOS, and they employ Actel’s PLICE® antifuse technology. The unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. Device utilization is typically 95 to 100 percent of available logic modules. ACT 1 devices also provide system designers with unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. Additional features include an on-chip clock driver with a hardwired distribution network. The network provides efficient clock distribution with minimum skew. The user-definable I/Os are capable of driving at both TTL and CMOS drive levels. Available packages include plastic and ceramic J-leaded chip carriers, ceramic and plastic quad flatpacks, and ceramic pin grid array. A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. Product Family Profile The Designer and Designer Advantage™ Systems The ACT 1 device family is supported by Actel’s Designer and Designer Advantage Systems, allowing logic design implementation with minimum effort. The systems offer Microsoft® Windows™ and X Windows™ graphical user interfaces and integrate with the resident CAE system to provide a complete gate array design environment: schematic capture, simulation, fully automatic place and route, timing verification, and device programming. The systems also include the ACTmap™ VHDL optimization and synthesis tool and the ACTgen™ Macro Builder, a powerful macro function generator for counters, adders, and other structural blocks. Device A1010B A10V10B A1020B A10V20B Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages 1,200 3,000 30 12 2,000 6,000 50 20 Logic Modules 295 547 Flip-Flops (maximum) 147 273 Routing Resources Horizontal Tracks/Channel Vertical Tracks/Column PLICE Antifuse Elements 22 13 112,000 22 13 186,000 User I/Os (maximum) 57 69 Packages: 44 PLCC 68 PLCC 100 PQFP 80 VQFP 84 CPGA 44 PLCC 68 PLCC 84 PLCC 100 PQFP 80 VQFP 84 CPGA 84 CQFP Performance 5 V Data Rate (maximum) 3.3 V Data Rate (maximum) 75 MHz 55 MHz 75 MHz 55 MHz Note: See Product Plan on page 1-286 for package availability.April 1996 1-283 © 1996 Actel Corporation

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The systems are available for 386/486/Pentium™ PC and for HP™ and Sun™ workstations and for running Viewlogic®, Mentor Graphics®, Cadence™, OrCAD™, and Synopsys design environments. ACT 1 Device Structure A partial view of an ACT 1 device (Figure 1) depicts four logic modules and distributed horizontal and vertical interconnect tracks. PLICE antifuses, located at intersections of the horizontal and vertical tracks, connect logic module inputs and outputs. During programming, these antifuses are addressed and programmed to make the connections required by the circuit application. The ACT 1 Logic Module The ACT 1 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources (Figure 2). The logic module can implement the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions, with different combinations of active-low inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs, and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the array, since latches and flip-flops may be constructed from logic modules wherever needed in the application. I/O Buffers Each I/O pin is available as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Outputs sink or Figure 1 • Partial View of an ACT 1 Device Figure 2 • ACT 1 Logic Module1-284

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ACT ™ 1 Series FPGAs source 10 mA at TTL levels. See Electrical Specifications for additional I/O buffer specifications. Device Organization ACT 1 devices consist of a matrix of logic modules arranged in rows separated by wiring channels. This array is surrounded by a ring of peripheral circuits including I/O buffers, testability circuits, and diagnostic probe circuits providing real-time diagnostic capability. Between rows of logic modules are routing channels containing sets of segmented metal tracks with PLICE antifuses. Each channel has 22 signal tracks. Vertical routing is permitted via 13 vertical tracks per logic module column. The resulting network allows arbitrary and flexible interconnections between logic modules and I/O modules. Probe Pin ACT 1 devices have two independent diagnostic probe pins. These pins allow the user to observe any two internal signals by entering the appropriate net name in the diagnostic software. Signals may be viewed on a logic analyzer using Actel’s Actionprobe® diagnostic tools. The probe pins can also be used as user-defined I/Os when debugging is finished. ACT 1 Array Performance Temperature and Voltage Effects Worst-case delays for ACT 1 arrays are calculated in the same manner as for masked array products. A typical delay parameter is multiplied by a derating factor to account for temperature, voltage, and processing effects. However, in an ACT 1 array, temperature and voltage effects are less dramatic than with masked devices. The electrical characteristics of module interconnections on ACT 1 devices remain constant over voltage and temperature fluctuations. As a result, the total derating factor from typical to worst-case for a standard speed ACT 1 array is only 1.19 to 1, compared to 2 to 1 for a masked gate array. Logic Module Size Logic module size also affects performance. A mask programmed gate array cell with four transistors usually implements only one logic level. In the more complex logic module (similar to the complexity of a gate array macro) of an ACT 1 array, implementation of multiple logic levels within a single module is possible. This eliminates interlevel wiring and associated RC delays. The effect is termed “net compression.” Ordering Information Application (Temperature Range) C = Commercial (0 to +70° C) I = Industrial (–40 to +85° C) M = Military (–55 to +125° C) B = MIL-STD-883 Package Type PL = Plastic J-Leaded Chip Carriers PQ = Plastic Quad Flatpacks CQ = Ceramic Quad Flatpack PG = Ceramic Pin Grid Array VQ = Very Thin Quad Flatpack Speed Grade Blank = Standard Speed –1 = Approximately 15% faster than Standard –2 = Approximately 25% faster than Standard –3 = Approximately 35% faster than Standard Part Number A1010 = 1200 Gates (5 V) A1020 = 2000 Gates (5 V) A10V10 = 1200 Gates (3.3 V) A10V20 = 2000 Gates (3.3 V) Die Revision B = 1.0 micron CMOS Process Package Lead Count A1010 B – 2 PL 84 C1-285

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Product Plan Speed Grade* Application Std –1 –2 –3 C I M B A1010B Device 44-pin Plastic Leaded Chip Carrier (PL) 68-pin Plastic Leaded Chip Carrier (PL) 100-pin Plastic Quad Flatpack (PQ) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) 84-pin Ceramic Pin Grid Array (PG) ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — ✔ ✔ ✔ ✔ — ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — — — — — — ✔ — — — — ✔ A1020B Device 44-pin Plastic Leaded Chip Carrier (PL) 68-pin Plastic Leaded Chip Carrier (PL) 84-pin Plastic Leaded Chip Carrier (PL) 100-pin Plastic Quad Flatpack (PQ) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) 84-pin Ceramic Pin Grid Array (PG) 84-pin Ceramic Quad Flatpack (CQ) ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — — ✔ ✔ ✔ ✔ ✔ — — ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — — — — — — — — ✔ ✔ — — — — — ✔ ✔ A10V10B Device 68-pin Plastic Leaded Chip Carrier (PL) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) ✔ ✔ — — — — — — ✔ ✔ — — — — — — A10V20B Device 68-pin Plastic Leaded Chip Carrier (PL) 84-pin Plastic Leaded Chip Carrier (PL) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) ✔ ✔ ✔ — — — — — — — — — ✔ ✔ ✔ — — — — — — — — — Applications: C = Commercial Availability: ✔ = Available * Speed Grade: –1 = Approx. 15% faster than Standard I = Industrial P = Planned –2 = Approx. 25% faster than Standard M = Military — = Not Planned –3 = Approx. 35% faster than Standard B = MIL-STD-883 Device Resources User I/Os Device Logic Modules Gates 44-pin 68-pin 80-pin 84-pin 100-pin A1010B, A10V10B 295 1200 34 57 57 57 57 A1020B, A10V20B 547 2000 34 57 69 69 691-286

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ACT ™ 1 Series FPGAs Pin Description CLK Clock (Input) TTL Clock input for global clock distribution network. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. GND Ground Input LOW supply voltage. I/O Input/Output (Input, Output) I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the ALS software. MODE Mode (Input) The MODE pin controls the use of multifunction pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/O. To provide Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled high when required. NC No Connection This pin is not connected to circuitry within the device. Absolute Maximum Ratings1 Free air temperature range PRA Probe A (Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect the programmed design’s confidentiality. PRA is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. PRB Probe B (Output) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect the programmed design’s confidentiality. PRB is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDI Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. VCC Supply Voltage Input HIGH supply voltage. Recommended Operating Conditions Symbol Parameter Limits Units VCC DC Supply Voltage 2 –0.5 to +7.0 Volts VI Input Voltage –0.5 to VCC +0.5 Volts VO Output Voltage –0.5 to VCC +0.5 Volts IIO I/O Sink/Source Current3 ± 20 mA TSTG Storage Temperature –65 to +150 ° C Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. VPP = VCC , except during device programming. 3. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5 V, the internal protection diode will be forward biased and can draw excessive current. Parameter Commercial Industrial Military Units Temperature Range1 0 to +70 –40 to +85 –55 to +125 ° C Power Supply Tolerance ± 5 ± 10 ± 10 %VCC Note: 1. Ambient temperature (TA) used for commercial and industrial; case temperature (TC) used for military.1-287

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Electrical Specifications (5V) Symbol Parameter Commercial Industrial Military UnitsMin. Max. Min. Max. Min. Max. VOH 1 (IOH = –10 mA) 2 2.4 V (IOH = –6 mA) 3.84 V (IOH = –4 mA) 3.7 3.7 V VOL 1 (IOL = 10 mA) 2 0.5 V (IOL = 6 mA) 0.33 0.40 0.40 V VIL –0.3 0.8 –0.3 0.8 –0.3 0.8 V VIH 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V Input Transition Time tR, tF 2 500 500 500 ns CIO I/O Capacitance 2, 3 10 10 10 pF Standby Current, ICC 4 (typical = 1 mA) 3 10 20 mA Leakage Current5 –10 10 –10 10 –10 10 µ A Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 4. Typical standby current = 1 mA. All outputs unloaded. All inputs = VCC or GND. 5. VO , VIN = VCC or GND. Electrical Specifications (3.3V) Parameter Commercial Units Min. Max. VOH 1 (IOH = –4 mA) 2.15 V (IOH = –3.2 mA) 2.4 V VOL 1 (IOL = 6 mA) 0.4 V VIL –0.3 0.8 V VIH 2.0 VCC + 0.3 V Input Transition Time tR, tF 2 500 ns CIO I/O Capacitance 2, 3 10 pF Standby Current, ICC 4 (typical = 0.3 mA) 0.75 mA Leakage Current5 –10 10 µ A Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND. 5. VO, VIN = VCC or GND1-288

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ACT™ 1 Series FPGAsPackage Thermal Characteristics The device junction to case thermal characteristics is θ jc, and the junction to ambient air characteristics is θ ja. The thermal characteristics for θ ja are shown with two different air flow rates. Maximum junction temperature is 150° C. A sample calculation of the maximum power dissipation for an 84-pin plastic leaded chip carrier at commercial temperature is as follows: General Power Equation P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH * (VCC – VOH) * M Where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the family type, design details, and on the system I/O. The power can be divided into two components: static and active. Static Power Component Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions. ICC VCC Power 3 mA 5.25 V 15.75 mW (max) 1 mA 5.25 V 5.25 mW (typ) 0.75 mA 3.60 V 2.70 mW (max) 0.30 mA 3.30 V 0.99 mW (typ) Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. Package Type Pin Count θ jc θ ja Still Air θ ja 300 ft/min Units Plastic J-Leaded Chip Carrier 44 68 84 15 13 12 45 38 37 35 29 28 ° C/W ° C/W ° C/W Plastic Quad Flatpack 100 13 48 40 ° C/W Very Thin (1.0 mm) Quad Flatpack 80 12 43 35 ° C/W Ceramic Pin Grid Array 84 8 33 20 ° C/W Ceramic Quad Flatpack 84 5 40 30 ° C/W Max junction temp. ° C ( ) Max commercial temp. ° C ( ) – θ ja ° C W ⁄( ) ------------------------------------------------------------------------------------------------------------------------------------------------- 150 ° C 70 ° C– 37 ° C W ⁄ ---------------------------------- 2.2 W= =1-289

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Equivalent Capacitance The power dissipated by a CMOS circuit can be expressed by the Equation 1. Power (uW) = C EQ * V CC2 * F (1) Where: C EQ is the equivalent capacitance expressed in pF. V CC is the power supply in volts. F is the switching frequency in MHz. Equivalent capacitance is calculated by measuring I CC active at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of V CC . Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C EQ Values for Actel FPGAs To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Power = V CC 2 * [(m * C EQM * f m ) modules + (n * C EQI * f n ) inputs + (p * (C EQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1] (2) Where: Fixed Capacitance Values for Actel FPGAs (pF) r1 Device Type routed_Clk1 A1010B 41.4 A1020B 68.6 A10V10B 40 A10V20B 65 Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: A10V10B A10V20B A1010B A1020B Modules (CEQM) 3.2 3.7 Input Buffers (CEQI) 10.9 22.1 Output Buffers (CEQO) 11.6 31.2 Routed Array Clock Buffer Loads (CEQCR) 4.1 4.6 m = Number of logic modules switching at fm n = Number of input buffers switching at fn p = Number of output buffers switching at fp q1 = Number of clock loads on the first routed array clock (All families) r1 = Fixed capacitance due to first routed array clock (All families) CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CL = Output lead capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average first routed array clock rate in MHz (All families) Logic Modules (m) 90% of modules Inputs switching (n) #inputs/4 Outputs switching (p) #outputs/4 First routed array clock loads (q1) 40% of modules Load capacitance (CL) 35 pF Average logic module switching rate (fm) F/10 Average input switching rate (fn) F/5 Average output switching rate (fp) F/10 Average first routed array clock rate (fq1) F 1-290

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ACT™ 1 Series FPGAsFunctional Timing Tests AC timing for logic module internal delays is determined after place and route. The DirectTime Analyzer utility displays actual timing parameters for circuit delays. ACT 1 devices are AC tested to a “binning” circuit specification. The circuit consists of one input buffer + n logic modules + one output buffer (n = 16 for A1010B; n = 28 for A1020B). The logic modules are distributed along two sides of the device, as inverting or non-inverting buffers. The modules are connected through programmed antifuses with typical capacitive loading. Propagation delay [tPD = (tPLH + tPHL)/2] is tested to the following AC test specifications. Output Buffer Performance Derating (5V) Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices. Output Buffer Performance Derating (3.3V) Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices. Sink 12 10 8 6 4 0.2 0.3 0.4 0.5 0.6 VOL (Volts) I O L ( m A ) Source –4 –6 –8 –10 –12 4.0 3.6 3.2 2.8 2.4 VOH (Volts) I O H ( m A ) 2.0 Military, worst-case values at 125° C, 4.5 V. Commercial, worst-case values at 70° C, 4.75 V. Sink 12 10 8 6 4 0.0 0.1 0.2 0.3 0.4 VOL (Volts) I O L ( m A ) Source –4 –6 –8 –10 –12 0 0.5 1.0 1.5 2.0 VOH (Volts) I O H ( m A ) 2.5 Commercial, worst-case values at 70° C, 4.75 V.1-291

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Alber*****nters

August 22, 2020

Great price. Worked well for my needs.

Mark*****hauhan

August 21, 2020

Used these for a solar project, and they are working great.

Adel*****Reyna

August 16, 2020

Very happy for the fast shipping and good price!

Noel*****tillo

August 9, 2020

Very easy to co-operate with; they take care of orders promptly.

Pais*****More

August 6, 2020

Very easy to find and order what I wanted. Being able to add multiple items in various quantities from an online catalog page with a simple click.

Darw*****hingra

July 31, 2020

On time and as described, fast delivery. Would definitely buy again. Thx.

Jac***** Loke

July 31, 2020

The helper is super handy, especially if you work with medium size PCB boards as it allows to hold the board steady in every position. It feels pretty sturdy and of good quality.

Brun*****audry

July 23, 2020

To be honest, you're beating your competitor on delivery - sometimes I request 2nd day and you still get it here overnight. Thanks!

Jay*****Mack

July 23, 2020

the parts work as they should. Amazing price perfect all round many thanks

Ala*****elly

July 8, 2020

Great seller, would recommend buying from. , good communication and problem solving

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