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AD1940YSTZRL

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AD1940YSTZRL

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Part Number AD1940YSTZRL
Manufacturer Analog Devices Inc.
Description IC DSP AUDIO 16CH/28BIT 48-LQFP
Datasheet AD1940YSTZRL Datasheet
Package 48-LQFP
In Stock 574 piece(s)
Unit Price $ 7.9488 *
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 2 - Dec 7 (Choose Expedited Shipping)
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Part Number # AD1940YSTZRL (Data Acquisition - ADCs/DACs - Special Purpose) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD1940YSTZRL Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - ADCs/DACs - Special Purpose
Datasheet AD1940YSTZRLDatasheet
Package48-LQFP
SeriesSigmaDSP?
TypeAudio
Number of Channels-
Resolution (Bits)28 b
Sampling Rate (Per Second)192k
Data InterfaceSPI
Voltage Supply SourceSingle Supply
Voltage - Supply2.25 V ~ 2.75 V
Operating Temperature-40°C ~ 125°C
Mounting TypeSurface Mount
Package / Case48-LQFP
Supplier Device Package48-LQFP (7x7)

AD1940YSTZRL Datasheet

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SigmaDSP Multichannel 28-Bit Audio Processor AD1940/AD1941 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113©2004–2010 Analog Devices, Inc. All rights reserved. FEATURES 16-channel digital audio processor Accepts sample rates up to 192 kHz 28-bit × 28-bit multiplier with full 56-bit accumulator Fully programmable program RAM for custom program download Parameter RAM allows complete control of 1,024 parameters Control port features safeload for transparent parameter updates and complete mode and memory transfer control Target/slew RAM for click-free volume control and dynamic parameter updates Double precision mode for full 56-bit processing PLL for generating MCLK from 64 × fS, 256 × fS, 384 × fS, or 512 × fS clocks Hardware-accelerated DSP core 21 kB (6,144 words) data memory for up to 128 ms of audio delay at fs = 48 kHz Flexible serial data port with I2S-compatible, left-justified, and right-justified serial port modes 8- and 16-channel TDM input/output modes On-chip voltage regulator for compatibility with 3.3 V and 5 V systems Programmable low power mode Fast start-up and boot time from power-on or reset 48-lead LQFP plastic package APPLICATIONS Automotive sound systems Digital televisions Home theater systems (Dolby digital/DTS postprocessor) Multichannel audio systems Mini-component stereos Multimedia audio Digital speaker crossover Musical instruments In-seat sound systems (aircrafts/motor coaches) FUNCTIONAL BLOCK DIAGRAM VOLTAGE REGULATOR AD1940/AD1941 28 × 28 DSP CORE DATA FORMAT: PLL SERIAL CONTROL INTERFACE SERIAL DATA/ TDM INPUTS MASTER CLOCK INPUT SPI/I2C I/O RAM ROM SERIAL DATA/ TDM OUTPUTS 04 60 7- 0- 00 1 2 4 4 2 2 5.23 (SINGLE PRECISION) 10.46 (DOUBLE PRECISION) Figure 1. GENERAL DESCRIPTION The AD1940/AD1941 are a complete 28-bit, single-chip, multi- channel audio SigmaDSP™ for equalization, multiband dynamic processing, delay compensation, speaker compensation, and image enhancement. These algorithms can be used to compen- sate for the real world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of perceived audio quality. The signal processing used in the AD1940/AD1941 is comparable to that found in high end studio equipment. Most of the processing is done in full, 56-bit double-precision mode, resulting in very good, low level signal performance and the absence of limit cycles or idle tones. The dynamics processor uses a sophisticated, multiple-breakpoint algorithm often found in high end broadcast compressors. The AD1940/AD1941 are a fully programmable DSP. Easy to use software allows the user to graphically configure a custom signal processing flow using blocks such as biquad filters, dyna- mics processors, and surround sound processors. An extensive control port allows click-free parameter updates, along with readback capability from any point in the algorithm flow. The AD1940/AD1941’s digital input and output ports allow a glueless connection to ADCs and DACs by multiple, 2-channel serial data streams or TDM data streams. When in TDM mode, the AD1940/AD1941 can input 8 or 16 channels of serial data, and can output 8 or 16 channels of serial data. The input and output port configurations can be individually set. The AD1940 is controlled by a 4-wire SPI® port; the AD1941 is controlled by a 2-wire I2C® bus. Other than the control interface, the functions of the two parts are identical.

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AD1940/AD1941 Rev. B | Page 2 of 36 TABLE OF CONTENTS Specifications ..................................................................................... 3 Digital I/O ..................................................................................... 3 Power .............................................................................................. 3 Digital Timing ............................................................................... 4 PLL ................................................................................................. 5 Regulator ........................................................................................ 5 Temperature Range ...................................................................... 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Digital Timing Diagrams ................................................................. 7 Pin Configuration and Function Descriptions ............................. 9 Features ............................................................................................ 11 Pin Functions .............................................................................. 12 Signal Processing ............................................................................ 14 Overview ...................................................................................... 14 Numeric Formats ........................................................................ 14 Programming .............................................................................. 14 Control Port ..................................................................................... 15 Overview ...................................................................................... 15 AD1940 SPI Port ........................................................................ 15 AD1941 I2C Port ......................................................................... 15 RAMs and Registers ....................................................................... 19 Control Port Addressing ........................................................... 19 Parameter RAM Contents ......................................................... 19 Recommended Program/Parameter Loading Procedures .... 20 Target/Slew RAM ....................................................................... 20 Safeload Registers ....................................................................... 23 Data Capture Registers .............................................................. 23 DSP Core Control Register ....................................................... 24 RAM Configuration Register ................................................... 25 Control Port Read/Write Data Formats .................................. 25 Serial Data Input/Output Ports .................................................... 28 Serial Output Control Registers ............................................... 30 Serial Input Control Register .................................................... 30 Initialization .................................................................................... 33 Power-Up Sequence ................................................................... 33 Setting Master Clock/PLL Mode .............................................. 33 Voltage Regulator ....................................................................... 33 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35 REVISION HISTORY 4/10—Rev. A to Rev. B Changes to Voltage Regulator Section ..................................... 34 Updated Outline Dimensions ................................................... 35 Changes to Ordering Guide ...................................................... 35 4/05—Rev. 0 to Rev. A Added AD1941 .............................................................. Universal Changes to Specifications ............................................................ 3 Changes to Pin Function Descriptions ...................................... 9 Changes to Features Section...................................................... 11 Changes to Pin Functions Section ............................................ 13 Addition of AD1940 SPI Port Section ..................................... 15 Added Table 13 to Table 16 ....................................................... 18 7/04—Revision 0: Initial Version

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AD1940/AD1941 Rev. B | Page 3 of 36 SPECIFICATIONS Test conditions, unless otherwise noted. Table 1. Parameter Conditions Supply Voltage (VDD) 2.5 V PLL Voltage (PLL_VDD) 2.5 V Output Voltage (ODVDD) 5.0 V INVDD Voltage 5.0 V Ambient Temperature 25°C Master Clock Input 3.072 MHz, 64 × fs mode Load Capacitance 50 pF Load Current ±1 mA Input Voltage, HI 2.4 V Input Voltage, LO 0.8 V DIGITAL I/O VDD = 2.25 V to 2.75 V. Specifications measured across −40°C to 125°C (case). Table 2. Parameter Comments Min Max Unit Input Voltage, HI (VIH) 2.1 V Input Voltage, LO (VIL) 0.8 V Input Leakage (IIH) 10 μA Input Leakage (IIL) 10 μA High Level Output Voltage (VOH) ODVDD = 4.5 V, IOH = 1 mA 3.9 V High Level Output Voltage (VOH) ODVDD = 3.0 V, IOH = 1 mA 2.6 V Low Level Output Voltage (VOL) ODVDD = 4.5 V, IOL = 1 mA1 0.4 V Low Level Output Voltage (VOL) ODVDD = 3.0 V, IOL = 1 mA1 0.3 V Input Capacitance 5 pF 1 SDA is measured with a 3 mA sink current. POWER Table 3. Parameter Min Typ Max1 Unit SUPPLIES Voltage 2.25 2.5 2.75 V Digital Current 92 1552 mA PLL Current 3.5 8 mA Digital Current, Reset 4.53 133 mA PLL Current, Reset 3 8.5 mA DISSIPATION Operation, All Supplies 238.8 mW Reset, All Supplies 10.8 mW 1 Maximum specifications are measured across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V. 2 Measurement running a typical large program that writes to all 16 outputs with 0 dB digital sine waves applied to all eight inputs. The end user’s program may differ. 3 The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.

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AD1940/AD1941 Rev. B | Page 4 of 36 DIGITAL TIMING VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C. Table 4. Digital Timing1 Parameter Mnemonic Comments Min Max Unit MASTER CLOCK, SERIAL DATA PORTS, RESET MCLK Period tMP 512 fS mode 36 244 ns MCLK Period tMP 384 fS mode 48 366 ns MCLK Period tMP 256 fS mode 73 488 ns MCLK Period tMP 64 fS mode 291 1953 ns MCLK Period tMP Bypass mode 12 ns MCLK Duty Cycle tMDC Bypass mode 40 60 % BCLK_IN LO Pulse Width tBIL 4 ns BCLK_IN HI Pulse Width tBIH 2 ns LRCLK_IN Setup tLIS To BCLK_IN rising 12 ns LRCLK_IN Hold tLIH From BCLK_IN rising 0 ns SDATA_INx Setup tSIS To BCLK_IN rising 3 ns SDATA_INx Hold tSIH From BCLK_IN rising 2 ns LRCLK_OUTx Setup tLOS Slave mode 2 ns LRCLK_OUTx Hold tLOH Slave mode 2 ns BCLK_OUTx Falling to LRCLK_OUTx Timing Skew tTS 2 ns SDATA_OUTx Delay tSODS Slave mode, from BCLK_OUTx falling 17 ns SDATA_OUTx Delay tSODM Master mode, from BCLK_OUTx falling 17 ns RESETB LO Pulse Width tRLPW 10 ns SPI PORT (AD1940) CCLK Pulse Width LO tCCPL 1 × INTMCLK (14)2 ns CCLK Pulse Width HI tCCPH 1 × INTMCLK (14)2 ns CLATCH Setup tCLS To CCLK rising 0 ns CLATCH Hold tCLH From CCLK rising 2 × INTMCLK + 4 (32)2 ns CLATCH Pulse Width HI tCLPH 2 × INTMCLK (28)2 ns CDATA Setup tCDS To CCLK rising 0 ns CDATA Hold tCDH From CCLK rising 2 × INTMCLK + 2 (30)2 ns COUT Delay tCOD From CCLK rising 4 × INTMCLK +18 (74)2 ns I2C PORT (AD1941) SCL Clock Frequency fSCL 400 kHz SCL Low tSCLL 1.3 μs SCL High tSCLH 0.6 μs Setup Time (Start Condition) tSCS Relevent for repeated start condition 0.6 μs Hold Time (Start Condition) tSCH First clock generated after this period 0.6 μs Setup Time (Stop Condition) tSSH 0.6 μs Data Setup Time tDS 100 ns SDA and SCL Rise Time tSR 300 ns SDA and SCL Fall Time tSF 300 ns Bus-Free Time tBFT Between stop and start 1.3 μs 1 All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Table 37. 2 These specifications are based on the internal master clock period in a specific application. In normal operation, the master clock runs at 1,536 × fs, so the internal master clock at fs = 48 kHz has a 14 ns period. The values in parentheses are the timing values for fs = 48 kHz.

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AD1940/AD1941 Rev. B | Page 5 of 36 PLL VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C. Table 5. Parameter Min Typ Max Unit Lock Time 3 20 ms REGULATOR VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C. Table 6. Parameter Min Typ Max Unit VSENSE Output Voltage 2.25 2.5 2.68 V TEMPERATURE RANGE Table 7. Parameter Min Typ Max Unit Functionality Guaranteed –40 +105 °C Ambient –40 +125 °C Case

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AD1940/AD1941 Rev. B | Page 6 of 36 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Min Max Unit VDD to DGND –0.3 +3.0 V PLL_ VDD to PGND –0.3 +3.0 V OD VDD to DGND –0.3 +6.0 V INVDD to DGND ODVDD +6.0 V Digital Inputs DGND – 0.3 INVDD + 0.3 V Maximum Junction Temperature 135 °C Storage Temperature Range –65 +150 °C Soldering (10 sec) 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 9. Package Characteristics Parameter Min Typ Max Unit θJA Thermal Resistance (Junction- to-Ambient) 72 °C/W θJC Thermal Resistance (Junction- to-Case) 19.5 °C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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AD1940/AD1941 Rev. B | Page 7 of 36 DIGITAL TIMING DIAGRAMS BCLK_IN LRCLK_IN SDATA_INX LEFT-JUSTIFIED MODE LSB SDATA_INX I2S-JUSTIFIED MODE SDATA_INX RIGHT-JUSTIFIED MODE tBIH MSB MSB-1 MSB MSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) tLIS tSIS tSIH tSIH tSIS tSIS tSIH tSIS tSIH tLIH tBIL 04 60 7- 0- 01 3 Figure 2. Serial Input Port Timing BCLK_OUTX LRCLK_OUTX SDATA_OUTX LEFT-JUSTIFIED MODE LSB SDATA_OUTX I2S-JUSTIFIED MODE SDATA_OUTX RIGHT-JUSTIFIED MODE tBIH MSB MSB-1 MSB MSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) tLOS tSDDS tSDDM tSDDS tSDDM tSDDS tSDDM tLCH tTS tBIL 04 60 7- 0- 01 4 Figure 3. Serial Output Port Timing

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AD1940/AD1941 Rev. B | Page 8 of 36 CLATCH CCLK CDATA COUT tCLS tCDS tCDH tCOD tCCPH tCCPL tCLH tCLPH 04 60 7- 0- 01 5 Figure 4. AD1940 SPI Port Timing tTSCH tSCLHtSR tSCLL tST tDS SDA SCLK tTSCH tSSH 04 60 7- 02 6 tSCS Figure 5. AD1941 I2C Port Timing MCLK RESETB tMP tRLPW 04 60 7- 0- 01 6 Figure 6. Master Clock and Reset Timing

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AD1940/AD1941 Rev. B | Page 9 of 36 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 3743 42 41 40 GND BCLK_OUT1 LRCLK_OUT1 ODVDD SDATA_OUT3 SDATA_OUT2 SDATA_OUT1 VDD MCLK RESERVED PLL_VDD NC SDATA_OUT0 ODVDD BCLK_OUT0 LRCLK_OUT0 GND VDD PIN 1 INDICATOR PLL_CTRL0 PLL_CTRL1 PLL_CTRL2 PLL_GND AD1940 TOP VIEW (Not to Scale) V D D S D A T A _I N 1 S D A T A _I N 2 S D A T A _ I N 3 C O U T C C L K C L A T C H C D A T A R E S E T B G N D S D A T A _ IN 0 A D R _ S E L G N D V R E F V D R IV E V S E N S E V S U P P L Y IN V D D S D A T A _ O U T 7 S D A T A _O U T 6 O D V D D S D A T A _O U T 5 S D A T A _O U T 4 V D D 04 60 7- 0- 00 2 LRCLK_IN BCLK_IN NC = NO CONNECT 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 3743 42 41 40 GND BCLK_OUT1 LRCLK_OUT1 ODVDD SDATA_OUT3 SDATA_OUT2 SDATA_OUT1 VDD MCLK RESERVED PLL_VDD I2C_FILT_EN SDATA_OUT0 ODVDD BCLK_OUT0 LRCLK_OUT0 GND VDD PIN 1 INDICATOR PLL_CTRL0 PLL_CTRL1 PLL_CTRL2 PLL_GND AD1941 TOP VIEW (Not to Scale) V D D S D A T A _I N 1 S D A T A _I N 2 S D A T A _ I N 3 S D A S C L N C N C R E S E T B G N D S D A T A _ IN 0 A D R _ S E L G N D V R E F V D R IV E V S E N S E V S U P P L Y IN V D D S D A T A _ O U T 7 S D A T A _O U T 6 O D V D D S D A T A _O U T 5 S D A T A _O U T 4 V D D 04 60 7- 0- 01 1 LRCLK_IN BCLK_IN NC = NO CONNECT Figure 7. 48-Lead LQFP Pin Configuration, AD1940 Figure 8. 48-Lead LQFP Pin Configuration, AD1941 Table 10. Pin Function Descriptions Pin No. AD1940 AD1941 I/O Mnemonic Description 1, 25, 37 1, 25, 37 VDD Core Power. 2 2 IN MCLK Master Clock Input. 3 3 RESERVED This pin should be connected to ground. 4 4 IN PLL_CTRL0 PLL Control 0. 5 5 IN PLL_CTRL1 PLL Control 1. 6 6 IN PLL_CTRL2 PLL Control 2. 7 7 PLL_GND PLL Ground. 8 8 PLL_VDD PLL Power. 9 21, 22 NC No Connect. 9 IN I2C_FILT_ENB I2C Filter Enable, Active Low. 10 10 IN LRCLK_IN Left/Right Clock for Serial or TDM Data Inputs. 11 11 IN BCLK_IN Bit Clock for Serial or TDM Data Inputs. 12, 24, 36, 48 12, 24, 36, 48 GND Digital Ground. 13 13 VDD Core Power. 14 14 IN SDATA_IN0 Serial Data Input 0. 15 12 IN SDATA_IN1 Serial Data Input 1. 16 16 IN SDATA_IN2/TDM_IN1 Serial Data Input 2/TDM Input 1. 17 17 IN SDATA_IN3/TDM_IN0 Serial Data Input 3/TDM Input 0. 18 18 IN ADR_SEL Control Port Address Select. 19 OUT COUT SPI Data Output. 20 IN CCLK Clock for SPI. 21 IN CLATCH SPI Data Latch.

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November 18, 2020

Heisener has a fantastic Web site shopping system! Best purchasing interface of the bundle.

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November 16, 2020

arrived well within time bracket, put this firm on my suppliers list, many thanks

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October 27, 2020

They are components and they work. Wasn’t expecting anything more or anything less.

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October 20, 2020

So far all the items still work. I'm using these for some home made solar panels and they're doing great.

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October 11, 2020

Rec today in good order & condition . Thanks for speedy delivery.Regards.

Manue*****livan

October 10, 2020

Every little component you can always find in here, and good suggestion for relative times too.

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October 10, 2020

Happy with purchase, would do business again

Ang*****Gade

October 7, 2020

Arrived safely. All OK. Thanks

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