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AD45048ARZ-REEL7

hot AD45048ARZ-REEL7

AD45048ARZ-REEL7

For Reference Only

Part Number AD45048ARZ-REEL7
Manufacturer Analog Devices Inc.
Description IC ADSL LINE DRIVER R-R 8SOIC
Datasheet AD45048ARZ-REEL7 Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 8000 piece(s)
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Lead Time Can Ship Immediately
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AD45048ARZ-REEL7

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AD45048ARZ-REEL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - Drivers, Receivers, Transceivers
Datasheet AD45048ARZ-REEL7 Datasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
TypeDriver
ProtocolxDSL
Number of Drivers/Receivers2/0
Voltage - Supply6 V ~ 12 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC

AD45048ARZ-REEL7 Datasheet

Page 1

Page 2

Rail-to-Rail Upstream ADSL Line Driver AD45048 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. FEATURES Dual op amp Voltage feedback Wide supply range: from 3.3 V to 24 V Rail-to-rail output Output swing to within 0.5 V of supply rails @ 230 mA 23 V p-p differential, RLOAD of 50 Ω from 12 V supply High output current Linear output current of 230 mA peak into 25 Ω −68 dBc MTPR @ 15 dBm (100 Ω telephone line) Low noise 4.5 nV/√Hz voltage noise density @ 100 kHz 1.5 pA/√Hz current noise density @ 100 kHz High speed 65 MHz bandwidth (AV = 1, −3 dB) 55 V/μs slew rate (RLOAD = 25 Ω) APPLICATIONS Consumer xDSL modems Twisted pair line drivers ADSL CPE applications (Drop in replacement for TS613ID and EL1519CS) Audio applications GENERAL DESCRIPTION The AD45048 ADSL CPE line driver is a dual operational amplifier capable of driving high output current (230 mA); it features a rail-to-rail output stage that swings to within 0.5 V of the supply rails. The AD45048 rail-to-rail output stage surpasses the output voltage capability of typical emitter- follower output stages and can deliver up to 23 V p-p differentially from a single 12 V supply in ADSL CPE line driving applications. The low distortion, high output current and wide output dynamic range make the AD45048 ideal for driving upstream signals in ADSL CPE applications. Fabricated with ADI’s high speed XFCB-HV (eXtra Fast Complementary Bipolar-High Voltage) process, the high bandwidth and fast slew rate of the AD45048 keep distortion to a minimum while dissipating minimum power. The AD45048 is available in a standard 8-lead SOIC package that can operate from −40°C to +85°C. PIN CONFIGURATION OUT1 1 –IN1 2 +IN1 3 –VS 4 +VS OUT2 –IN2 +IN2 8 7 6 5 04 81 7- S p0 -0 01 Figure 1. 8-Lead SOIC 10 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 CENTER 86.31174378kHz 1kHz/ SPAN 10kHz 04 81 7- S p0 -0 02 d B m –68dB Figure 2. AD45048AR Upstream ADSL MTPR (13 dBm, CF = 5.3) OB SO L TE

Page 3

AD45048 Rev. A | Page 2 of 8 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Pin Configuration............................................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Typical Performance Characteristics ............................................. 5 General Description..........................................................................7 Power Supply and Decoupling.....................................................7 Layout Considerations..................................................................7 CPE ADSL Application ................................................................7 Transformer Selection ..................................................................7 Receive Channel Considerations.................................................7 Outline Dimensions ..........................................................................8 Ordering Guide .............................................................................8 REVISION HISTORY 9/05—Rev. 0 to Rev. A Updated Outline Dimensions ......................................................... 8 Changes to Ordering Guide ............................................................ 8 7/04—Revision 0: Initial Version OB SO LE TE

Page 4

AD45048 Rev. A | Page 3 of 8 SPECIFICATIONS VS = ±6 V or +12 V (@ TA = 25°C, G = +10, RL = 100 Ω, unless otherwise noted). Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, VOUT = 0.1 V p-p, RFB = 0 Ω, RLOAD = 25 Ω 65 MHz 0.1 dB Flatness VOUT = 0.1 V p-p single-ended, G = +1, RLOAD = 25 Ω 3.35 MHz Large Signal Bandwidth VOUT = 1 V p-p single-ended, G = +10, RLOAD = 25 Ω 4.5 MHz Large Signal Slew Rate VOUT = 5 V p-p, G = +1, RLOAD = 25 Ω 55 V/μs NOISE/DISTORTION PERFORMANCE Distortion (Worst Harmonic) fC = 40 kHz, VOUT = 6 V p-p, single-ended, RLOAD = 25 Ω −80 dBc Multitone Power Ratio 26 kHz to 134 kHz, ZLINE = 100 Ω, XFMR = 1:2 turns, PLINE = 13 dBm −68 dBc Input Voltage Noise f = 100 kHz 4.5 nV/√Hz Input Current Noise f = 100 kHz 1.5 pA/√Hz DC PERFORMANCE Input Offset Voltage 1 2.5 mV TMIN − TMAX 2.5 mV Input Offset Voltage Match 1 2.0 mV Input Bias Current 200 900 nA TMIN − TMAX 1.3 μA Input Offset Current 50 300 nA Open-Loop Gain 85 94 dB INPUT CHARACTERISTICS Input Resistance f = 100 kHz 87 kΩ Input Capacitance 1.4 pF OUTPUT CHARACTERISTICS Output Resistance 1.4 MHz; G = +1 0.2 Ω Output Voltage Swing Maximum swing (differential) VOMAX, RLOAD = 50 Ω differential 11.25 11.5 V diff Minimum swing (differential) VOMIN, RLOAD = 50 Ω differential −11.5 −11.25 V diff Differential Output Voltage Swing ΔVOUT = VOMAX − VOMIN 22.5 23 V p-p Single-Ended +Swing RLOAD = 25 Ω 5.68 5.76 Vp Single-Ended -Swing RLOAD = 25 Ω −5.67 −5.58 Vp Single-Ended +Swing RLOAD = 100 Ω 5.92 5.95 Vp Single-Ended –Swing RLOAD = 100 Ω −5.91 −5.86 Vp Operating Range (Dual Supply) ±1.5 ±12.6 V Supply Current 7 9 12 mA Power Supply Rejection Ratio ±0.5 V −85 −75 dB Common-Mode Rejection Ratio ±1 V −86 −79 dB OB SO LE TE

Page 5

AD45048 Rev. A | Page 4 of 8 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage 26.4 V Power Dissipation (TJMAX – TA)/θJA1 Storage Temperature −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature Range (Soldering 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 θJA = 112.7°C/W for SOIC package in still air based on 2S2P JEDEC PCB. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. OB SO LE TE

Page 6

AD45048 Rev. A | Page 5 of 8 TYPICAL PERFORMANCE CHARACTERISTICS 25 –25 –5 –10 –15 –20 0 5 10 15 20 10k 100k 1M 10M 1G100M 04 81 7- S p0 -0 17 G A IN ( d B ) FREQUENCY (Hz) G = +10 G = +5 G = +2 G = +1 – + 499Ω 25Ω RG Figure 3. Noninverting Small Signal Bandwidth (VS = ±6 V, VO = 0.1 V p-p, RL = 25 Ω) 25 –25 –20 –15 –10 –5 0 5 10 15 20 10k 100k 1M 10M 100M 1G 04 81 7- S p0 -0 25 G A IN ( d B ) FREQUENCY (Hz) G = –10 G = –5 G = –2 G = –1 – + 5kΩ 25Ω RG Figure 4. Inverting Small Signal Bandwidth (VS = ±6 V, VO = 0.1 V p-p, RL = 25 Ω) –40 –80 –70 –60 –50 0 5 10 15 20 04 81 7- S p0 -0 27 M T P R dBm (100Ω) Figure 5. MTPR vs. Line Power (See Schematic in Figure 8) 25 –25 –20 –15 –10 –5 0 5 10 15 20 10k 100k 1M 10M 100M 1G 04 81 7- S p0 -0 26 G A IN ( d B ) FREQUENCY (Hz) G = +10 G = +5 G = +2 G = +1 – + 499Ω 25Ω RG Figure 6. Noninverting Large Signal Bandwidth (VS = ±6 V, VO = 1 V p-p, RL = 25 Ω) 25 –25 –20 –15 –10 –5 0 5 10 15 20 10k 100k 1M 10M 100M 1G 04 81 7- S p0 -0 18 G A IN ( d B ) FREQUENCY (Hz) G = –10 G = –5 G = –2 G = –1 – + 5kΩ 25Ω RG Figure 7. Inverting Large Signal Bandwidth (VS = ±6 V, VO = 1 V p-p, RL = 25 Ω) 04 81 7- S p0 -0 14 1 OUT +VIN U1A AD45048 8 V+ +12V 2 3 R1 499Ω R2 3kΩ R3 12.5Ω 7 OUT –VIN U1B AD450484 V– 5 6 R4 499Ω R5 3kΩ R6 12.5Ω TX1 1:2 R3 100Ω+6V 0.1μF 4.7μF TANT Figure 8. Differential Test Circuit for MTPR OB SO LE TE

Page 7

AD45048 Rev. A | Page 6 of 8 100 1 10 10 100 1k 10k 100k 1M 10M 100M 04 81 7- S p0 -0 19 V O L T A G E N O IS E ( n V / H z) FREQUENCY (Hz) Figure 9. Voltage Noise vs. Frequency, VS = ±6 V 0 –120 –100 –80 –60 –40 –20 1 3 5 7 92 4 6 8 10 11 04 81 7- S p0 -0 28 D IS T O R T IO N ( d B c) OUTPUT VOLTAGE (p-p) SECOND THIRD Figure 10. Single-Ended Harmonic Distortion, VS = ±6 V dc, G = +6, RF = 499 Ω, RG = 100 Ω, RL = 25 Ω, Fundamental Frequency = 40 kHz 04 81 7- S p0 -0 29 2V/DIV M 5.00μs Figure 11. Discrete Multitone Modulation Overdrive Recovery (See Schematic in Figure 8) 100 1 10 10 100 1k 10k 100k 1M 10M 04 81 7- S p0 -0 20 C U R R E N T N O IS E ( p A / H z) FREQUENCY (Hz) Figure 12. Input Current Noise vs. Frequency, VS = ±6 V 1000 0.001 0.01 0.1 1 10 100 10k 100k 1M 10M 100M 04 81 7- S p0 -0 30 O U T P U T IM D E D A N C E ( Ω ) FREQUENCY (Hz) Figure 13. Output Impedance vs. Frequency 04 81 7- S p0 -0 31 50mV/DIV M 100ns Figure 14. Small Signal Pulse Response RLOAD = 1 kΩ, RFB = 500 Ω OB SO LE TE

Page 8

AD45048 Rev. A | Page 7 of 8 GENERAL DESCRIPTION The AD45048 is a voltage feedback, rail-to-rail output amplifier with high output current capability. Fabricated on Analog Devices’ proprietary high speed eXtra fast complementary bipolar high voltage process (XFCB-HV), the high bandwidth and fast slew rate of the AD45048 keep distortion to a minimum while dissipating minimum power. The XFCB-HV, silicon-on-insulator (SOI) process prevents latch-up problems and enables the construction of high frequency, low distortion amplifiers, such as the AD45048. POWER SUPPLY AND DECOUPLING The AD45048 can be powered with a good quality, well regulated, low noise supply anywhere in the range from +3 V to ±12.6 V. In order to optimize the AD45048 in standard ADSL CPE line driver applications (see Figure 8), power the amplifier with a well regulated 12 V supply. Careful attention should be paid to decoupling the power supply. High quality capacitors with low equivalent series resistance (ESR), such as multilayer ceramic capacitors (MLCCs), should be used to minimize the supply voltage ripple and power dissipation. A 0.1 μF MLCC decoupling capacitor(s) should be located no more than 1/8-inch away from the power supply pin(s). A large, usually tantalum, 10 μF to 47 μF capacitor is recommended to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the AD45048 outputs. LAYOUT CONSIDERATIONS As is the case with all high speed applications, careful attention to printed circuit board layout details prevents associated board parasitics from becoming problematic. Proper RF layout and printed circuit board design techniques are strongly recommended. The PCB should have a low impedance return path (or ground) to the supply. Removing the ground plane from all layers in the immediate area of the amplifier reduces stray capacitances. The signal routing should be short and direct in order to minimize the parasitic inductance and capacitance associated with these traces. Termination resistors and loads should be located as close as possible to their respective inputs and outputs. Input traces should be kept as far apart as possible from the output traces to minimize coupling (crosstalk) though the board. Wherever there are complementary signals, a symmetrical layout should be provided to the extent possible in order to maximize balanced performance. When running differential signals over a long distance, the traces on the PCB should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. This reduces the radiated energy and makes the circuit less susceptible to RF interference. Adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended. CPE ADSL APPLICATION The low cost, high output current dual AD45048 xDSL line driver amplifiers have been specifically designed to drive high fidelity xDSL signals to within 0.5 V of the power rails on a single 12 V supply. The AD45048 can be used in transformer- coupled bridge hybrid circuits designed to drive modulated signals, including discrete multitone (DMT), upstream to the central office. TRANSFORMER SELECTION Customer premise ADSL applications require the transmission of a 13 dBm DMT signal (20 mW into 100 Ω). DMT signals can have a crest factor (V peak/V rms ratio) as high as 5.3, requiring the line driver to provide a peak power of 560 mW. The line driver is required to drive a 7.5 V peak onto the 100 Ω telephone line while maintaining about −65 dBc to −70 dBc of MTPR. Since the maximum low distortion output swing available from the AD45048 line driver is approximately 11.5 V on a 12 V supply (depending on the load), and taking into account the power lost in the transformer and termination resistors, a step-up transformer with a minimum turns ratio of 1.5 or greater is needed. In the simplified differential driver circuit shown in Figure 8, the AD45048 is driving a 25 Ω impedance reflected by 1:2 step-up transformer. R3 and R6 are 12.5 Ω each and are back-termination or load-matching resistors whose values can be calculated by (100 Ω/(N2))/2 where 100 Ω is the approximate phone line impedance and N is the transformer turns ratio. In Figure 8, the total differential load including the termination resistors is 50 Ω, and under these conditions, the AD45048 is capable of driving low distortion signals to within 0.5 V of the power rails. RECEIVE CHANNEL CONSIDERATIONS A step-up transformer of N turns used at the output of the differential line driver increases the differential output voltage to the line (see Figure 8). However, the inverse effect is seen in the receive channel as the amplitude of signal on the driver side of the transformer is divided by N turns. The decision to use a particular transformer turns ratio may be impacted by the ability of the receive circuitry to resolve low level signals in the noisy twisted pair telephone plant. Higher turns ratio transformers reduce the effective receive channel SNR (signal- to-noise ratio) due to the reduction in the received signal strength. An amplifier with low RTI noise, such as the AD8022 (2.5 nV/√Hz), is recommended for the receive channel. For a complete selection of amplifiers and other related components, see www.analog.com. OB SO LE TE

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