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AD5227BUJZ100-RL7

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AD5227BUJZ100-RL7

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Part Number AD5227BUJZ100-RL7
Manufacturer Analog Devices Inc.
Description IC DGTL POT UP/DN 100K TSOT23-8
Datasheet AD5227BUJZ100-RL7 Datasheet
Package SOT-23-8 Thin, TSOT-23-8
In Stock 873 piece(s)
Unit Price $ 0.6300 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 24 - Sep 29 (Choose Expedited Shipping)
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Part Number # AD5227BUJZ100-RL7 (Data Acquisition - Digital Potentiometers) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD5227BUJZ100-RL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital Potentiometers
Datasheet AD5227BUJZ100-RL7Datasheet
PackageSOT-23-8 Thin, TSOT-23-8
Series-
TaperLinear
ConfigurationPotentiometer
Number of Circuits1
Number of Taps64
Resistance (Ohms)100k
InterfaceUp/Down (U/D, CS)
Memory TypeVolatile
Voltage - Supply2.7 V ~ 5.5 V
Features-
Tolerance±20%
Temperature Coefficient (Typ)35 ppm/°C
Resistance - Wiper (Ohms) (Typ)100
Operating Temperature-40°C ~ 105°C
Package / CaseSOT-23-8 Thin, TSOT-23-8
Supplier Device PackageTSOT-23-8

AD5227BUJZ100-RL7 Datasheet

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64-Position Up/Down Control Digital Potentiometer AD5227 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703© 2004–2009 Analog Devices, Inc. All rights reserved. FEATURES 64-position digital potentiometer 10 kΩ, 50 kΩ, 100 kΩ end-to-end terminal resistance Simple up/down digital or manual configurable control Midscale preset Low potentiometer mode tempco = 10 ppm/°C Low rheostat mode tempco = 35 ppm/°C Ultralow power, IDD = 0.4 μA typ and 3 μA max Fast adjustment time, ts = 1 μs Chip select enable multiple device operation Low operating voltage, 2.7 V to 5.5 V Automotive temperature range, −40°C to +105°C Compact thin SOT-23-8 (2.9 mm × 3 mm) Pb-free package APPLICATIONS Mechanical potentiometer and trimmer replacements LCD backlight, contrast, and brightness controls Portable electronics level adjustment Programmable power supply Digital trimmer replacements Automatic closed-loop control FUNCTIONAL BLOCK DIAGRAM 04 41 9- 0- 00 1 CS U/D CLK GND VDD 6-BIT UP/DOWN CONTROL LOGIC POR MIDSCALE WIPER REGISTER A W B AD5227 Figure 1. GENERAL DESCRIPTION The AD5227 is Analog Devices’ latest 64-step up/down control digital potentiometer1. This device performs the same electronic adjustment function as a 5 V potentiometer or variable resistor. Its simple 3-wire up/down interface allows manual switching or high speed digital control. The AD5227 presets to midscale at power-up. When CS is enabled, the devices changes step at every clock pulse. The direction is determined by the state of the U/D pin (see ). The interface is simple to activate by any host controller, discrete logic, or manually with a rotary encoder or pushbuttons. The AD5227’s 64-step resolution, small footprint, and simple interface enable it to replace mechanical potentiometers and trimmers with typically 6× improved resolution, solid-state reliability, and design layout flexibility, resulting in a considerable cost savings in end users’ systems. Table 1 1 The terms digital potentiometer and RDAC are used interchangeably. The AD5227 is available in a compact thin SOT-23-8 (TSOT-8) Pb-free package. The part is guaranteed to operate over the automotive temperature range of −40°C to +105°C. Users who consider EEMEM potentiometers should refer to some recommendations in the Applications section. Table 1. Truth Table CS CLK U/D Operation1 0 ↓ 0 RWB Decrement 0 ↓ 1 RWB Increment 1 X X No Operation 1 RWA increments if RWB decrements and vice versa.

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AD5227 Rev. B | Page 2 of 16 TABLE OF CONTENTS Electrical Characteristics ................................................................. 3  Interface Timing Diagrams ......................................................... 4  Absolute Maximum Ratings ............................................................ 5  ESD Caution .................................................................................. 5  Pin Configuration and Function Descriptions ............................. 6  Typical Performance Characteristics ............................................. 7  Theory of Operation ...................................................................... 10  Programming the Digital Potentiometers ............................... 10  Digital Interface .......................................................................... 11  Terminal Voltage Operation Range ......................................... 11  Power-Up and Power-Down Sequences .................................. 11  Layout and Power Supply Biasing ............................................ 11  Applications ..................................................................................... 12  Manual Control with Toggle and Pushbutton Switches ........ 12  Manual Control with Rotary Encoder ..................................... 12  Adjustable LED Driver .............................................................. 12  Adjustable Current Source for LED Driver ............................ 12  Adjustable High Power LED Driver ........................................ 13  Automatic LCD Panel Backlight Control ................................ 13  6-Bit Controller .......................................................................... 13  Constant Bias with Supply to Retain Resistance Setting ....... 14  Outline Dimensions ....................................................................... 15  Ordering Guide .......................................................................... 15  REVISION HISTORY 5/09—Rev. A to Rev. B Changes to Table 2……………………………………………3 4/09—Rev. 0 to Rev. A Changes to Table 2……………………………………………3 Changes to Ordering Guide …………………………………15 3/04—Revision 0: Initial Version

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AD5227 Rev. B | Page 3 of 16 ELECTRICAL CHARACTERISTICS 10 kΩ, 50 kΩ, 100 kΩ versions: VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +105°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, A = no connect −0.5 ±0.15 +0.5 LSB Resistor Integral Nonlinearity2 R-INL RWB, A = no connect −1 ±0.3 +1 LSB Nominal Resistor Tolerance3 ∆RAB/RAB −20 +20 % Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C Wiper Resistance RW VDD = 2.7 V 100 250 Ω VDD = 2.8 V to 5.5 V 50 200 Ω DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Resolution N 6 Bits Integral Nonlinearity3 INL −1 ±0.1 +1 LSB Differential Nonlinearity3, 4 DNL −0.5 ±0.1 +0.5 LSB Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106 Midscale 5 ppm/°C Full-Scale Error VWFSE ≥+31 steps from midscale −1.2 −0.5 0 LSB −40°C < TA < +60°C, VDD = 2.8 V to 5.5 V −1 −0.5 0 LSB Zero-Scale Error VWZSE ≤−32 steps from midscale 0 0.5 1.2 LSB −40°C < TA < +60°C, VDD = 2.8 V to 5.5 V 0 0.5 1 LSB RESISTOR TERMINALS Voltage Range5 VA, B, W With respect to GND 0 VDD V Capacitance A, B6 CA, B f = 1 MHz, measured to GND 140 pF Capacitance W6 CW f = 1 MHz, measured to GND 150 pF Common-Mode Leakage ICM VA = VB = VW 1 nA DIGITAL INPUTS (CS, CLK, U/D) Input Logic High VIH 2.4 5.5 V Input Logic Low VIL 0 0.8 V Input Current II VIN = 0 V or 5 V ±1 μA Input Capacitance6 CI 5 pF POWER SUPPLIES Power Supply Range VDD 2.7 5.5 V Supply Current IDD VIH = 5 V or VIL = 0 V, VDD = 5 V 0.4 3 μA Power Dissipation7 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 17 μW Power Supply Sensitivity PSSR VDD = 5 V ± 10% 0.01 0.05 %/% DYNAMIC CHARACTERISTICS6, 8, 9 Bandwidth −3 dB BW_10 k RAB = 10 kΩ, midscale 460 kHz BW_50 k RAB = 50 kΩ, midscale 100 kHz BW_100 k RAB = 100 kΩ, midscale 50 kHz Total Harmonic Distortion THD VA = 1 V rms, RAB = 10 kΩ, VB = 0 V dc, f = 1 kHz 0.05 % Adjustment Settling Time tS VA = 5 V ± 1 LSB error band, VB = 0, measured at VW 1 μs Resistor Noise Voltage eN_WB RWB = 5 kΩ, f = 1 kHz 14 nV/√Hz Footnotes on the next page.

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AD5227 Rev. B | Page 4 of 16 Parameter Symbol Conditions Min Typ1 Max Unit INTERFACE TIMING CHARACTERISTICS (applies to all parts6, 10) Clock Frequency fCLK 50 MHz Input Clock Pulse Width tCH, tCL Clock level high or low 10 ns CS to CLK Setup Time tCSS 10 ns CS Rise to CLK Hold Time tCSH 10 ns U/D to Clock Fall Setup Time tUDS 10 ns 1 Typicals represent average readings at 25°C, VDD = 5 V. 2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 NL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. 4 DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 All dynamic characteristics use VDD = V. 10 All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 5 V. INTERFACE TIMING DIAGRAMS 04 41 9- 0- 00 4 CS = LOW U/D = HIGH CLK RWB Figure 2. Increment RWB 04 41 9- 0- 00 5 CS = LOW U/D = 0 CLK RWB Figure 3. Decrement RWB 04 41 9- 0- 00 6 1 0 1 0 1 0 CS CLK U/D RWB tS tUDS tCL tCH tCSS tCSH Figure 4. Detailed Timing Diagram (Only RWB Decrement Shown)

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AD5227 Rev. B | Page 5 of 16 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating VDD to GND −0.3 V, +7 V VA, VB, VW to GND 0 V, VDD Digital Input Voltage to GND (CS, CLK, U/D) 0 V, VDD Maximum Current IWB, IWA Pulsed ±20 mA IWB Continuous (RWB ≤ 5 kΩ, A open)1 ±1 mA IWA Continuous (RWA ≤ 5 kΩ, B open)1 ±1 mA IAB Continuous (RAB = 10 kΩ/50 kΩ/100 kΩ)1 ±500 μA/ ±100 μA/±50 μA Operating Temperature Range −40°C to +105°C Maximum Junction Temperature (TJmax) 150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 10 s – 30 s) 245°C Thermal Resistance2 θJA 230°C/W 1 Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V. 2 Package power dissipation = (TJmax – TA) / θJA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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AD5227 Rev. B | Page 6 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 04 41 9- 0- 00 3 AD5227 TOP VIEW (Not to Scale) CLK 1 U/D 2 A 3 GND 4 VDD CS B W 8 7 6 5 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined by the state of the U/D pin. CLK is a negative-edge trigger. Logic high signal can be higher than VDD, but lower than 5.5 V. 2 U/D Up/Down Selections. Logic 1 selects up and Logic 0 selects down. U can be higher than VDD, but lower than 5.5 V. 3 A Resistor Terminal A. GND ≤ VA ≤ VDD. 4 GND Common Ground. 5 W Wiper Terminal W. GND ≤ VW ≤ VDD. 6 B Resistor Terminal B. GND ≤ VB ≤ VDD. 7 CS Chip Select. Active Low. Logic high signal can be higher than VDD, but lower than 5.5 V. 8 VDD Positive Power Supply, 2.7 V to 5.5 V.

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AD5227 Rev. B | Page 7 of 16 TYPICAL PERFORMANCE CHARACTERISTICS 0.25 –0.25 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0 645648403224168 04 41 9- 0- 00 7 CODE (Decimal) R H E O S T A T M O D E I N L ( L S B ) VDD = 5.5V –40°C +25°C +85°C +105°C Figure 6. R-INL vs. Code vs. Temperature, VDD = 5 V 0.25 –0.25 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0 645648403224168 04 41 9- 0- 00 8 CODE (Decimal) R H E O S T A T M O D E D N L ( L S B ) VDD = 5.5V –40°C +25°C +85°C +105°C Figure 7. R-DNL vs. Code vs. Temperature, VDD = 5 V 0.25 –0.25 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0 645648403224168 04 41 9- 0- 01 0 CODE (Decimal) P O T E N T IO M E T E R M O D E IN L ( L S B ) VDD = 5.5V –40°C +25°C +85°C +105°C Figure 8. INL vs. Code, VDD = 5 V 0.25 –0.25 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0 65648403224168 04 41 9- 0- 01 2 CODE (Decimal) P O T E N T IO M E T E R M O D E D N L ( L S B ) 4 VDD = 5.5V –40°C +25°C +85°C +105°C Figure 9. DNL vs. Code vs. Temperature, VDD = 5 V 0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 –40 –20 0 20 40 60 10080 04 41 9- 0- 01 3 TEMPERATURE (°C) F S E ( L S B ) VDD = 5.5V VDD = 2.7V Figure 10. Full-Scale Error vs. Temperature 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 –40 –20 0 20 40 60 10080 04 41 9- 0- 01 4 TEMPERATURE (°C) Z S E ( L S B ) VDD = 5.5V VDD = 2.7V Figure 11. Zero-Scale Error vs. Temperature

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AD5227 Rev. B | Page 8 of 16 1 0.1 –40 –20 0 20 40 60 10080 04 41 9- 0- 01 5 TEMPERATURE (°C) S U P P L Y C U R R E N T ( μA ) VDD = 5.5V Figure 12. Supply Current vs. Temperature 1 0.1 –40 –20 0 20 40 60 10080 04 41 9- 0- 01 6 TEMPERATURE (°C) N O M IN A L R E S IS T A N C E , R A B ( kΩ ) VDD = 5.5V RAB = 50kΩ RAB = 100kΩ RAB = 10kΩ Figure 13. Nominal Resistance vs. Temperature 120 0 20 40 60 80 100 –40 –20 0 20 40 60 10080 04 41 9- 0- 01 7 TEMPERATURE (°C) W IP E R R E S IS T A N C E , R W ( Ω ) VDD = 5.5V VDD = 2.7V Figure 14. Wiper Resistance vs. Temperature 20 –20 –15 –10 –5 0 5 10 15 0 8 16 24 32 40 48 56 64 04 41 9- 0- 01 8 CODE (Decimal) R H E O S T A T M O D E T E M P C O ( p p m /° C ) 10kΩ 50kΩ 100kΩ VDD = 5.5V Figure 15. Rheostat Mode Tempco ΔRWB/ΔT vs. Code 20 –20 –15 –10 –5 0 5 10 15 0 8 16 24 32 40 48 56 64 04 41 9- 0- 01 9 CODE (Decimal) P O T E N T IO M E T E R M O D E T E M P C O ( p p m /° C ) 10kΩ 50kΩ 100kΩ VDD = 5.5V Figure 16. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code 6 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 1k 10k 1M START 1 000.000Hz STOP 1 000 000.000Hz REF LEVEL 0dB /DIV 6.0dB MARKER MAG (A/R) 461 441.868Hz –8.957dB 100k 04 41 9- 0- 04 2 d B TA = 25°C VDD = 5.5V VA = 50mV rms 32 STEPS 16 STEPS 8 STEPS 4 STEPS 2 STEPS 1 STEP Figure 17. Gain vs. Frequency vs. Code, RAB = 10 kΩ

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AD5227 Rev. B | Page 9 of 16 6 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 1k 10k 1M START 1 000.000Hz STOP 1 000 000.000Hz REF LEVEL 0dB /DIV 6.0dB MARKER MAG (A/R) 100 885.289Hz –9.060dB 100k 04 41 9- 0- 04 3 d B TA = 25°C VDD = 5.5V VA = 50mV rms 32 STEPS 16 STEPS 8 STEPS 4 STEPS 2 STEPS 1 STEP Figure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ 6 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 1k 10k 1M START 1 000.000Hz STOP 1 000 000.000Hz REF LEVEL 0dB /DIV 6.0dB MARKER MAG (A/R) 52 246.435Hz –9.139dB 100k 04 41 9- 0- 04 4 d B TA = 25°C VDD = 5.5V VA = 50mV rms 32 STEPS 16 STEPS 8 STEPS 4 STEPS 2 STEPS 1 STEP Figure 19. Gain vs. Frequency vs. Code, RAB = 100 kΩ 0 –60 –40 –20 100 1k 10k 100k 1M 04 41 9- 0- 02 3 FREQUENCY (Hz) P S R R ( d B ) VDD = 5V DC ±10% p-p AC VDD = 3V DC ±10% p-p AC STEP = MIDSCALE, VA = VDD, VB = 0V Figure 20. PSRR 200 0 100 150 50 10k 100k 10M1M 04 41 9- 0- 02 4 FREQUENCY (Hz) I D D ( μA ) VDD = 5V VDD = 3V Figure 21. IDD vs. CLK Frequency 1.2 0 0.2 0.4 0.6 0.8 1.0 0 8 16 24 32 40 48 56 64 04 41 9- 0- 02 5 CODE (Decimal) T H E O R E T IC A L I W B _M A X ( m A ) RAB = 10kΩ RAB = 50kΩ RAB = 100kΩ A = OPEN TA = 25°C Figure 22. Maximum IWB vs. Code 04 41 9- 0- 02 2 CH1 2.00V CH2 50.0mV M 400ns A CH2 60.0mV VW 1 2 VA T 0.00000s VDD = 5V VA = 5V VB = 0V VB = 0V STEP N+1 STEP N Figure 23. Step Change Settling Time

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August 13, 2020

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August 12, 2020

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August 11, 2020

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August 5, 2020

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July 29, 2020

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July 25, 2020

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July 7, 2020

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July 5, 2020

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