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2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail
Voltage Output 8-/10-/12-Bit DACs
AD5303/AD5313/AD5323
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved.
FEATURES
AD5303: 2 buffered 8-bit DACs in 1 package
A version: ±1 LSB INL, B version: ±0.5 LSB INL
AD5313: 2 buffered 10-bit DACs in 1 package
A version: ±4 LSB INL, B version: ±2 LSB INL
AD5323: 2 buffered 12-bit DACs in 1 package
A version: ±16 LSB INL, B version: ±8 LSB INL
16-lead TSSOP package
Micropower operation: 300 μA @ 5 V (including reference
current)
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
2.5 V to 5.5 V power supply
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on-reset to 0 V
SDO daisy-chaining option
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Low power serial interface with Schmitt-triggered inputs
On-chip rail-to-rail output buffer amplifiers
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual 8-/10-/12-bit buffered
voltage output DACs in a 16-lead TSSOP package that operate
from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V.
Their on-chip output amplifiers allow the outputs to swing rail-to-
rail with a slew rate of 0.7 V/μs. The AD5303/AD5313/AD5323
utilize a versatile 3-wire serial interface that operates at clock
rates up to 30 MHz and is compatible with standard SPI, QSPI™,
MICROWIRE™, and DSP interface standards.
The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured
as buffered or unbuffered inputs. The parts incorporate a power-
on reset circuit, which ensures that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
place. There is also an asynchronous active low CLR pin that
clears both DACs to 0 V. The outputs of both DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the
current consumption of the devices to 200 nA at 5 V (50 nA
at 3 V) and provides software-selectable output loads while
in power-down mode. The parts may also be used in daisy-
chaining applications using the SDO pin.
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is 1.5 mW at 5 V and 0.7 mW at
3 V, reducing to 1 μW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
DAC
REGISTER
POWER-DOWN
LOGIC
BUFFER
STRING
DAC
STRING
DAC
AD5303/AD5313/AD5323
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
INTERFACE
LOGICSCLK
POWER-ON
RESET
VDD VREFA
VOUTA
VOUTB
GNDVREFBLDAC
DIN
00
47
2-
0
01
SYNC
CLR PD BUF B
BUFFER
SDO
DCEN
BUF A
RESISTOR
NETWORK
RESISTOR
NETWORK
GAIN-SELECT
LOGIC
Figure 1.
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AD5303/AD5313/AD5323
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 6
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
Functional Description .................................................................. 15
Digital-to-Analog ....................................................................... 15
Resistor String ............................................................................. 15
DAC Reference Inputs ............................................................... 15
Output Amplifier........................................................................ 15
Power-On Reset .............................................................................. 16
Clear Function (CLR) ................................................................ 16
Serial Interface ................................................................................ 17
Input Shift Register .................................................................... 17
Low Power Serial Interface ....................................................... 17
Double-Buffered Interface ........................................................ 17
Power-Down Modes ...................................................................... 19
Microprocesser Interfacing ........................................................... 20
AD5303/AD5313/AD5323 to ADSP-2101 Interface............. 20
AD5303/AD5313/AD5323 to 68HC11/68L11 Interface ...... 20
AD5303/AD5313/AD5323 to 80C51/80L51 Interface.......... 20
AD5303/AD5313/AD5323 to MICROWIRE Interface ........ 20
Applications Information .............................................................. 21
Typical Application Circuit....................................................... 21
Bipolar Operation Using the AD5303/AD5313/AD5323..... 21
Opto-Isolated Interface for Process Control Applications ... 22
Decoding Multiple AD5303/AD5313/AD5323s.................... 22
AD5303/AD5313/AD5323 as a Digitally Programmable
Window Detector ....................................................................... 22
Coarse and Fine Adjustment Using the
AD5303/AD5313/AD5323 ....................................................... 23
Daisy-Chain Mode ..................................................................... 23
Power Supply Bypassing and Grounding................................ 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
6/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 4............................................................................ 8
Changes to the Ordering Guide.................................................... 25
8/03—Rev. 0 to Rev. A
Added A Version.................................................................Universal
Changes to Features.......................................................................... 1
Changes to Specifications ................................................................ 2
Changes to Absolute Maximum Ratings ....................................... 5
Changes to Ordering Guide ............................................................ 5
Updated Outline Dimensions ....................................................... 18
4/99—Revision 0: Initial Version
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AD5303/AD5313/AD5323
Rev. B | Page 3 of 28
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Version1 B Version1
Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments
DC PERFORMANCE3 , 4
AD5303
Resolution 8 8 Bits
Relative Accuracy ±0.15 ±1 ± 0.15 ±0.5 LSB
Differential Nonlinearity ±0.02 ±0.25 ± 0.02 ±0.25 LSB Guaranteed monotonic by design over
all codes
AD5313
Resolution 10 10 Bits
Relative Accuracy ±0.5 ±4 ± 0.5 ±2 LSB
Differential Nonlinearity ±0.05 ±0.5 ± 0.05 ±0.5 LSB Guaranteed monotonic by design over
all codes
AD5323
Resolution 12 12 Bits
Relative Accuracy ±2 ±16 ±2 ±8 LSB
Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over
all codes
Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR See Figure 2 and Figure 3
Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR See Figure 2 and Figure 3
Lower Dead Band 10 60 10 60 mV See Figure 2 and Figure 3
Offset Error Drift5 −12 −12 ppm of FSR/°C
Gain Error Drift5 −5 −5 ppm of FSR/°C
Power Supply Rejection Ratio5 −60 −60 dB ΔVDD = ±10%
DC Crosstalk5 30 30 μV
DAC REFERENCE INPUTS5
1 VDD 1 VDD V Buffered reference mode VREF Input Range
0 VDD 0 VDD V Unbuffered reference mode
>10 >10 MΩ Buffered reference mode
180 180 kΩ Unbuffered reference mode
0 V to VREF output range, input
impedance = RDAC
90 90 kΩ Unbuffered reference mode
VREF Input Impedance
0 V to 2 VREF output range, input
impedance = RDAC
Reference Feedthrough −90 −90 dB Frequency = 10 kHz
Channel-to-Channel Isolation −80 −80 dB Frequency = 10 kHz
OUTPUT CHARACTERISTICS5
Minimum Output Voltage6 0.001 0.001 V min
Maximum Output Voltage6 VDD − 0.001 VDD − 0.001 V max
This is a measure of the minimum and
maximum drive capability of the output
amplifier
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 50 50 mA VDD = 5 V
20 20 mA VDD = 3 V
Power-Up Time 2.5 2.5 μs Coming out of power-down mode;
VDD = 5 V
5 5 μs Coming out of power-down mode;
VDD = 3 V
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AD5303/AD5313/AD5323
Rev. B | Page 4 of 28
A Version1 B Version1
Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments
LOGIC INPUTS5
Input Current ±1 ±1 μA
0.8 0.8 V VDD = 5 V ± 10%
0.6 0.6 V VDD = 3 V ± 10%
Input Low Voltage, VIL
0.5 0.5 V VDD = 2.5 V
2.4 2.4 V VDD = 5 V ± 10%
2.1 2.1 V VDD = 3 V ± 10%
Input High Voltage, VIH
2.0 2.0 V VDD = 2.5 V
Pin Capacitance 2 3.5 2 3.5 pF
LOGIC OUTPUT (SDO)5
VDD = 5 V ± 10%
Output Low Voltage 0.4 0.4 V ISINK = 2 mA
Output High Voltage 4.0 4.0 V ISOURCE = 2 mA
VDD = 3 V ± 10%
Output Low Voltage 0.4 0.4 V ISINK = 2 mA
Output High Voltage 2.4 2.4 V ISOURCE = 2 mA
Floating-State Leakage Current 1 1 μA DCEN = GND
Floating-State Output
Capacitance
3 3 pF DCEN = GND
POWER REQUIREMENTS
VDD 2.5 5.5 2.5 5.5 V IDD specification is valid for all DAC codes
IDD (Normal Mode) Both DACs active and excluding load
currents
VDD = 4.5 V to 5.5 V 300 450 300 450 μA
VDD = 2.5 V to 3.6 V 230 350 230 350 μA
Both DACs in unbuffered mode;
VIH = VDD and VIL = GND; in buffered
mode, extra current is typically x μA
per DAC, where x = 5 μA + VREF/RDAC
IDD (Full Power-Down)
VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 μA
VDD = 2.5 V to 3.6 V 0.05 1 0.05 1 μA
1 Temperature range for Version A, Version B: −40°C to +105°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5303 (Code 8 to Code 248); AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981).
5 Guaranteed by design and characterization, not production tested.
6 In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD
and offset plus gain error must be positive.
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AD5303/AD5313/AD5323
Rev. B | Page 5 of 28
DAC CODE
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
POSITIVE
OFFSET
ERROR
NEGATIVE
OFFSET
ERROR
AMPLIFIER
FOOTROOM
(1mV)
0
04
72
-0
0
5
ACTUAL
IDEAL
DEAD BAND
Figure 2. Transfer Function with Negative Offset
0
04
72
-0
0
6
ACTUAL
IDEAL
DAC CODE
POSITIVE
OFFSET
ERROR
OUTPUT
VOLTAGE
GAIN ERROR
PLUS
OFFSET ERROR
Figure 3. Transfer Function with Positive Offset
Page 7
AD5303/AD5313/AD5323
Rev. B | Page 6 of 28
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A, B Version3
Parameter2 Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time VREF = VDD = 5 V
AD5303 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xc0)
AD5313 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300)
AD5323 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xc00)
Slew Rate 0.7 V/μs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry
(011 . . . 11 to 100 . . . 00)
Digital Feedthrough 0.10 nV-s
Analog Crosstalk 0.01 nV-s
DAC-to-DAC Crosstalk 0.01 nV-s
Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p, unbuffered mode
Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range for Version A and Version B: −40°C to +105°C.
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
Parameter1, 2, 3 (A, B Version) Unit Conditions/Comments
t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 0 ns min SYNC to SCLK rising edge setup time
t5 5 ns min Data setup time
t6 4.5 ns min Data hold time
t7 0 ns min SCLK falling edge to SYNC rising edge
t8 100 ns min Minimum SYNC high time
t9 20 ns min LDAC pulse width
t10 20 ns min SCLK falling edge to LDAC rising edge
t11 20 ns min CLR pulse width
t124, 5 5 ns min SCLK falling edge to SDO invalid
t134, 5 20 ns max SCLK falling edge to SDO valid
t145 0 ns min SCLK falling edge to SYNC rising edge
t155 10 ns min SYNC rising edge to SCLK rising edge
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 4 and Figure 5.
4 These are measured with the load circuit of Figure 4.
5 Daisy-chain mode only (see Figure 47).
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AD5303/AD5313/AD5323
Rev. B | Page 7 of 28
2mA IOL
2mA IOH
1.6VTO OUTPUT
PIN
CL
50pF
00
47
2-
0
02
Figure 4. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
SYNC
DIN* DB15 DB0
LDAC
LDAC
CLR
*SEE THE INPUT SHIFT REGISTER SECTION.
t1
t2t3
t4
t5
t6
t7t8
t9
t10
t11
00
47
2-
00
3
Figure 5. Serial Interface Timing Diagram
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AD5303/AD5313/AD5323
Rev. B | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Reference Input Voltage to GND −0.3 V to VDD + 0.3 V
VOUTA, VOUTB to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ Max) 150°C
16-Lead TSSOP Package
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance 160°C/W
Lead Temperature JEDEC Industry Standard
Soldering J-STD-020
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
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AD5303/AD5313/AD5323
Rev. B | Page 9 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
LDAC
VDD
VREFB
BUF A
VOUTA
VREFA
CLR
BUF B
16
15
14
13
12
11
10
9
GND
DIN
SCLK
PD
DCEN
VOUTB
SYNC
SDO
AD5303/
AD5313/
AD5323
TOP VIEW
(Not to Scale)
0
04
72
-0
04
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLR Active Low Control Input. Loads all zeros to both input and DAC registers.
2 LDAC Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing
this pin low allows either or both DAC registers to be updated if the input registers have new data. This allows
the simultaneous update of both DAC outputs.
3 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
4 VREFB Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state
of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
5 VREFA Reference Input Pin for DAC A. It may be configured as a buffered or an unbuffered input depending on the state
of the BUF A pin. It has an input range from 0 to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
6 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
7 BUF A Control Pin. Controls whether the reference input for DAC A is unbuffered or buffered. If this pin is tied low, the
reference input is unbuffered. If it is tied high, the reference input is buffered.
8 BUF B Control Pin. Controls whether the reference input for DAC B is unbuffered or buffered. If this pin is tied low, the
reference input is unbuffered. If it is tied high, the reference input is buffered.
9 DCEN This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy
chain. The pin should be tied low if it is being used in standalone mode.
10 PD Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software power-down
option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high
impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V).
11 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
12 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the device.
13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
14 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input. The DIN input buffer is powered down after each write cycle.
15 GND Ground Reference Point for All Circuitry on the Part.
16 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the
data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock.