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AD5317RBRUZ

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AD5317RBRUZ

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Part Number AD5317RBRUZ
Manufacturer Analog Devices Inc.
Description IC DAC 10BIT SPI/SRL 16-TSSOP
Datasheet AD5317RBRUZ Datasheet
Package 16-TSSOP (0.173", 4.40mm Width)
In Stock 712 piece(s)
Unit Price $ 7.0900 *
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 6 - Aug 11 (Choose Expedited Shipping)
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Part Number # AD5317RBRUZ (Data Acquisition - Digital to Analog Converters (DAC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD5317RBRUZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet AD5317RBRUZDatasheet
Package16-TSSOP (0.173", 4.40mm Width)
SeriesnanoDAC?
Number of Bits10
Number of D/A Converters4
Settling Time7µs
Output TypeVoltage - Buffered
Differential OutputNo
Data InterfaceSPI
Reference TypeExternal, Internal
Voltage - Supply, Analog2.7 V ~ 5.5 V
Voltage - Supply, Digital2.7 V ~ 5.5 V
INL/DNL (LSB)±0.12, -
ArchitectureString DAC
Operating Temperature-40°C ~ 105°C
Package / Case16-TSSOP (0.173", 4.40mm Width)
Supplier Device Package16-TSSOP
Mounting Type-

AD5317RBRUZ Datasheet

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Quad, 10-Bit nanoDAC® with 2 ppm/°C Reference, SPI Interface Data Sheet AD5317R Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 50 MHz SPI with readback or daisy chain Low glitch: 0.5 nV-sec Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range APPLICATIONS Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems FUNCTIONAL BLOCK DIAGRAM SCLK VLOGIC SYNC SDIN SDO INPUT REGISTER DAC REGISTER STRING DAC A BUFFER VOUTA INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTC INPUT REGISTER DAC REGISTER STRING DAC D BUFFER VOUTD VREFGNDVDD 2.5V REFERENCE POWER- DOWN LOGIC POWER-ON RESET GAIN ×1/×2 IN TE R FA C E LO G IC RSTSEL GAINLDAC RESET AD5317R 10 80 0- 00 1 Figure 1. GENERAL DESCRIPTION The AD5317R, a member of the nanoDAC® family, is a low power, quad, 10-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package. The AD5317R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 µA at 3 V while in power-down mode. The AD5317R employs a versatile SPI interface that operates at clock rates up to 50 MHz and contains a VLOGIC pin intended for 1.8 V/3 V/5 V logic. Table 1. Related Devices Interface Reference 12-Bit 10-Bit SPI Internal AD5684R External AD5684 AD53171 I2C Internal AD5694R AD5316R External AD5694 AD5316 1 The AD5317 and AD5317R are not pin-to-pin or software compatible. PRODUCT HIGHLIGHTS 1. Precision DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum 2. Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficient 3. Two Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP

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AD5317R Data Sheet Rev. B | Page 2 of 28 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Characteristics ........................................................................ 5 Timing Characteristics ................................................................ 6 Daisy-Chain and Readback Timing Characteristics ............... 7 Absolute Maximum Ratings ............................................................ 9 ESD Caution .................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 19 Digital-to-Analog Converter .................................................... 19 Transfer Function ....................................................................... 19 DAC Architecture ....................................................................... 19 Serial Interface ............................................................................ 20 Standalone Operation ................................................................ 21 Write and Update Commands .................................................. 21 Daisy-Chain Operation ............................................................. 21 Readback Operation .................................................................. 22 Power-Down Operation ............................................................ 22 Load DAC (Hardware LDAC Pin) ........................................... 23 LDAC Mask Register ................................................................. 23 Hardware Reset (RESET) .......................................................... 24 Reset Select Pin (RSTSEL) ........................................................ 24 Internal Reference Setup ........................................................... 25 Solder Heat Reflow ..................................................................... 25 Long-Term Temperature Drift ................................................. 25 Thermal Hysteresis .................................................................... 25 Applications Information .............................................................. 26 Microprocessor Interfacing ....................................................... 26 AD5317R to ADSP-BF531 Interface ........................................ 26 AD5317R to SPORT Interface .................................................. 26 Layout Guidelines....................................................................... 26 Galvanically Isolated Interface ................................................. 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 REVISION HISTORY 5/2017—Rev. A to Rev. B Changes to Table 2 Summary .......................................................... 3 Changes to Table 3 ............................................................................ 5 Changes to Table 4 and Figure 2 ..................................................... 6 Changes to Table 5 and Figure 4 ..................................................... 7 Changes to Figure 5 .......................................................................... 8 Changes to Table 6 ............................................................................ 9 Changes to VLOGIC Pin Description and RESET Pin Description, Table 7 .............................................................................................. 10 Changes to Figure 16 to Figure 19 ................................................ 12 Changes to Figure 20 to Figure 24 ................................................ 13 Changes to Figure 30 ...................................................................... 14 Changes to Figure 37 ...................................................................... 15 Changes to Figure 38 ...................................................................... 16 Changes to Table 8 .......................................................................... 20 Changes to Readback Operation Section .................................... 22 Changes to Hardware Reset (RESET) Section ............................ 24 Added Long-Term Temperature Drift Section and Figure 49; Renumbered Sequentially .............................................................. 25 Changes to Ordering Guide .......................................................... 28 2/2014—Rev. 0 to Rev. A Change to Table 2 .............................................................................. 3 Change to Table 7 ........................................................................... 10 Deleted Figure 10, Renumbered Sequentially ............................ 11 Deleted Long-Term Temperature Drift Section and Figure 50 ...................................................................................... 1025 7/2012—Revision 0: Initial Version

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Data Sheet AD5317R Rev. B | Page 3 of 28 SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE1 Resolution 10 Bits Relative Accuracy ±0.12 ±0.5 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design Zero-Code Error 0.4 1.5 mV All 0s loaded to DAC register Offset Error +0.1 ±1.5 mV Full-Scale Error +0.01 ±0.1 % of FSR All 1s loaded to DAC register Gain Error ±0.02 ±0.1 % of FSR Total Unadjusted Error ±0.01 ±0.1 % of FSR External reference; gain = 2; TSSOP ±0.2 % of FSR Internal reference; gain = 1; TSSOP Offset Error Drift2 ±1 µV/°C Gain Temperature Coefficient2 ±1 ppm Of FSR/°C DC Power Supply Rejection Ratio2 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10% DC Crosstalk2 ±2 µV Due to single channel, full-scale output change ±3 µV/mA Due to load current change ±2 µV Due to power-down (per channel) OUTPUT CHARACTERISTICS2 Output Voltage Range 0 VREF V Gain = 1 0 2 × VREF V Gain = 2, see Figure 28 Capacitive Load Stability 2 nF RL = ∞ 10 nF RL = 1 kΩ Resistive Load3 1 kΩ Load Regulation 80 µV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ +30 mA 80 µV/mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ IOUT ≤ +20 mA Short-Circuit Current4 40 mA Load Impedance at Rails5 25 Ω See Figure 28 Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V REFERENCE OUTPUT Output Voltage6 2.4975 2.5025 V At ambient Reference TC7, 8 2 5 ppm/°C See the Terminology section Output Impedance2 0.04 Ω Output Voltage Noise2 12 µV p-p 0.1 Hz to 10 Hz Output Voltage Noise Density2 240 nV/√Hz At ambient; f = 10 kHz, CL = 10 nF Load Regulation, Sourcing2 20 µV/mA At ambient Load Regulation, Sinking2 40 µV/mA At ambient Output Current Load Capability2 ±5 mA VDD ≥ 3 V Line Regulation2 100 µV/V At ambient Thermal Hysteresis2 125 ppm First cycle 25 ppm Additional cycles

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AD5317R Data Sheet Rev. B | Page 4 of 28 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS2 Input Current ±2 µA Per pin Input Low Voltage, VINL 0.3 × VLOGIC V Input High Voltage, VINH 0.7 × VLOGIC V Pin Capacitance 2 pF LOGIC OUTPUTS (SDO)2 Output Low Voltage, VOL 0.4 V ISINK = 200 μA Output High Voltage, VOH VLOGIC − 0.4 V ISOURCE = 200 μA Floating State Output Capacitance 4 pF POWER REQUIREMENTS VLOGIC 1.62 5.5 V ILOGIC 3 µA VDD 2.7 5.5 V Gain = 1 VREF + 1.5 5.5 V Gain = 2 IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V Normal Mode9 0.59 0.7 mA Internal reference off 1.1 1.3 mA Internal reference on, at full scale All Power-Down Modes10 1 4 µA −40°C to +85°C 6 µA −40°C to +105°C 1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 4 to 1020. 2 Guaranteed by design and characterization; not production tested. 3 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA up to a junction temperature of 110°C. 4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum operation junction temperature may impair device reliability. 5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 28). 6 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Terminology section. 7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C. 8 Reference temperature coefficient calculated as per the box method. See the Terminology section for more information. 9 Interface inactive. All DACs active. DAC outputs unloaded. 10 All DACs powered down.

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Data Sheet AD5317R Rev. B | Page 5 of 28 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1 Table 3. Parameter2 Min Typ Max Unit Test Conditions/Comments3 Output Voltage Settling Time 5 7 µs ¼ to ¾ scale settling to ±1 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry Digital Feedthrough 0.13 nV-sec Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec Total Harmonic Distortion4 −80 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz Output Noise Spectral Density 300 nV/√Hz DAC code = midscale, 10 kHz, gain = 2, internal reference enabled Output Noise 6 µV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical @ 25°C. 4 Digitally generated sine wave @ 1 kHz.

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AD5317R Data Sheet Rev. B | Page 6 of 28 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. 1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V Parameter1 Symbol Min Max Min Max Unit SCLK Cycle Time t1 20 20 ns SCLK High Time t2 10 10 ns SCLK Low Time t3 10 10 ns SYNC to SCLK Falling Edge Setup Time t4 15 10 ns Data Setup Time t5 5 5 ns Data Hold Time t6 5 5 ns SCLK Falling Edge to SYNC Rising Edge t7 10 10 ns Minimum SYNC High Time t8 20 20 ns SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates) t9 870 830 ns SYNC Falling Edge to SCLK Fall Ignore t10 16 10 ns LDAC Pulse Width Low t11 15 15 ns SYNC Rising Edge to LDAC Rising Edge t12 20 20 ns SYNC Rising Edge to LDAC Falling Edge t13 30 30 ns LDAC Falling Edge to SYNC Rising Edge t14 840 800 ns Minimum Pulse Width Low t15 30 30 ns Pulse Activation Time t16 30 30 ns Power-Up Time2 4.5 4.5 µs 1Guaranteed by design and characterization; not production tested. 2 Time to exit power-down to normal mode of AD5686R/AD5685R/AD5684R operation, SYNCE rising edge to 90% of DAC midscale value, with output unloaded. t4 t3 SCLK SYNC SDIN t1 t2 t5 t6 t7 t14 t9 t8 DB23 t10 t11 t12 LDAC1 LDAC2 t13 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. RESET t15 t16VOUT DB0 10 80 0- 00 2 Figure 2. Serial Write Operation

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Data Sheet AD5317R Rev. B | Page 7 of 28 17BDAISY-CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 5. 1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V Parameter16F1 Symbol Min Max Min Max Unit SCLK Cycle Time t1 66 40 ns SCLK High Time t2 33 20 ns SCLK Low Time t3 33 20 ns ASYNC EEA to SCLK Falling Edge t4 33 20 ns Data Setup Time t5 5 5 ns Data Hold Time t6 5 5 ns SCLK Falling Edge to ASYNC EEA Rising Edge t7 15 10 ns Minimum ASYNC EEA High Time t8 60 30 ns SDO Data Valid from SCLK Rising Edge t9 45 30 ns ASYNC EEA Rising Edge to SCLK Falling Edge t10 15 10 ns ASYNC EEA Rising Edge to SDO Disable t11 60 60 ns 1 Guaranteed by design and characterization; not production tested. 42BCircuit and Timing Diagrams 200µA IOL 200µA IOH VOH (MIN)TO OUTPUTPIN CL 20pF 10 80 0- 00 3 Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications t4 t1 t2 t3 t5 t6 t8 SDO SDIN SYNC SCLK 4824 DB23 DB0 DB23 DB0 DB23 INPUT WORD FOR DAC NUNDEFINED INPUT WORD FOR DAC N + 1INPUT WORD FOR DAC N DB0 t7 t10 t9 10 80 0- 00 4 Figure 4. Daisy-Chain Timing Diagram

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AD5317R Data Sheet Rev. B | Page 8 of 28 SYNC t8 t6 SCLK 241 241 t8t4 t2 t10 t7 t3 t1 DB23 DB0 DB23 DB0SDIN NOP CONDITIONINPUT WORD SPECIFIES REGISTER TO BE READ t5 DB23 DB0SDO SELECTED REGISTER DATA CLOCKED OUT HI-Z t9 t11 10 80 0- 00 5 Figure 5. Readback Timing Diagram

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Data Sheet AD5317R Rev. B | Page 9 of 28 1BABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter Rating VDD to GND −0.3 V to +7 V VLOGIC to GND −0.3 V to +7 V VOUT to GND −0.3 V to VDD + 0.3 V VREF to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to VLOGIC + 0.3 V Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 125°C 16-Lead TSSOP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) 112.6°C/W 16-Lead LFCSP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) 70°C/W Reflow Soldering Peak Temperature, Pb Free (J-STD-020) 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 18BESD CAUTION

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Terr***** Young

July 16, 2020

These are great for projects with the kids or doing any type of DIY projects. The case is nice to keep everything separated. Very nice.

Maxt*****utta

July 8, 2020

This product is very easy to replace and solved my problem.

Laur*****oswami

June 26, 2020

All of the components worked, and are still working. So even though the price is amazingly low, the diodes really do work!

Terr***** Yang

June 21, 2020

I was able to make my list of needed parts and use suggested products. The big plus is the fact they show inventory quantity.

Jayl*****Chang

June 17, 2020

Well packed in anti-static bags. Repaired my amp perfectly - thank you!

Sky*****Hogan

June 16, 2020

Outstanding supplier! Heisener is on a very short list of suppliers I can recommend. From stock, pricing, ease of ordering and great service, they get it all.

Ivo*****Blair

June 16, 2020

EXACTLY what I was looking for -- one piece with a low forward voltage drop to isolate some DC power sources. They work fantastic!

Lanc*****uirre

June 14, 2020

Item works as described, fast delivery, nice contact!

Ahmad*****ington

June 11, 2020

Fast delivery, good quality, 100% satisfacted

Gatl*****onway

June 11, 2020

Used this on starter solenoid and works as expected.

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