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AD5320BRT-500RL7

hotAD5320BRT-500RL7

AD5320BRT-500RL7

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Part Number AD5320BRT-500RL7
Manufacturer Analog Devices Inc.
Description IC DAC 12BIT R-R W/BUFF SOT23-6
Datasheet AD5320BRT-500RL7 Datasheet
Package SOT-23-6
In Stock 1,333 piece(s)
Unit Price $ 5.2080 *
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 7 - Aug 12 (Choose Expedited Shipping)
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Part Number # AD5320BRT-500RL7 (Data Acquisition - Digital to Analog Converters (DAC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD5320BRT-500RL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet AD5320BRT-500RL7Datasheet
PackageSOT-23-6
Series-
Number of Bits12
Number of D/A Converters1
Settling Time10µs
Output TypeVoltage - Buffered
Differential OutputNo
Data InterfaceSPI, DSP
Reference TypeSupply
Voltage - Supply, Analog2.7 V ~ 5.5 V
Voltage - Supply, Digital2.7 V ~ 5.5 V
INL/DNL (LSB)±16 (Max), ±1 (Max)
ArchitectureString DAC
Operating Temperature-40°C ~ 105°C
Package / CaseSOT-23-6
Supplier Device PackageSOT-23-6
Mounting Type-

AD5320BRT-500RL7 Datasheet

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2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output 12-Bit DAC in an SOT-23 AD5320 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. FEATURES Single 12-bit DAC 6-lead SOT-23 and 8-lead MSOP packages Micropower operation: 140 μA @ 5 V Power-down to 200 nA @ 5 V, 50 nA @ 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Reference derived from power supply Power-on reset to zero volts Three power-down functions Low power serial interface with Schmitt-triggered inputs On-chip output buffer amplifier, rail-to-rail operation SYNC interrupt facility APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators FUNCTIONAL BLOCK DIAGRAM VDD VOUT GND AD5320 12-BIT DAC SCLK DIN REF (+) REF (–) REGISTER NETWORK POWER-DOWN CONTROL LOGIC DAC REGISTER OUTPUT BUFFER POWER-ON RESET SYNC INPUT CONTROL LOGIC 0 0 9 3 4- 0 0 1 Figure 1. GENERAL DESCRIPTION The AD53201 is a single, 12-bit buffered voltage out digital-to- analog converter (DAC) that operates from a single 2.7 V to 5.5 V supply consuming 115 μA at 3 V. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The AD5320 utilizes a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™ and digital signal processing (DSP) interface standards. The reference for AD5320 is derived from the power supply inputs and thus gives the widest dynamic output range. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to zero volts and remains there until a valid write takes place to the device. The part contains a power- down feature that reduces the current consumption of the device to 200 nA at 5 V and provides software selectable output loads while in power-down mode. The part is put into power- down mode over the serial interface. The low power consumption of this part in normal operation makes it ideally suited to portable, battery-operated equipment. The power consumption is 0.7 mW at 5 V reducing to 1 μW in power-down mode. 1 Patent pending; protected by U.S. Patent No. 5684481. The AD5320 is one of a family of pin-compatible DACs. The AD5300 is the 8-bit version and the AD5310 is the 10-bit version. The AD5300/AD5310/AD5320 are available in 6-lead SOT-23 packages and 8-lead MSOP packages. PRODUCT HIGHLIGHTS 1. Available in 6-lead SOT-23 and 8-lead MSOP packages. 2. Low power, single-supply operation. This part operates from a single 2.7 V to 5.5 V supply and typically consumes 0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for battery-powered applications. 3. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a slew rate of 1 V/μs. 4. Reference derived from the power supply. 5. High speed serial interface with clock speeds up to 30 MHz. Designed for very low power consumption. The interface only powers up during a write cycle. 6. Power-down capability. When powered down, the DAC typically consumes 50 nA at 3 V and 200 nA at 5 V.

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AD5320 Rev. C | Page 2 of 20 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Terminology ...................................................................................... 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 11 D/A Section................................................................................. 11 Resistor String ............................................................................. 11 Output Amplifier........................................................................ 11 Serial Interface ................................................................................ 12 Input Shift Register .................................................................... 12 SYNC Interrupt .......................................................................... 12 Power-On Reset .......................................................................... 12 Power-Down Modes .................................................................. 13 Microprocessor Interfacing........................................................... 14 AD5320 to ADSP-2101/ADSP-2103 Interface ....................... 14 AD5320 to 68HC11/68L11 Interface....................................... 14 AD5320 to 80C51/80L51 Interface .......................................... 14 AD5320 to MICROWIRE Interface......................................... 14 Applications..................................................................................... 15 Using REF19x as a Power Supply for AD5320 ....................... 15 Bipolar Operation Using the AD5320 ..................................... 15 Using AD5320 with an Opto-Isolated Interface .................... 15 Power Supply Bypassing and Grounding................................ 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 REVISION HISTORY 11/05—Rev. B to Rev. C Updated Format..................................................................Universal Changes to Table 4............................................................................ 6 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17

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AD5320 Rev. C | Page 3 of 20 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. B Version1 Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 Resolution 12 Bits Relative Accuracy ±16 LSB See Figure 5 Differential Nonlinearity ±1 LSB Guaranteed monotonic by design (see Figure 6) Zero-Code Error 5 40 mV All zeroes loaded to DAC register (see Figure 9) Full-Scale Error −0.15 −1.25 % of FSR All ones loaded to DAC register (see Figure 9) Gain Error ±1.25 % of FSR Zero-Code Error Drift −20 μV/°C Gain Temperature Coefficient −5 ppm of FSR/°C OUTPUT CHARACTERISTICS3 Output Voltage Range 0 VDD V Output Voltage Settling Time 8 10 μs 1/4 scale to 3/4 scale change (400 hex to C00 hex) RL = 2 kΩ, 0 pF < CL < 200 pF (see Figure 19) 12 μs RL = 2 kΩ, CL = 500 pF Slew Rate 1 V/μs Capacitive Load Stability 470 pF RL = ∞ 1000 pF RL = 2 kΩ Digital-to-Analog Glitch Impulse 20 nV-s 1 LSB change around major carry (see Figure 22) Digital Feedthrough 0.5 nV-s DC Output Impedance 1 Ω Short Circuit Current 50 mA VDD = 5 V 20 mA VDD = 3 V Power-Up Time 2.5 μs Coming out of power-down mode, VDD = 5 V 5 μs Coming out of power-down mode, VDD = 3 V LOGIC INPUTS3 Input Current ±1 μA VINL, Input Low Voltage 0.8 V VDD = 5 V VINL, Input Low Voltage 0.6 V VDD = 3 V VINH, Input High Voltage 2.4 V VDD = 5 V VINH, Input High Voltage 2.1 V VDD = 3 V Pin Capacitance 3 pF POWER REQUIREMENTS VDD 2.7 5.5 V IDD (Normal Mode) DAC active and excluding load current VDD = 4.5 V to 5.5 V 140 250 μA VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 115 200 μA VIH = VDD and VIL = GND IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V 0.2 1 μA VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 0.05 1 μA VIH = VDD and VIL = GND POWER EFFICIENCY IOUT/IDD 93 % ILOAD = 2 mA, VDD = 5 V 1 Temperature range is as follows: B Version: −40°C to +105°C. 2 Linearity calculated using a reduced code range of 48 to 4047; output unloaded. 3 Guaranteed by design and characterization, not production tested.

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AD5320 Rev. C | Page 4 of 20 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Limit at TMIN, TMAX Parameter1, 2 VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Description t13 50 33 ns min SCLK cycle time t2 13 13 ns min SCLK high time t3 22.5 13 ns min SCLK low time t4 0 0 ns min SYNC to SCLK rising edge setup time t5 5 5 ns min Data setup time t6 4.5 4.5 ns min Data hold time t7 0 0 ns min SCLK falling edge to SYNC rising edge t8 50 33 ns min Minimum SYNC high time 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 See Figure 2. 3 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V. 0 09 34 -0 02 SCLK DIN DB15 DB0 t4 t1 t3 t2 t8 t7 t6 t5 SYNC Figure 2. Serial Write Operation

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AD5320 Rev. C | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Ratings VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V VOUT to GND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ Max) 150°C SOT-23 Package Power Dissipation (TJ Max − TA)/θJA θJA Thermal Impedance 240°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C MSOP Package 450 mW Power Dissipation (TJ Max − TA)/θJA θJA Thermal Impedance 206°C/W θJC Thermal Impedance 44°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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AD5320 Rev. C | Page 6 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD5320 TOP VIEW (Not to Scale) VOUT 1 GND 2 VDD 3 SYNC SCLK DIN 6 5 4 0 0 93 4 -0 03 Figure 3. SOT-23 Pin Configuration AD5320 TOP VIEW (Not to Scale) VDD 1 NC 2 NC 3 VOUT 4 SYNC SCLK DIN GND8 7 6 5 0 0 9 3 4 -0 0 4 NC = NO CONNECT Figure 4. MSOP Pin Configuration Table 4. Pin Function Descriptions SOT-23 Pin No. MSOP Pin No. Mnemonic Description 1 4 VOUT Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. 2 8 GND Ground Reference Point for All Circuitry on the Part. 3 1 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and VDD should be decoupled to GND. 4 7 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 5 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 6 5 SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 2, 3 NC No Connect.

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AD5320 Rev. C | Page 7 of 20 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 5. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 6. Zero-Code Error Zero-code error is a measure of the output error when zero code (000 hex) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5320 because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. A plot of zero- code error vs. temperature can be seen in Figure 9. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (FFF Hex) is loaded to the DAC register. Ideally the output should be VDD − 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error vs. temperature can be seen in Figure 9. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error considering all the various errors. A typical TUE vs. code plot can be seen in Figure 7. Zero-Code Error Drift This is a measure of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV seconds and is measured when the digital input code is changed by 1 LSB at the major carry transition (7FF Hex to 800 Hex); see Figure 22. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV seconds and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.

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AD5320 Rev. C | Page 8 of 20 TYPICAL PERFORMANCE CHARACTERISTICS INL @ 5V INL @ 3V CODE IN L E R R O R ( L S B s) 16 12 4 –4 –12 8 0 –8 –16 0 800 1600 2400 40003200 00 93 4- 0 05 TA = 25°C Figure 5. Typical INL Plot CODE D N L E R R O R ( L S B s) 1.0 0.5 0 –0.5 –1.0 0 1000 2000 3000 4000 00 93 4- 0 06 DNL @ 3V DNL @ 5V TA = 25°C Figure 6. Typical DNL Plot CODE T U E ( L S B s) 16 8 0 –8 –16 0 800 1600 2400 40003200 00 93 4- 0 07 TUE @ 3V TUE @ 5V TA = 25°C Figure 7. Typical Total Unadjusted Error Plot MAX INL MAX DNL MIN INL MIN DNL TEMPERATURE (°C) –40 0 40 80 120 00 93 4- 0 08 16 12 4 –4 –12 8 0 –8 –16 E R R O R ( L S B s) Figure 8. INL Error and DNL Error vs. Temperature VDD = 5V ZS ERROR FS ERROR 30 20 30 0 10 20 10 TEMPERATURE (°C) E R R O R ( m V ) –40 0 40 80 120 00 93 4- 00 9 Figure 9. Zero-Scale Error and Full-Scale Error vs. Temperature 2500 2000 500 50 190 1500 1000 0 F R E Q U E N C Y VDD = 3V VDD = 5V 60 70 80 90 100 110 120 130 140 150 160 170 180 0 09 3 4- 0 10 IDD (µA) Figure 10. IDD Histogram with VDD = 3 V and VDD = 5 V

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AD5320 Rev. C | Page 9 of 20 DAC LOADED WITH FFF HEX DAC LOADED WITH 000 HEX ISOURCE/SINK (mA) V O U T ( V ) 3 2 1 0 0 5 10 0 09 34 -0 11 TA = 25°C 15 Figure 11. Source and Sink Current Capability with VDD = 3 V 5 4 3 2 1 DAC LOADED WITH 000 HEX DAC LOADED WITH FFF HEX ISOURCE/SINK (mA) V O U T ( V ) 0 0 5 10 0 09 34 -0 1 2 15 TA = 25°C Figure 12. Source and Sink Current Capability with VDD = 5 V CODE I D D ( µ A ) 0 800 1600 2400 3200 4000 00 93 4- 0 13 500 400 0 300 200 100 VDD = 5V VDD = 3V Figure 13. Supply Current vs. Code TEMPERATURE °C I D D ( µ A ) 300 200 150 50 0 –40 0 40 80 120 00 93 4- 0 14 VDD = 5V Figure 14. Supply Current vs. Temperature VDD (V) 2.7 3.2 3.73.7 4.2 4.7 5 00 93 4- 0 15 300 250 200 150 100 50 0 I D D ( µ A ) TA = 25°C Figure 15. Supply Current vs. Supply Voltage 2.7 3.2 3.7 4.7 5.24.2 00 93 4 -0 1 6 1.0 0.9 0 0.4 0.3 0.2 0.1 0.8 0.6 0.7 0.5 –40°C CONDITION THREE-STATE VDD (V) I D D ( µ A ) +25°C +105°C Figure 16. Power-Down Current vs. Supply Voltage

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