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AD5421BREZ

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AD5421BREZ

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Part Number AD5421BREZ
Manufacturer Analog Devices Inc.
Description IC DAC 16BIT 1.8-12V 28TSSOP
Datasheet AD5421BREZ Datasheet
Package 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
In Stock 461,776 piece(s)
Unit Price $ 11.9700 *
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 2 - Dec 7 (Choose Expedited Shipping)
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Part Number # AD5421BREZ (Data Acquisition - Digital to Analog Converters (DAC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD5421BREZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet AD5421BREZDatasheet
Package28-TSSOP (0.173", 4.40mm Width) Exposed Pad
Series-
Number of Bits16
Number of D/A Converters1
Settling Time50µs (Typ)
Output TypeVoltage - Unbuffered
Differential OutputNo
Data InterfaceSPI, DSP
Reference TypeExternal, Internal
Voltage - Supply, Analog1.71 V ~ 5.5 V
Voltage - Supply, Digital3.17 V ~ 3.48 V
INL/DNL (LSB)-, ±1 (Max)
ArchitectureCyclic Serial
Operating Temperature-40°C ~ 105°C
Package / Case28-TSSOP (0.173", 4.40mm Width) Exposed Pad
Supplier Device Package28-TSSOP-EP
Mounting Type-

AD5421BREZ Datasheet

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16-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC Data Sheet AD5421 Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 16-bit resolution and monotonicity Pin selectable NAMUR-compliant ranges 4 mA to 20 mA 3.8 mA to 21 mA 3.2 mA to 24 mA NAMUR-compliant alarm currents Downscale alarm current = 3.2 mA Upscale alarm current = 22.8 mA/24 mA Total unadjusted error (TUE): 0.05% maximum INL error: 0.0035% FSR maximum Output TC: 3 ppm/°C typical Quiescent current: 300 μA maximum Flexible SPI-compatible serial digital interface with Schmitt triggered inputs On-chip fault alerts via FAULT pin or alarm current Automatic readback of fault register on each write cycle Slew rate control function Gain and offset adjust registers On-chip reference TC: 4 ppm/°C maximum Selectable regulated voltage output Loop voltage range: 5.5 V to 52 V Temperature range: −40°C to +105°C TSSOP and LFCSP packages APPLICATIONS Industrial process control 4 mA to 20 mA loop-powered transmitters Smart transmitters HART network connectivity GENERAL DESCRIPTION The AD5421 is a complete, loop-powered, 4 mA to 20 mA digital-to-analog converter (DAC) designed to meet the needs of smart transmitter manufacturers in the industrial control industry. The DAC provides a high precision, fully integrated, low cost solution in compact TSSOP and LFCSP packages. The AD5421 includes a regulated voltage output that is used to power itself and other devices in the transmitter. This regulator provides a regulated 1.8 V to 12 V output voltage. The AD5421 also contains 1.22 V and 2.5 V references, thus eliminating the need for a discrete regulator and voltage reference. The AD5421 can be used with standard Highway Addressable Remote Transducer (HART®) FSK protocol communication circuitry without any degradation in specified performance. The high speed serial interface is capable of operating at 30 MHz and allows for simple connection to commonly used microprocessors and microcontrollers via a SPI-compatible, 3-wire interface. The AD5421 is guaranteed monotonic to 16 bits. It provides 0.0015% integral nonlinearity, 0.0012% offset error, and 0.0006% gain error under typical conditions. The AD5421 is available in a 28-lead TSSOP and a 32-lead LFCSP specified over the extended industrial temperature range of −40°C to +105°C. COMPANION LOW POWER PRODUCTS HART Modem: AD5700, AD5700-1 Microcontroller: ADuCM360 FUNCTIONAL BLOCK DIAGRAM RSET 24kΩ SYNC SCLK SDIN SDO LDAC RANGE0 RANGE1 ALARM_CURRENT_DIRECTION FAULT RINT/REXT INPUT REGISTER CONTROL LOGIC GAIN/OFFSET ADJUSTMENT REGISTERS TEMPERATURE SENSOR REFOUT2 REFIN CIN REXT1 REXT2REFOUT1 VREF 16 16-BIT DAC LOOP VOLTAGE MONITOR VLOOPDVDDIODVDD AD5421 VOLTAGE REGULATOR REG_SEL0 REG_SEL1 REG_SEL2 REGOUT REGIN DRIVE LOOP– 11.5kΩ 52Ω 09 12 8- 00 1 COM Figure 1.

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AD5421 Data Sheet Rev. I | Page 2 of 36 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Companion Low Power Products .................................................. 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 AC Performance Characteristics ................................................ 9 Timing Characteristics ................................................................ 9 Absolute Maximum Ratings .......................................................... 11 Thermal Resistance .................................................................... 11 ESD Caution ................................................................................ 11 Pin Configurations and Function Descriptions ......................... 12 Typical Performance Characteristics ........................................... 14 Terminology .................................................................................... 20 Theory of Operation ...................................................................... 21 Fault Alerts .................................................................................. 21 External Current Setting Resistor ............................................ 22 Loop Current Range Selection .................................................. 22 Connection to Loop Power Supply .......................................... 22 On-Chip ADC ............................................................................ 23 Voltage Regulator ....................................................................... 23 Loop Current Slew Rate Control .............................................. 23 Power-On Default ...................................................................... 24 HART Communications ........................................................... 24 Serial Interface ................................................................................ 26 Input Shift Register .................................................................... 26 Register Readback ...................................................................... 26 DAC Register .............................................................................. 27 Control Register ......................................................................... 28 Fault Register .............................................................................. 29 Offset Adjust Register ................................................................ 30 Gain Adjust Register .................................................................. 30 Applications Information .............................................................. 32 Determining the Expected Total Error ................................... 32 Thermal and Supply Considerations ....................................... 34 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 36

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Data Sheet AD5421 Rev. I | Page 3 of 36 REVISION HISTORY 11/2018—Rev. H to Rev. I Change to Table 7 ............................................................................ 11 Changes to Figure 6 ......................................................................... 12 Updated Outline Dimensions ........................................................ 35 Changes to Ordering Guide ........................................................... 36 11/2014—Rev. G to Rev. H Changes to Offset Adjust Register Section and Gain Adjust Register Section ............................................................................... 30 10/2013—Rev. F to Rev. G Added Figure 4; Renumbered Sequentially ................................. 10 Change to Table 7 ............................................................................ 11 Changes to Fault Alerts Section .................................................... 21 Added Table 11; Renumbered Sequentially ................................. 24 Moved Figure 48 .............................................................................. 25 Changes to Applications Information Section ............................ 32 Changes to Figure 51 ...................................................................... 33 1/2013—Rev. E to Rev. F Moved Revision History Section ..................................................... 3 Change to Table 7 ............................................................................ 11 Changes to Table 8 .......................................................................... 13 Changes to On-Chip ADC Section ............................................... 23 Changes to Table 19 and On-Chip ADC Transfer Function Equations Section ............................................................................ 29 7/2012—Rev. D to Rev. E Changes to Figure 1 and Companion Products Section .............. 1 Changes to Pin LOOP− Description ............................................ 12 Changes to Applications Information Section and Figure 49 ... 31 Added Figure 50 .............................................................................. 32 5/2012—Rev. C to Rev. D Changes to Features Section and Applications Section; Added Companion Products Section .......................................................... 1 Changes to Line Regulation Parameter, Table 1 ............................ 5 Updated Outline Dimensions ........................................................ 33 12/2011—Rev. B to Rev. C Change to REFOUT1 Pin, Capacitive Load Parameter, Test Conditions, Table 1 ........................................................................... 4 Change to REGOUT Output, Capacitive Load Parameter, Test Conditions, Table 1 ........................................................................... 5 Changes to ESD Parameter, Table 6 .............................................. 10 12/2011—Rev. A to Rev. B Added 32-Lead LFCSP ...................................................... Universal Changes to the Specifications Section, Table 1 ............................. 3 Changes to Table 7 .......................................................................... 10 Added Figure 5, Renumbered Sequentially ................................. 11 Changes to Table 8 .......................................................................... 11 Changes to Figure 33 ...................................................................... 17 Changes to the On-Chip ADC Section ........................................ 22 Changes to Figure 46 ...................................................................... 23 Changes to Figure 48 ...................................................................... 24 Changes to the Register Readback Section .................................. 25 Updated Outline Dimensions ........................................................ 33 Changes to Ordering Guide ........................................................... 34 5/2011—Rev. 0 to Rev. A Changes to REGIN, REFOUT1, and REFOUT2 Pin Descriptions in Table 8 ................................................................... 10 Change to Figure 45 ........................................................................ 22 Changes to Input Shift Register Section, Table 11, and Register Readback Section ............................................................................ 24 Changes to Figure 48 ...................................................................... 30 2/2011—Revision 0: Initial Version

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AD5421 Data Sheet Rev. I | Page 4 of 36 SPECIFICATIONS Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 Min Typ Max Unit Test Conditions/Comments ACCURACY, INTERNAL RSET Resolution 16 Bits Total Unadjusted Error (TUE)2 −0.126 +0.126 % FSR C grade −0.041 ±0.0064 +0.041 % FSR C grade, TA = 25°C −0.18 +0.18 % FSR B grade −0.06 ±0.011 +0.06 % FSR B grade, TA = 25°C −0.27 +0.27 % FSR A grade −0.08 ±0.011 +0.08 A grade, TA = 25°C TUE Long-Term Stability 210 ppm FSR Drift after 1000 hours at TA = 125°C Relative Accuracy (INL) −0.0035 ±0.0015 +0.0035 % FSR C grade −0.012 ±0.006 +0.012 % FSR B grade −0.024 ±0.01 +0.024 % FSR A grade Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.056 +0.056 % FSR B grade and C grade −0.008 ±0.0008 +0.008 % FSR B grade and C grade, TA = 25°C −0.11 ±0.0008 +0.11 % FSR A grade Offset Error TC3 1 ppm FSR/°C Gain Error −0.107 +0.107 % FSR B grade and C grade −0.035 ±0.0058 +0.035 % FSR B grade and C grade, TA = 25°C −0.2 ±0.0058 +0.2 % FSR A grade Gain Error TC3 4 ppm FSR/°C Full-Scale Error −0.126 +0.126 % FSR B grade and C grade −0.041 ±0.0065 +0.041 % FSR B grade and C grade, TA = 25°C −0.25 ±0.0065 +0.25 % FSR A grade Full-Scale Error TC3 5 ppm FSR/°C Downscale Alarm Current 3.19 3.21 mA Upscale Alarm Current 22.77 22.83 mA 4 mA to 20 mA and 3.8 mA to 21 mA ranges 23.97 24.03 mA 3.2 mA to 24 mA range ACCURACY, EXTERNAL RSET (24 kΩ) Assumes ideal resistor, B grade and C grade only; not specified for A grade Resolution 16 Bits Total Unadjusted Error (TUE)2 −0.048 +0.048 % FSR C grade −0.027 ±0.002 +0.027 % FSR C grade, TA = 25°C −0.08 +0.08 % FSR B grade −0.04 ±0.003 +0.04 % FSR B grade, TA = 25°C TUE Long-Term Stability 40 ppm FSR Drift after 1000 hours at TA = 125°C Relative Accuracy (INL) −0.0035 ±0.0015 +0.0035 % FSR C grade −0.012 ±0.006 +0.012 % FSR B grade Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.021 +0.021 % FSR −0.007 ±0.0012 +0.007 % FSR TA = 25°C Offset Error TC3 0.5 ppm FSR/°C Gain Error −0.03 +0.03 % FSR −0.023 ±0.0006 +0.023 % FSR TA = 25°C

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Data Sheet AD5421 Rev. I | Page 5 of 36 Parameter1 Min Typ Max Unit Test Conditions/Comments Gain Error TC3 1 ppm FSR/°C Full-Scale Error −0.047 +0.047 % FSR −0.028 ±0.0017 +0.028 % FSR TA = 25°C Full-Scale Error TC3 1 ppm FSR/°C Downscale Alarm Current 3.08 3.21 mA Upscale Alarm Current 22.78 23 mA 4 mA to 20 mA and 3.8 mA to 21 mA ranges 23.99 24.01 mA 3.2 mA to 24 mA range OUTPUT CHARACTERISTICS3 Loop Compliance Voltage4 LOOP− + 5.5 V REGOUT < 5.5 V, loop current = 24 mA LOOP− + 12.5 V REGOUT = 12 V, loop current = 24 mA Loop Current Long-Term Stability 100 ppm FSR Drift after 1000 hours at TA = 125°C, loop current = 12 mA, internal RSET 15 ppm FSR Drift after 1000 hours at TA = 125°C, loop current = 12 mA, external RSET Loop Current Error vs. REGOUT Load Current 1.2 µA/mA Loop current = 12 mA, load current from REGOUT = 5 mA Resistive Load 0 2 kΩ See Figure 21 for a load line graph Inductive Load 50 mH Stable operation Power Supply Sensitivity 0.1 µA/V Loop current = 12 mA Output Impedance 12 400 MΩ Output TC 3 ppm FSR/°C Loop current = 12 mA, internal RSET 1 ppm FSR/°C Loop current = 12 mA, external RSET Output Noise 0.1 Hz to 10 Hz 50 nA p-p 500 Hz to 10 kHz 0.2 mV rms HART bandwidth; measured across 500 Ω load Noise Spectral Density 195 nA/√Hz At 1 kHz 256 nA/√Hz At 10 kHz REFERENCE INPUT (REFIN PIN)3 Reference Input Voltage5 2.5 V For specified performance DC Input Impedance 75 800 MΩ REFERENCE OUTPUTS REFOUT1 Pin Output Voltage 2.498 2.5 2.503 V TA = 25°C Temperature Coefficient 1.5 4 ppm/°C C grade 2 8 ppm/°C B grade 4 10 ppm/°C A grade Output Noise (0.1 Hz to 10 Hz)3 7.5 µV p-p Noise Spectral Density3 245 nV/√Hz At 1 kHz 70 nV/√Hz At 10 kHz Output Voltage Drift vs. Time3 200 ppm Drift after 1000 hours at TA = 125°C Capacitive Load3 10 nF Recommended operation Load Current3, 6 4 mA Short-Circuit Current3 6.5 mA Short circuit to COM Power Supply Sensitivity3 2 12 µV/V Thermal Hysteresis3 285 ppm First temperature cycle 5 ppm Second temperature cycle Load Regulation3 0.1 0.2 mV/mA Measured at 0 mA and 1 mA loads Output Impedance 0.1 Ω REFOUT2 Pin Output Voltage 1.18 1.227 1.28 V TA = 25°C Output Impedance 72 kΩ

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AD5421 Data Sheet Rev. I | Page 6 of 36 Parameter1 Min Typ Max Unit Test Conditions/Comments REGOUT OUTPUT Voltage regulator output Output Voltage 1.8 12 V See Table 10 Output Voltage TC3 110 ppm/°C Output Voltage Accuracy −4 ±2 +4 % Externally Available Current3, 6 3.15 mA Assuming 4 mA is flowing in the loop and during HART communications Short-Circuit Current 23 mA Line Regulation3 500 µV/V Internal NMOS 10 µV/V External NMOS Load Regulation3 8 mV/mA Inductive Load 50 mH Stable operation Capacitive Load 2 10 µF Recommended operation ADC ACCURACY Die Temperature ±5 °C VLOOP Input ±1 % DVDD OUTPUT Can be overdriven up to 5.5 V Output Voltage 3.17 3.3 3.48 V Externally Available Current3, 6 3.15 mA Assuming 4 mA is flowing in the loop and during HART communications Short-Circuit Current 7.7 mA Load Regulation 45 mV/mA Measured at 0 mA and 3 mA loads DIGITAL INPUTS3 SCLK, SYNC, SDIN, LDAC Input High Voltage, VIH 0.7 × IODVDD V Input Low Voltage, VIL 0.25 × IODVDD V Hysteresis 0.21 V IODVDD = 1.8 V 0.63 V IODVDD = 3.3 V 1.46 V IODVDD = 5.5 V Input Current −0.015 +0.015 µA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS3 SDO Pin Output Low Voltage, VOL 0.4 V Output High Voltage, VOH IODVDD − 0.5 V High Impedance Leakage Current −0.01 +0.01 µA High Impedance Output Capacitance 5 pF FAULT Pin Output Low Voltage, VOL 0.4 V Output High Voltage, VOH IODVDD − 0.5 V FAULT THRESHOLDS ILOOP Under ILOOP − 0.01% FSR mA ILOOP Over ILOOP + 0.01% FSR mA Temp 140°C 133 °C Fault removed when temperature is ≤ 125°C Temp 100°C 90 °C Fault removed when temperature is ≤ 85°C VLOOP 6V 0.3 V Fault removed when VLOOP ≥ 0.4 V VLOOP 12V 0.6 V Fault removed when VLOOP ≥ 0.7 V

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Data Sheet AD5421 Rev. I | Page 7 of 36 Parameter1 Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS REGIN 5.5 52 V With respect to LOOP− pin IODVDD 1.71 5.5 V With respect to COM pin Quiescent Current 260 300 µA 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421. System level total error can be reduced using the offset and gain registers. 3 Guaranteed by design and characterization; not production tested. 4 The voltage between LOOP− and REGIN must be 5.5 V or greater. 5 The AD5421 is factory calibrated with an external 2.5 V reference connected to REFIN. 6 This is the current that the output is capable of sourcing. The load current originates from the loop and, therefore, contributes to the total current consumption figure.

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AD5421 Data Sheet Rev. I | Page 8 of 36 Loop voltage = 24 V; REFIN = REFOUT1 (2.5 V internal reference); RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1, 2 C Grade Unit Test Conditions/Comments Min Typ Max ACCURACY, INTERNAL RSET Total Unadjusted Error (TUE)3 −0.157 +0.157 % FSR −0.117 ±0.0172 +0.117 % FSR TA = 25°C Relative Accuracy (INL) −0.004 +0.004 % FSR −0.004 ±0.0015 +0.004 % FSR TA = 25°C Offset Error −0.04 +0.04 % FSR −0.025 ±0.0025 +0.025 % FSR TA = 25°C Offset Error TC 1 ppm FSR/°C Gain Error −0.128 +0.128 % FSR −0.093 ±0.0137 +0.093 % FSR TA = 25°C Gain Error TC 5 ppm FSR/°C Full-Scale Error −0.157 +0.157 % FSR −0.117 ±0.0172 +0.117 % FSR TA = 25°C Full-Scale Error TC 6 ppm FSR/°C ACCURACY, EXTERNAL RSET (24 kΩ) Assumes ideal resistor Total Unadjusted Error (TUE)3 −0.133 +0.133 % FSR −0.133 ±0.0252 +0.133 % FSR TA = 25°C Relative Accuracy (INL) −0.004 +0.004 % FSR −0.004 ±0.0015 +0.004 % FSR TA = 25°C Offset Error −0.029 +0.029 % FSR −0.029 ±0.0038 +0.029 % FSR TA = 25°C Offset Error TC 0.5 ppm FSR/°C Gain Error −0.11 +0.11 % FSR −0.106 ±0.0197 +0.106 % FSR TA = 25°C Gain Error TC 2 ppm FSR/°C Full-Scale Error −0.133 +0.133 % FSR −0.133 ±0.0252 +0.133 % FSR TA = 25°C Full-Scale Error TC 2 ppm FSR/°C 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Specifications guaranteed by design and characterization; not production tested. 3 Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421. System level total error can be reduced using the offset and gain registers.

Page 10

Data Sheet AD5421 Rev. I | Page 9 of 36 AC PERFORMANCE CHARACTERISTICS Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Loop Current Settling Time 50 µs To 0.1% FSR, CIN = open circuit Loop Current Slew Rate 400 µA/µs CIN = open circuit AC Loop Voltage Sensitivity 1.3 µA/V 1200 Hz to 2200 Hz, 5 V p-p, RL = 3 kΩ 1 Temperature range: −40°C to +105°C; typical at +25°C. TIMING CHARACTERISTICS Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications TMIN to TMAX. Table 4. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description t1 33 ns min SCLK cycle time t2 17 ns min SCLK high time t3 17 ns min SCLK low time t4 17 ns min SYNC falling edge to SCLK falling edge setup time t5 10 ns min SCLK falling edge to SYNC rising edge t6 25 µs min Minimum SYNC high time t7 5 ns min Data setup time t8 5 ns min Data hold time t9 25 µs min SYNC rising edge to LDAC falling edge t10 10 ns min LDAC pulse width low t11 70 ns max SCLK rising edge to SDO valid (CL SDO = 30 pF) t12 0 ns min SYNC falling edge to SCLK rising edge setup time t13 70 ns max SYNC rising edge to SDO tristate (CL SDO = 30 pF) 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 2 and Figure 3. Table 5. SPI Watchdog Timeout Periods Parameter1 Min Typ Max Unit T0 T1 T2 0 0 0 43 50 59 ms 0 0 1 87 100 117 ms 0 1 0 436 500 582 ms 0 1 1 873 1000 1163 ms 1 0 0 1746 2000 2326 ms 1 0 1 2619 3000 3489 ms 1 1 0 3493 4000 4652 ms 1 1 1 4366 5000 5814 ms 1 Specifications guaranteed by design and characterization; not production tested.

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