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AD5541CR

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AD5541CR

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Part Number AD5541CR
Manufacturer Analog Devices Inc.
Description IC DAC 16BIT SERIAL-IN 8-SOIC
Datasheet AD5541CR Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 2,216 piece(s)
Unit Price $ 35.3036 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 9 - Jul 14 (Choose Expedited Shipping)
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Part Number # AD5541CR (Data Acquisition - Digital to Analog Converters (DAC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD5541CR Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet AD5541CRDatasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
Number of Bits16
Number of D/A Converters1
Settling Time1µs (Typ)
Output TypeVoltage - Unbuffered
Differential OutputNo
Data InterfaceSPI, DSP
Reference TypeExternal
Voltage - Supply, Analog2.7 V ~ 5.5 V
Voltage - Supply, Digital2.7 V ~ 5.5 V
INL/DNL (LSB)±0.5, ±0.5
ArchitectureR-2R
Operating Temperature-40°C ~ 85°C
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC
Mounting Type-

AD5541CR Datasheet

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2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DACs Data Sheet AD5541/AD5542 Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1999–2012 Analog Devices, Inc. All rights reserved. FEATURES Full 16-bit performance 3 V and 5 V single-supply operation Low 0.625 mW power dissipation 1 µs settling time Unbuffered voltage output capable of driving 60 kΩ loads directly SPI-/QSPI-/MICROWIRE-compatible interface standards Power-on reset clears DAC output to 0 V (unipolar mode) 5 kV HBM ESD classification Low glitch: 1.1 nV-sec APPLICATIONS Digital gain and offset adjustment Automatic test equipment Data acquisition systems Industrial process control GENERAL DESCRIPTION The AD5541/AD5542 are single, 16-bit, serial input, voltage output digital-to-analog converters (DACs) that operate from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to VREF. The DAC output range extends from 0 V to VREF and is guaranteed monotonic, providing 1 LSB INL accuracy at 16 bits without adjustment over the full specified temperature range of −40°C to +85°C. Offering unbuffered outputs, the AD5541/AD5542 achieve a 1 µs settling time with low power consumption and low offset errors. Providing a low noise performance of 11.8 nV/√Hz and low glitch, the AD5541/AD5542 is suitable for deployment across multiple end systems. The AD5542 can be operated in bipolar mode, which generates a ±VREF output swing. The AD5542 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. The AD5541/AD5542 utilize a versatile 3-wire interface that is compatible with SPI, QSPI™, MICROWIRE™ and DSP interface standards. The AD5541/AD5542 are available in 8-lead and 14-lead SOIC packages. FUNCTIONAL BLOCK DIAGRAMS 6 1 2 8 7 16-BIT DAC 16-BIT DAC LATCH SERIAL INPUT REGISITER VDD DGND DIN REF CS SCLK 3 4 5 VOUT AGND AD5541 CONTROL LOGIC 07 55 7- 00 1 Figure 1. AD5541 11 2 3 14 12 16-BIT DAC 16-BIT DAC LATCH SERIAL INPUT REGISITER VDD DGND LDAC REFF CS DIN 6 REFS 5 7 10 VOUT 13 INV 1 RFB AGNDF 4 AGNDS AD5542 CONTROL LOGIC 07 55 7- 00 2 8SCLK RFB RINV Figure 2. AD5542 Table 1. Part No. Description AD5541A/AD5542A Single, 16-bit unbuffered nanoDAC™, ±1 LSB INL, LFCSP AD5024/AD5044/AD5064 Quad 12-/14-/16-bit nanoDAC, ±1 LSB INL, TSSOP AD5062 Single, 16-bit nanoDAC, ±1 LSB INL, SOT-23 AD5063 Single, 16-bit nanoDAC, ±1 LSB INL, SOT-23 PRODUCT HIGHLIGHTS 1. Single-Supply Operation. The AD5541 and AD5542 are fully specified and guaranteed for a single 2.7 V to 5.5 V supply. 2. Low Power Consumption. These parts consume typically 0.625 mW with a 5 V supply and 0.375 mV at 3 V. 3. 3-Wire Serial Interface. 4. Unbuffered Output Capable of Driving 60 kΩ Loads. This reduces power consumption because there is no internal buffer to drive. 5. Power-On Reset Circuitry.

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AD5541/AD5542 Data Sheet Rev. F | Page 2 of 20 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Terminology .................................................................................... 10 Theory of Operation ...................................................................... 11 Digital-to-Analog Section ......................................................... 11 Serial Interface ............................................................................ 11 Unipolar Output Operation ...................................................... 11 Bipolar Output Operation ......................................................... 12 Output Amplifier Selection ....................................................... 12 Force Sense Amplifier Selection ............................................... 12 Reference and Ground ............................................................... 12 Power-On Reset .......................................................................... 13 Power Supply and Reference Bypassing .................................. 13 Microprocessor Interfacing ........................................................... 14 AD5541/AD5542 to ADSP-21xx Interface ............................. 14 AD5541/AD5542 to 68HC11/68L11 Interface....................... 14 AD5541/AD5542 to MICROWIRE Interface ........................ 14 AD5541/AD5542 to 80C51/80L51 Interface .......................... 14 Applications Information .............................................................. 15 Optocoupler Interface ................................................................ 15 Decoding Multiple AD5541/AD5542s .................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 17 REVISION HISTORY 3/12—Rev. E to Rev. F Change to Figure 19 ......................................................................... 9 Changes to Ordering Guide .......................................................... 17 3/11—Rev. D to Rev. E Changed +105°C to +85°C, General Description Section .......... 1 2/11—Rev. C to Rev. D Changes to Features Section, General Description Section, Product Highlights Section ............................................................. 1 Added Table 1; Renumbered Sequentially .................................... 1 Added Output Noise Spectral Density Parameter and Output Noise Parameter, Table 2.................................................................. 3 Changes to Ordering Guide .......................................................... 17 4/10—Rev. B to Rev. C Changes to General Description Section ...................................... 1 Changes to Features List .................................................................. 1 Changes to Product Highlights ....................................................... 1 Changes to Table 1 ............................................................................. 3 Changes to Table 3 ............................................................................. 5 Changes to Figure 16, Figure 17, and Figure 19 ....................... 8, 9 Changes to Theory of Operations Section .................................. 11 Changes to Microprocessor Interfacing Section ........................ 14 Changes to Outline Dimensions .................................................. 16 Changes to Ordering Guide .......................................................... 17 8/08—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Timing Characteristics Section ................................... 4 Changes to Table 3 ............................................................................. 5 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 17 10/99—Rev. 0 to Rev. A

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Data Sheet AD5541/AD5542 Rev. F | Page 3 of 20 SPECIFICATIONS VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 Min Typ Max Unit Test Conditions STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy (INL) ±0.5 ±1.0 LSB L, C grades ±0.5 ±2.0 LSB B, J grades ±0.5 ±4.0 LSB A grade Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic ±1.5 LSB J grade Gain Error +0.5 ±2 LSB TA = 25°C ±3 LSB Gain Error Temperature Coefficient ±0.1 ppm/°C Unipolar Zero Code Error ±0.3 ±0.7 LSB TA = 25°C ±1.5 LSB Unipolar Zero Code Temperature Coefficient ±0.05 ppm/°C AD5542 Bipolar Resistor Matching 1.000 Ω/Ω RFB/RINV, typically RFB = RINV = 28 kΩ ±0.0015 ±0.0076 % Ratio error Bipolar Zero Offset Error ±1 ±5 LSB TA = 25°C ±6 LSB Bipolar Zero Temperature Coefficient ±0.2 ppm/°C Bipolar Zero Code Offset Error ±1 ±5 LSB TA = 25°C ±6 LSB Bipolar Gain Error +1 ±5 LSB TA = 25°C ±6 LSB Bipolar Gain Temperature Coefficient ±0.1 ppm/°C OUTPUT CHARACTERISTICS Output Voltage Range 0 VREF − 1 LSB V Unipolar operation −VREF VREF − 1 LSB V AD5542 bipolar operation Output Voltage Settling Time 1 μs To 1/2 LSB of FS, CL = 10 pF Slew Rate 17 V/μs CL = 10 pF, measured from 0% to 63% Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around the major carry Digital Feedthrough 0.2 nV-sec All 1s loaded to DAC, VREF = 2.5 V DAC Output Impedance 6.25 kΩ Tolerance typically 20% Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x8400, frequency = 1 kHz Output Noise 0.134 µV p-p 0.1 Hz to 10 Hz Power Supply Rejection Ratio ±1.0 LSB ΔVDD ± 10% DAC REFERENCE INPUT Reference Input Range 2.0 VDD V Reference Input Resistance2 9 kΩ Unipolar operation 7.5 kΩ AD5542, bipolar operation LOGIC INPUTS Input Current ±1 μA Input Low Voltage, VINL 0.8 V Input High Voltage, VINH 2.4 V Input Capacitance3 10 pF Hysteresis Voltage3 0.15 V REFERENCE 3 Reference −3 dB Bandwidth 2.2 MHz All 1s loaded Reference Feedthrough 1 mV p-p All 0s loaded, VREF = 1 V p-p at 100 kHz Signal-to-Noise Ratio 92 dB Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0xFFFF

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AD5541/AD5542 Data Sheet Rev. F | Page 4 of 20 Parameter1 Min Typ Max Unit Test Conditions POWER REQUIREMENTS Digital inputs at rails VDD 2.7 5.5 V IDD 125 150 μA Power Dissipation 0.625 0.825 mW 1 Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C. 2 Reference input resistance is code-dependent, minimum at 0x8555. 3 Guaranteed by design, not subject to production test. TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V ±10%, VREF = 2.5 V, VINH = 3 V and 90% of VDD, VINL = 0 V and 10% of VDD, AGND = DGND = 0 V; −40°C < TA < +85°C, unless otherwise noted. Table 3. Parameter1, 2 Limit Unit Description fSCLK 25 MHz max SCLK cycle frequency t1 40 ns min SCLK cycle time t2 20 ns min SCLK high time t3 20 ns min SCLK low time t4 10 ns min CS low to SCLK high setup t5 15 ns min CS high to SCLK high setup t6 30 ns min SCLK high to CS low hold time t7 20 ns min SCLK high to CS high hold time t8 15 ns min Data setup time t9 4 ns min Data hold time (VINH = 90% of VDD, VINL = 10% of VDD) t9 7.5 ns min Data hold time (VINH = 3V, VINL = 0 V) t10 30 ns min LDAC pulse width t11 30 ns min CS high to LDAC low setup t12 30 ns min CS high time between active periods 1 Guaranteed by design and characterization. Not production tested 2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2. SCLK CS DIN DB15 LDAC* t6 t4 t12 t8 t5 t2 t3 t1 t7 t5 t11 t10 *AD5542 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED. 07 55 7- 00 3 Figure 3. Timing Diagram

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Data Sheet AD5541/AD5542 Rev. F | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to AGND −0.3 V to +6 V Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V VOUT to AGND −0.3 V to VDD + 0.3 V AGND, AGNDF, AGNDS to DGND −0.3 V to +0.3 V Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Industrial (A, B, C Versions) −40°C to +85°C Commercial (J, L Versions) 0°C to 70°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (TJ max) 150°C Package Power Dissipation (TJ max – TA)/θJA Thermal Impedance, θJA SOIC (R-8) 149.5°C/W SOIC (R-14) 104.5°C/W Lead Temperature, Soldering Peak Temperature1 260°C ESD2 5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 As per JEDEC Standard 20. 2 HBM Classification.

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AD5541/AD5542 Data Sheet Rev. F | Page 6 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT 1 AGND 2 REF 3 CS 4 VDD8 DGND7 DIN6 SCLK5 AD5541 TOP VIEW (Not to Scale) 07 55 7- 00 4 Figure 4. AD5541 Pin Configuration Table 5. AD5541 Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT Analog Output Voltage from the DAC. 2 AGND Ground Reference Point for Analog Circuitry. 3 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD. 4 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 5 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 6 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. 7 DGND Digital Ground. Ground reference for digital circuitry. 8 VDD Analog Supply Voltage, 5 V ± 10%. 07 55 7- 00 5 RFB 1 VOUT 2 AGNDF 3 AGNDS 4 VDD14 INV13 DGND12 LDAC11 REFS 5 DIN10 REFF 6 NC9 CS 7 SCLK8 NC = NO CONNECT AD5542 TOP VIEW (Not to Scale) Figure 5. AD5542 Pin Configuration Table 6. AD5542 Pin Function Descriptions Pin No. Mnemonic Description 1 RFB Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. 2 VOUT Analog Output Voltage from the DAC. 3 AGNDF Ground Reference Point for Analog Circuitry (Force). 4 AGNDS Ground Reference Point for Analog Circuitry (Sense). 5 REFS Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD. 6 REFF Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD. 7 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 8 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 9 NC No Connect. 10 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. 11 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. 12 DGND Digital Ground. Ground reference for digital circuitry. 13 INV Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in bipolar mode. 14 VDD Analog Supply Voltage, 5 V ± 10%.

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Data Sheet AD5541/AD5542 Rev. F | Page 7 of 20 TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.25 0 –0.25 –0.50 –0.75 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE IN TE G R A L N O N LI N EA R IT Y (L SB ) 07 55 7- 00 6 VDD = 5V VREF = 2.5V Figure 6. Integral Nonlinearity vs. Code 0.25 0 –0.25 –0.50 –0.75 –1.00 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) IN TE G R A L N O N LI N EA R IT Y (L SB ) 07 55 7- 00 7 VDD = 5V VREF = 2.5V Figure 7. Integral Nonlinearity vs. Temperature 0.50 0.25 0 –0.25 –0.50 –0.75 2 3 4 5 6 7 SUPPLY VOLTAGE (V) LI N EA R IT Y ER R O R (L SB ) 07 55 7- 00 8 VREF = 2.5V TA = 25°C DNL INL Figure 8. Linearity Error vs. Supply Voltage 0.50 0.25 0 –0.25 –0.50 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE D IF FE R EN TI A L N O N LI N EA R IT Y (L SB ) 07 55 7- 00 9 VDD = 5V VREF = 2.5V Figure 9. Differential Nonlinearity vs. Code 0.75 0.50 0.25 0 –0.25 –0.50 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) D IF FE R EN TI A L N O N LI N EA R IT Y (L SB ) 07 55 7- 01 0 VDD = 5V VREF = 2.5V Figure 10. Differential Nonlinearity vs. Temperature 0.75 0.50 0.25 0 –0.25 –0.50 0 1 2 3 4 5 6 REFERENCE VOLTAGE (V) LI N EA R IT Y ER R O R (L SB ) 07 55 7- 01 1 VDD = 5V TA = 25°C DNL INL Figure 11. Linearity Error vs. Reference Voltage

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AD5541/AD5542 Data Sheet Rev. F | Page 8 of 20 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –40 25 85 TEMPERATURE (°C) G A IN E R R O R ( L S B ) VDD = 5V VREF = 2.5V TA = 25°C 08 89 8- 01 2 Figure 12. Gain Error vs. Temperature 132 116 118 120 122 124 126 128 130 –40 25 85 TEMPERATURE (°C) S U P P L Y C U R R E N T ( µ A ) VDD = 5V VREF = 2.5V TA = 25°C 08 89 8- 01 3 Figure 13. Supply Current vs. Temperature 200 0 20 40 60 80 100 120 140 160 180 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DIGITAL INPUT VOLTAGE (V) S U P P L Y C U R R E N T ( µ V ) 08 89 8- 01 4 Figure 14. Supply Current vs. Digital Input Voltage 0.15 –0.15 –0.10 –0.05 0 0.05 0.10 –40 25 85 TEMPERATURE (°C) Z E R O -C O D E E R R O R ( L S B ) VDD = 5V VREF = 2.5V TA = 25°C 08 89 8- 01 5 Figure 15. Zero-Code Error vs. Temperature 08 89 8- 01 60 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 S U P P LY C U R R E N T ( µ A ) VOLTAGE (V) REFERENCE VOLTAGE VDD = 5V SUPPLY VOLTAGE VREF = 2.5V TA = 25°C Figure 16. Supply Current vs. Reference Voltage or Supply Voltage 200 150 100 50 0 0 70,00060,00050,00040,00030,00020,00010,000 CODE (Decimal) R E F E R E N C E C U R R E N T ( µ A ) VDD = 5V VREF = 2.5V TA = 25°C 08 89 8- 01 7 Figure 17. Reference Current vs. Code

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Data Sheet AD5541/AD5542 Rev. F | Page 9 of 20 2µs/DIV VREF = 2.5V VDD = 5V TA = 25°C DIN (5V/DIV) VOUT (50mV/DIV) 100 10 08 89 8- 01 8 Figure 18. Digital Feedthrough VO LT A G E (V ) 1.236 1.234 1.232 1.230 1.228 1.226 1.224 –0.5 0 0.5 1.0 1.5 2.0 5 0 –5 –10 –15 –20 –25 –30 TIME (µs) VOUT CS 07 55 7- 03 2 Figure 19. Digital-to-Analog Glitch Impulse 2µs/DIV VREF = 2.5VVDD = 5V TA = 25°C 200pF 10pF 50pF 100pF 100 10 CS (5V/DIV) VOUT (0.5V/DIV) 08 89 8- 02 0 Figure 20. Large Signal Settling Time 07 55 7- 02 1 • • • •• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0.5µs/DIV VREF = 2.5V VDD = 5V TA = 25°C 100 90 10 0% VOUT (1V/DIV) VOUT (50mV/DIV) GAIN = –216 1LSB = 8.2mV Figure 21. Small Signal Settling Time

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