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AD6642BBCZ

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AD6642BBCZ

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Part Number AD6642BBCZ
Manufacturer Analog Devices Inc.
Description IC IF RCVR 11BIT 200MSPS 144BGA
Datasheet AD6642BBCZ Datasheet
Package 144-LFBGA, CSPBGA
In Stock 3,178 piece(s)
Unit Price $ 129.3700 *
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Estimated Delivery Time Nov 2 - Nov 7 (Choose Expedited Shipping)
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Part Number # AD6642BBCZ (RF Misc ICs and Modules) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD6642BBCZ Specifications

ManufacturerAnalog Devices Inc.
CategoryRF/IF and RFID - RF Misc ICs and Modules
Datasheet AD6642BBCZDatasheet
Package144-LFBGA, CSPBGA
Series-
FunctionIF Receiver
Frequency-
RF TypeCDMA, LTE, W-CDMA, WiMAX
Secondary AttributesSample Rates to 200MSPS
Package / Case144-LFBGA, CSPBGA
Supplier Device Package144-CSBGA (10x10)

AD6642BBCZ Datasheet

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Dual IF Receiver AD6642 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved. FEATURES 11-bit, 200 MSPS output data rate per channel Integrated noise shaping requantizer (NSR) Performance with NSR enabled SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS Performance with NSR disabled SNR: 66.5 dBFS to 70 MHz @ 185 MSPS SFDR: 83 dBc to 70 MHz @ 185 MSPS Low power: 0.62 W @ 185 MSPS 1.8 V analog supply operation 1.8 V LVDS (ANSI-644 levels) output 1-to-8 integer clock divider Internal ADC voltage reference 1.75 V p-p analog input range (programmable to 2.0 V p-p) Differential analog inputs with 800 MHz bandwidth 95 dB channel isolation/crosstalk Serial port control User-configurable built-in self-test (BIST) capability Energy-saving power-down modes APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios FUNCTIONAL BLOCK DIAGRAM VIN+A D0±AB D10±AB VIN–A PIPELINE ADC NOISE SHAPING REQUANTIZER VIN+B VIN–B PIPELINE ADC SERIAL PORT REFERENCE 14 11 NOISE SHAPING REQUANTIZER AD6642 D A TA M U LT IP L E X E R A N D LV D S D R IV E R S 14 11 CLOCK DIVIDER VCMA VCMB DC0±AB SCLK SDIO CSB CLK+ AVDD AGND DRVDD DRGND CLK– MODE SYNC PDWN 08 56 3 -0 0 1 Figure 1. PRODUCT HIGHLIGHTS 1. Two ADCs are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package. 2. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS. 3. LVDS digital output interface configured for low cost FPGA families. 4. 120 mW per ADC core power consumption. 5. Operation from a single 1.8 V supply. 6. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. 7. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.

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AD6642 Rev. A | Page 2 of 32 TABLE OF CONTENTS Features .............................................................................................. 1  Applications....................................................................................... 1  Functional Block Diagram .............................................................. 1  Product Highlights ........................................................................... 1  Revision History ............................................................................... 2  General Description ......................................................................... 3  Specifications..................................................................................... 4  DC Specifications ......................................................................... 4  AC Specifications.......................................................................... 5  Digital Specifications ................................................................... 6  Switching Specifications .............................................................. 7  Timing Specifications .................................................................. 8  Absolute Maximum Ratings............................................................ 9  Thermal Characteristics .............................................................. 9  ESD Caution.................................................................................. 9  Pin Configuration and Function Descriptions........................... 10  Typical Performance Characteristics ........................................... 12  Equivalent Circuits ......................................................................... 15  Theory of Operation ...................................................................... 16  ADC Architecture ...................................................................... 16  Analog Input Considerations.................................................... 16  Clock Input Considerations ...................................................... 18  Power Dissipation and Standby Mode .................................... 20  Channel/Chip Synchronization................................................ 20  Digital Outputs ........................................................................... 21  Timing ......................................................................................... 21  Noise Shaping Requantizer (NSR) ............................................... 22  22% BW Mode (>40 MHz @ 184.32 MSPS)........................... 22  33% BW Mode (>60 MHz @ 184.32 MSPS)........................... 22  MODE Pin................................................................................... 23  Built-In Self-Test (BIST) and Output Test .................................. 24  Built-In Self-Test (BIST)............................................................ 24  Output Test Modes..................................................................... 24  Serial Port Interface (SPI).............................................................. 25  Configuration Using the SPI..................................................... 25  Hardware Interface..................................................................... 25  Memory Map .................................................................................. 26  Reading the Memory Map Register Table............................... 26  Memory Map Register Table..................................................... 27  Memory Map Register Descriptions........................................ 29  Applications Information .............................................................. 30  Design Guidelines ...................................................................... 30  Outline Dimensions ....................................................................... 31  Ordering Guide .......................................................................... 31  REVISION HISTORY 7/10—Rev. 0 to Rev. A Changes to ADC Architecture Section........................................ 16 Changes to Figure 34 and Figure 35............................................. 18 Changes to Timing Section and Data Clock Output (DCO) Section.............................................................................................. 21 Changes to 22% BW Mode (>40 MHz @ 184.32 MSPS) Section and 33% BW Mode (>60 MHz @ 184.32 MSPS) Section ......... 22 Changes to Design Guidelines Section........................................ 30 10/09—Revision 0: Initial Version

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AD6642 Rev. A | Page 3 of 32 GENERAL DESCRIPTION The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi- antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6642 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6642 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode. With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6642 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6642 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are desired. After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels. The AD6642 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces compo- nent cost and complexity compared with traditional analog techniques or less integrated digital methods. Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board-level system testing. The AD6642 is available in a Pb-free/RoHS compliant, 144-ball, 10 mm × 10 mm chip scale package ball grid array (CSP_BGA) and is specified over the industrial temperature range of −40°C to +85°C.

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AD6642 Rev. A | Page 4 of 32 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 1. Parameter Temperature Min Typ Max Unit RESOLUTION Full 11 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full −4.5 2 7.4 mV Gain Error Full ±3 ±7 % FSR Differential Nonlinearity (DNL)1 Full ±0.1 ±0.5 LSB Integral Nonlinearity (INL)1 Full ±0.2 ±0.5 LSB MATCHING CHARACTERISTIC Offset Error Full −2.4 2.5 8.3 mV Gain Error Full ±1 ±3 % FSR TEMPERATURE DRIFT Offset Error Full 2 ppm/°C Gain Error Full 40 ppm/°C ANALOG INPUT Input Range Full 1.4 1.75 2.0 V p-p Input Common-Mode Voltage Full 0.9 V Input Resistance (Differential) Full 20 kΩ Input Capacitance2 Full 5 pF POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current IAVDD1 Full 265 291 mA IDRVDD1 (1.8 V LVDS) Full 79 89 mA POWER CONSUMPTION Sine Wave Input1 Full 619 684 mW Standby Power3 Full 83 mW Power-Down Power Full 4.5 18 mW 1 Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).

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AD6642 Rev. A | Page 5 of 32 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 2. Parameter1 Temperature Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR)—NSR DISABLED fIN = 30 MHz 25°C 66.5 dBFS fIN = 70 MHz 25°C 66.5 dBFS fIN = 170 MHz Full 65.7 66.1 dBFS fIN = 250 MHz 25°C 65.5 dBFS SIGNAL-TO-NOISE-RATIO (SNR)—NSR ENABLED 22% BW Mode fIN = 70 MHz 25°C 75.5 dBFS fIN = 170 MHz Full 72.8 74.4 dBFS fIN = 230 MHz 25°C 72.8 dBFS 33% BW Mode fIN = 70 MHz 25°C 73.7 dBFS fIN = 170 MHz Full 71.0 72.6 dBFS fIN = 230 MHz 25°C 71.0 dBFS SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 30 MHz 25°C 65.5 dBFS fIN = 70 MHz 25°C 66.3 dBFS fIN = 170 MHz Full 64.1 65.6 dBFS fIN = 250 MHz 25°C 64.3 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz 25°C 10.6 Bits fIN = 70 MHz 25°C 10.7 Bits fIN = 170 MHz Full 10.3 10.6 Bits fIN = 250 MHz 25°C 10.3 Bits WORST SECOND OR THIRD HARMONIC fIN = 30 MHz 25°C −90 dBc fIN = 70 MHz 25°C −83 dBc fIN = 170 MHz Full −72 −78 dBc fIN = 250 MHz 25°C −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz 25°C 90 dBc fIN = 70 MHz 25°C 83 dBc fIN = 170 MHz Full 72 78 dBc fIN = 250 MHz 25°C 80 dBc WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH) fIN = 30 MHz 25°C −100 dBc fIN = 70 MHz 25°C −96 dBc fIN = 170 MHz Full −82 −90 dBc fIN = 250 MHz 25°C −95 dBc TWO-TONE SFDR (−7 dBFS) fIN1 = 169 MHz, fIN2 = 172 MHz 25°C 82 dBc CROSSTALK2 Full 95 dB ANALOG INPUT BANDWIDTH 25°C 800 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 155 MHz with −1 dBFS on one channel and no input on the alternate channel.

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AD6642 Rev. A | Page 6 of 32 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full AGND − 0.3 AVDD + 0.2 V High Level Input Voltage Full 1.2 2.0 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Resistance Full 12 16 20 kΩ Input Capacitance Full 1 pF LOGIC INPUT (CSB)1 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT (SCLK)2 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT/OUTPUT (SDIO)2 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF LOGIC INPUT (MODE)1 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA

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AD6642 Rev. A | Page 7 of 32 Parameter Temperature Min Typ Max Unit Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT (PDWN)2 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS (LVDS) Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V 1 Pull up. 2 Pull down. SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 4. Parameter Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 MHz Conversion Rate1 Full 40 185 200 MSPS CLK Pulse Width High (tCH) Full 2.7 ns Aperture Delay (tA) Full 1.3 ns Aperture Uncertainty (Jitter, tJ) Full 0.13 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3.0 4.35 5.7 ns DCO Propagation Delay (tDCO) Full 3.2 4.55 5.9 ns DCO to Data Skew (tSKEW) Full −0.4 −0.2 0 ns Pipeline Delay (Latency) Full 9 Cycles With NSR Enabled Full 12 Cycles Wake-Up Time2 Full 1.2 μs OUT-OF-RANGE RECOVERY TIME Full 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Wake-up time is dependent on the value of the decoupling capacitors.

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AD6642 Rev. A | Page 8 of 32 TIMING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 5. Parameter Description Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.24 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns Timing Diagrams N – 1 N + 1 N + 2 N + 3 N + 4 N + 5 N CLK+ CLK– DCO+ DCO– D10+AB (MSB) D10–AB (MSB) D0+AB (LSB) D0–AB (LSB) VIN tA tCH tDCO tCL tPD tSKEW 1/fS D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B D0A D0B D10A D10B D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B 08 56 3- 0 02 Figure 2. Data Output Timing SYNC CLK+ tHSYNCtSSYNC 08 56 3- 00 3 Figure 3. SYNC Input Timing Requirements

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AD6642 Rev. A | Page 9 of 32 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0 V VIN+x, VIN−x to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to AVDD + 0.2 V VCMx to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V SCLK to AGND −0.3 V to DRVDD + 0.2 V SDIO to AGND −0.3 V to DRVDD + 0.2 V PDWN to AGND −0.3 V to DRVDD + 0.2 V MODE to AGND −0.3 V to DRVDD + 0.2 V Digital Outputs to AGND −0.3 V to DRVDD + 0.2 V DCO+AB, DCO−AB to AGND −0.3 V to DRVDD + 0.2 V Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature Under Bias 150°C Storage Temperature Range (Ambient) −65°C to +150°C The values in Table 7 are per JEDEC JESD51-7 plus JEDEC JESD25-5 for a 2S2P test board. Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addi- tion, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces θJA. Table 7. Package Type Airflow Velocity θJA1 θJC2 θJB3 Unit 0 m/s 26.9 8.9 6.6 1 m/s 24.2 144-Ball CSP_BGA, 10 mm × 10 mm (BC-144-1) 2.5 m/s 23.0 °C/W 1 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 2 Per MIL-STD 883, Method 1012.1. 3 Per JEDEC JESD51-8 (still air). The values in Table 8 are from simulations. The PCB is a JEDEC multilayer board. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine whether they are similar to those assumed in these calculations. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8. Package Type Airflow Velocity ΨJB ΨJT Unit 0 m/s 14.4 0.23 1 m/s 14.0 0.50 144-Ball CSP_BGA, 10 mm × 10 mm (BC-144-1) 2.5 m/s 13.9 0.53 °C/W ESD CAUTION

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August 18, 2020

Thousands of in stock parts with low cost shipping and standard quality.

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August 16, 2020

Very much appreciate the thoughtful system to hold multiple orders, including back ordered items, can be shipped at once rather than incremental shipments.

Kyl*****Kakar

August 14, 2020

No complaints. Works perfectly every single one of them! great quality! No bent pins either!

Bry*****Kota

August 6, 2020

The specs range is wide for a selection and the customer service is great.

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