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AD7478ARTZ-500RL7

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AD7478ARTZ-500RL7

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Part Number AD7478ARTZ-500RL7
Manufacturer Analog Devices Inc.
Description IC ADC 8BIT 1MSPS LP SOT23-6
Datasheet AD7478ARTZ-500RL7 Datasheet
Package SOT-23-6
In Stock 718 piece(s)
Unit Price $ 1.8094 *
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 9 - Aug 14 (Choose Expedited Shipping)
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Part Number # AD7478ARTZ-500RL7 (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7478ARTZ-500RL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7478ARTZ-500RL7Datasheet
PackageSOT-23-6
Series-
Number of Bits8
Sampling Rate (Per Second)1M
Number of Inputs1
Input TypeSingle Ended
Data InterfaceSPI, DSP
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeSupply
Voltage - Supply, Analog2.7 V ~ 5.25 V
Voltage - Supply, Digital2.7 V ~ 5.25 V
Features-
Operating Temperature-40°C ~ 85°C
Package / CaseSOT-23-6
Supplier Device PackageSOT-23-6
Mounting Type-

AD7478ARTZ-500RL7 Datasheet

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1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 AD7476/AD7477/AD7478 Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved. FEATURES Fast throughput rate: 1 MSPS Specified for VDD of 2.35 V to 5.25 V Low power 3.6 mW at 1 MSPS with 3 V supplies 15 mW at 1 MSPS with 5 V supplies Wide input bandwidth 70 dB SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Standby mode: 1 μA maximum 6-lead SOT-23 package APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors FUNCTIONAL BLOCK DIAGRAM 01 02 4 -0 0 1 CONTROL LOGIC 12-/10-/8-BIT SUCCESSIVE- APPROXIMATION ADC VIN SCLK SDATA CS VDD GND AD7476/AD7477/AD7478 Figure 1. GENERAL DESCRIPTION The AD7476/AD7477/AD74781 are, respectively, 12-bit, 10-bit, and 8-bit, high speed, low power, successive approximation ADCs. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. Each part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 6 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is initiated at this point. There are no pipeline delays associated with these parts. The AD7476/AD7477/AD7478 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the parts is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus, the analog input range for the parts are 0 V to VDD. The conversion rate is determined by the SCLK. 1 Protected by U.S. Patent No. 6,681,332. PRODUCT HIGHLIGHTS 1. First 12-/10-/8-Bit ADCs in SOT-23 Packages. 2. High Throughput with Low Power Consumption. 3. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced while not converting. The parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. Current consumption is 1 μA maximum when in shutdown mode. 4. Reference Derived from the Power Supply. 5. No Pipeline Delay. The parts feature a standard successive- approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.

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AD7476/AD7477/AD7478 Rev. F | Page 2 of 24 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Product Highlights ........................................................................... 1  Revision History ............................................................................... 2  Specifications ..................................................................................... 3  AD7476 Specifications ................................................................. 3  AD7477 Specifications ................................................................. 5  AD7478 Specifications ................................................................. 7  Timing Specifications .................................................................. 8  Absolute Maximum Ratings ............................................................ 9  ESD Caution .................................................................................. 9  Pin Configuration and Function Descriptions ........................... 10  Typical Performance Characteristics ........................................... 11  Terminology .................................................................................... 12  Theory of Operation ...................................................................... 13  Circuit Information .................................................................... 13  Converter Operation .................................................................. 13  ADC Transfer Function ............................................................. 13  Typical Connection Diagram ................................................... 14  Modes of Operation ................................................................... 15  Power vs. Throughput Rate ....................................................... 17  Serial Interface ............................................................................ 18  Microprocessor Interfacing ....................................................... 19  Outline Dimensions ....................................................................... 21  Ordering Guide .......................................................................... 22  REVISION HISTORY 1/09—Rev. E to Rev. F Changes to Features .......................................................................... 1 Changes to Ordering Guide .......................................................... 22 4/06—Rev. D to Rev. E Updated Format .................................................................. Universal Changes to Table 1 Endnotes .......................................................... 3 Changes to Table 2 Endnotes .......................................................... 5 Changes to Table 3 Endnotes .......................................................... 7 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 3/04—Rev. C to Rev. D Added U.S. Patent Number .............................................................. 1 Changes to Specifications ................................................................. 2 Changes to Absolute Maximum Ratings ........................................ 6 Changes to AD7476/AD7477/AD7478 to ADSP-21xx Interface section .............................................................................. 16 2/03—Rev. B to Rev. C Changes to General Description ..................................................... 1 Changes to Specifications ................................................................. 2 Changes to Absolute Maximum Ratings ........................................ 6 Changes to Ordering Guide ............................................................. 6 Changes to Typical Connection Diagram section ..................... 10 Changes to Figure 8 caption .......................................................... 11 Changes to Figure 19 ...................................................................... 16 Changes to Figure 20 ...................................................................... 17 Updated Outline Dimensions ....................................................... 18

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AD7476/AD7477/AD7478 Rev. F | Page 3 of 24 SPECIFICATIONS AD7476 SPECIFICATIONS A version: VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, unless otherwise noted; S and B versions: VDD = 2.35 V to 5.25 V, fSCLK = 12 MHz, fSAMPLE = 600 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter A Version1,2 B Version1,2 S Version1,2 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 100 kHz sine wave Signal-to-(Noise + Distortion) (SINAD)3 69 70 69 dB min B version, VDD = 2.4 V to 5.25 V 70 70 dB min TA = 25°C 71.5 dB typ Signal-to-Noise Ratio (SNR)3 70 71 70 dB min B version, VDD = 2.4 V to 5.25 V 72.5 dB typ Total Harmonic Distortion (THD)3 −80 −78 −78 dB typ Peak Harmonic or Spurious Noise (SFDR)3 −82 −80 −80 dB typ Intermodulation Distortion (IMD)3 Second-Order Terms −78 −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Third-Order Terms −78 −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Aperture Delay 10 10 10 ns typ Aperture Jitter 30 30 30 ps typ Full Power Bandwidth 6.5 6.5 6.5 MHz typ @ 3 dB DC ACCURACY S, B versions, VDD = (2.35 V to 3.6 V)4; A version, VDD = (2.7 V to 3.6 V) Resolution 12 12 12 Bits Integral Nonlinearity3 ±1.5 ±1.5 LSB max ±1 ±0.6 ±0.6 LSB typ Differential Nonlinearity3 −0.9/+1.5 −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits ±0.75 ±0.75 ±0.75 LSB typ Offset Error3 ±1.5 ±2 LSB max ±0.5 LSB typ Gain Error3 ±1.5 ±2 LSB max ±0.5 LSB typ ANALOG INPUT Input Voltage Ranges 0 to VDD 0 to VDD 0 to VDD V DC Leakage Current ±1 ±1 ±1 μA max Input Capacitance 30 30 30 pF typ LOGIC INPUT Input High Voltage, VINH 2.4 2.4 2.4 V min 1.8 1.8 1.8 V min VDD = 2.35 V Input Low Voltage, VINL 0.4 0.4 0.4 V max VDD = 3 V 0.8 0.8 0.8 V max VDD = 5 V Input Current, IIN, SCLK Pin ±1 ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin ±1 ±1 ±1 μA typ Input Capacitance, CIN5 10 10 10 pF max LOGIC OUTPUT Output High Voltage, VOH VDD − 0.2 VDD − 0.2 VDD − 0.2 V min ISOURCE = 200 μA; VDD = 2.35 V to 5.25 V Output Low Voltage, VOL 0.4 0.4 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±10 ±10 ±10 μA max Floating-State Output Capacitance5 10 10 10 pF max Output Coding Straight (Natural) Binary

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AD7476/AD7477/AD7478 Rev. F | Page 4 of 24 Parameter A Version1,2 B Version1,2 S Version1,2 Unit Test Conditions/Comments CONVERSION RATE Conversion Time 0.8 1.33 1.33 μs max 16 SCLK cycles Track-and-Hold Acquisition Time 500 500 500 ns max Full-scale step input 350 400 400 ns max Sine wave input ≤ 100 kHz Throughput Rate 1000 600 600 kSPS max See Serial Interface section POWER REQUIREMENTS VDD 2.35/5.25 2.35/5.25 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 2 2 2 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off 1 1 1 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 3.5 3 3 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = fSAMPLEMAX6 1.6 1.4 1.4 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = fSAMPLEMAX6 Full Power-Down Mode 1 1 1 μA max SCLK off 80 80 80 μA max SCLK on Power Dissipation7 Normal Mode (Operational) 17.5 15 15 mW max VDD = 5 V, fSAMPLE = fSAMPLEMAX6 4.8 4.2 4.2 mW max VDD = 3 V, fSAMPLE = fSAMPLEMAX6 Full Power-Down 5 5 5 μW max VDD = 5 V, SCLK off 3 3 3 μW max VDD = 3 V, SCLK off 1 Temperature range for A and B versions is −40°C to +85°C; temperature range for S version is −55°C to +125°C. 2 Operational from VDD = 2.0 V. 3 See the Terminology section. 4 Maximum B and S version specifications apply as typical figures when VDD = 5.25 V. 5 Guaranteed by characterization. 6 For A version: fSAMPLEMAX = 1 MSPS; B and S versions: fSAMPLEMAX = 600 kSPS. 7 See the Power vs. Throughput Rate section.

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AD7476/AD7477/AD7478 Rev. F | Page 5 of 24 AD7477 SPECIFICATIONS VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter A Version1 ,2 S Version1,2 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 100 kHz sine wave, fSAMPLE = 1 MSPS Signal-to-(Noise + Distortion) (SINAD) 61 61 dB min Total Harmonic Distortion (THD)3 −73 −73 dB max Peak Harmonic or Spurious Noise (SFDR)3 −74 −74 dB max Intermodulation Distortion (IMD)3 Second-Order Terms −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Third-Order Terms −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Aperture Delay 10 10 ns typ Aperture Jitter 30 30 ps typ Full Power Bandwidth 6.5 6.5 MHz typ @ 3 dB DC ACCURACY Resolution 10 10 Bits Integral Nonlinearity3 ±1 ±1 LSB max Differential Nonlinearity3 ±0.9 ±0.9 LSB max Guaranteed no missed codes to 10 bits Offset Error3 ±1 ±1 LSB max Gain Error3 ±1 ±1 LSB max ANALOG INPUT Input Voltage Ranges 0 to VDD 0 to VDD V DC Leakage Current ±1 ±1 μA max Input Capacitance 30 30 pF typ LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V 0.4 0.4 V max VDD = 3 V Input Current, IIN, SCLK Pin ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin ±1 ±1 μA typ Input Capacitance, CIN4 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD – 0.2 VDD – 0.2 V min ISOURCE = 200 μA, VDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance4 10 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 800 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 400 400 ns max Throughput Rate 1 1 MSPS max See Serial Interface section

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AD7476/AD7477/AD7478 Rev. F | Page 6 of 24 Parameter A Version1 ,2 S Version1,2 Unit Test Conditions/Comments POWER REQUIREMENTS VDD 2.7/5.25 2.7/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 2 2 mA typ VDD = 4.75 V to 5.25 V; SCLK on or off 1 1 mA typ VDD = 2.7 V to 3.6 V; SCLK on or off Normal Mode (Operational) 3.5 3.5 mA max VDD = 4.75 V to 5.25 V; fSAMPLE = 1 MSPS 1.6 1.6 mA max VDD = 2.7 V to 3.6 V; fSAMPLE = 1 MSPS Full Power-Down Mode 1 1 μA max SCLK off 80 80 μA max SCLK on Power Dissipation5 Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V; fSAMPLE = 1 MSPS 4.8 4.8 mW max VDD = 3 V; fSAMPLE = 1 MSPS Full Power-Down 5 5 μW max VDD = 5 V; SCLK off 1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C. 2 Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V minimum. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section.

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AD7476/AD7477/AD7478 Rev. F | Page 7 of 24 AD7478 SPECIFICATIONS VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter A Version1,2 S Version1,2 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 100 kHz sine wave, fSAMPLE = 1 MSPS Signal-to-(Noise + Distortion) (SINAD)3 49 49 dB min Total Harmonic Distortion (THD)3 −65 −65 dB max Peak Harmonic or Spurious Noise (SFDR)3 −65 −65 dB max Intermodulation Distortion (IMD)3 Second-Order Terms −68 −68 dB typ fa = 498.7 kHz, fb = 508.7 kHz Third-Order Terms −68 −68 dB typ fa = 498.7 kHz, fb = 508.7 kHz Aperture Delay 10 10 ns typ Aperture Jitter 30 30 ps typ Full Power Bandwidth 6.5 6.5 MHz typ @ 3 dB DC ACCURACY Resolution 8 8 Bits Integral Nonlinearity3 ±0.5 ±0.5 LSB max Differential Nonlinearity3 ±0.5 ±0.5 LSB max Guaranteed no missed codes to eight bits Offset Error ±0.5 ±0.5 LSB max Gain Error ±0.5 ±0.5 LSB max Total Unadjusted Error (TUE) ±0.5 ±0.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to VDD 0 to VDD V DC Leakage Current ±1 ±1 μA max Input Capacitance 30 30 pF typ LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V 0.4 0.4 V max VDD = 3 V Input Current, IIN, SCLK Pin ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin ±1 ±1 μA typ Input Capacitance, CIN4 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD − 0.2 VDD − 0.2 V min ISOURCE = 200 μA, VDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance4 10 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 800 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 400 400 ns max Throughput Rate 1 1 MSPS max See Serial Interface section POWER REQUIREMENTS VDD 2.7/5.25 2.7/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 2 2 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off 1 1 mA typ VDD = 2.7 V to 3.6 V, SCLK on or off Normal Mode (Operational) 3.5 3.5 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS 1.6 1.6 mA max VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS Full Power-Down Mode 1 1 μA max SCLK off 80 80 μA max SCLK on

Page 9

AD7476/AD7477/AD7478 Rev. F | Page 8 of 24 Parameter A Version1,2 S Version1,2 Unit Test Conditions/Comments Power Dissipation5 Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V, fSAMPLE = 1 MSPS 4.8 4.8 mW max VDD = 3 V, fSAMPLE = 1 MSPS Full Power-Down 5 5 μW max VDD = 5 V, SCLK off 1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C. 2 Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V minimum. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. TIMING SPECIFICATIONS VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX1 Parameter2,3 3 V 5 V Unit Description fSCLK4 10 10 kHz min 20 20 MHz max A version 12 12 MHz max B version tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 10 10 ns min Minimum CS pulsewidth t2 10 10 ns min CS to SCLK setup time t35 20 20 ns max Delay from CS until SDATA three-state disabled t45 40 20 ns max Data access time after SCLK falling edge, A version 70 20 ns max Data access time after SCLK falling edge, B version t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulsewidth t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulsewidth t7 10 10 ns min SCLK to data valid hold time t86 10 10 ns min SCLK falling edge to SDATA high impedance 25 25 ns max SCLK falling edge to SDATA high impedance tPOWER-UP7 1 1 μs typ Power-up time from full power-down 1 3 V specifications apply from VDD = 2.7 V to 3.6 V for A version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B version; 5 V specifications apply from VDD = 4.75 V to 5.25 V. 2 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 3 Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version. 4 Mark/space ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 6 t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus loading. 7 See Power-Up Time section. 01 02 4- 00 2 200µA IOL 200µA IOH 1.6VTO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Digital Output Timing Specifications

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AD7476/AD7477/AD7478 Rev. F | Page 9 of 24 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating VDD to GND −0.3 V to +7 V Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range Commercial Range (A, B Versions) –40°C to +85°C Military Range (S Version) −55°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C SOT-23 Package θJA Thermal Impedance 230°C/W θJC Thermal Impedance 92°C/W Lead Temperature, Soldering Reflow (10 sec to 30 sec) 235 (0/+5)°C Pb-free Temperature Soldering Reflow 255 (0/+5)°C ESD 3.5 kV 1Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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