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AD7490BRUZ-REEL7

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AD7490BRUZ-REEL7

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Part Number AD7490BRUZ-REEL7
Manufacturer Analog Devices Inc.
Description IC ADC 12BIT 16CHAN 28TSSOP
Datasheet AD7490BRUZ-REEL7 Datasheet
Package 28-TSSOP (0.173", 4.40mm Width)
In Stock 12,670 piece(s)
Unit Price $ 8.4322 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 8 - Jun 13 (Choose Expedited Shipping)
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Part Number # AD7490BRUZ-REEL7 (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7490BRUZ-REEL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7490BRUZ-REEL7Datasheet
Package28-TSSOP (0.173", 4.40mm Width)
Series-
Number of Bits12
Sampling Rate (Per Second)1M
Number of Inputs16
Input TypeSingle Ended
Data InterfaceSPI, DSP
ConfigurationMUX-S/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeExternal
Voltage - Supply, Analog2.7 V ~ 5.25 V
Voltage - Supply, Digital2.7 V ~ 5.25 V
Features-
Operating Temperature-40°C ~ 85°C
Package / Case28-TSSOP (0.173", 4.40mm Width)
Supplier Device Package28-TSSOP
Mounting Type-

AD7490BRUZ-REEL7 Datasheet

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16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP Data Sheet AD7490 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Fast throughput rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low power at maximum throughput rates 5.4 mW maximum at 870 kSPS with 3 V supplies 12.5 mW maximum at 1 MSPS with 5 V supplies 16 (single-ended) inputs with sequencer Wide input bandwidth 69.5 dB SNR at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface, SPI/QSPI™/MICROWIRE™/ DSP compatible Full shutdown mode: 0.5 µA maximum 28-lead TSSOP and 32-lead LFCSP packages FUNCTIONAL BLOCK DIAGRAM REFIN VIN0 VIN15 AGND VDD AD7490 INPUT MUX 12-BIT SUCCESSIVE APPROXIMATION ADC CONTROL LOGICSEQUENCER SCLK DOUT DIN CS VDRIVE T/H 02 69 1- 00 1 Figure 1. GENERAL DESCRIPTION The AD7490 is a 12-bit high speed, low power, 16-channel, successive approximation ADC. The part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 1 MSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz. The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7490 uses advanced design techniques to achieve very low power dissipation at high throughput rates. For maximum throughput rates, the AD7490 consumes just 1.8 mA with 3 V supplies, and 2.5 mA with 5 V supplies. By setting the relevant bits in the control register, the analog input range for the part can be selected to be a 0 V to REFIN input or a 0 V to 2 × REFIN input, with either straight binary or twos complement output coding. The AD7490 features 16 single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequen- tially. The conversion time is determined by the SCLK frequency because this is also used as the master clock to control the conversion. The AD7490 is available in a 32-lead LFCSP and a 28-lead TSSOP package. PRODUCT HIGHLIGHTS 1. The AD7490 offers up to 1 MSPS throughput rates. At maximum throughput with 3 V supplies, the AD7490 dissipates just 5.4 mW of power. 2. A sequence of channels can be selected, through which the AD7490 cycles and converts. 3. The AD7490 operates from a single 2.7 V to 5.25 V supply. The VDRIVE function allows the serial interface to connect directly to either 3 V or 5 V processor systems independent of VDD. 4. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The part also features various shutdown modes to maximize power efficiency at lower throughput rates. Power consumption is 0.5 µA, maximum, when in full shutdown. 5. The part features a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.

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AD7490 Data Sheet Rev. D | Page 2 of 28 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 10 Internal Register Structure ............................................................ 12 Control Register .......................................................................... 12 Shadow Register ......................................................................... 14 Theory of Operation ...................................................................... 16 Circuit Information .................................................................... 16 Converter Operation .................................................................. 16 ADC Transfer Function ............................................................. 17 Typical Connection Diagram ................................................... 18 Modes of Operation ................................................................... 19 Serial Interface ............................................................................ 22 Power vs. Throughput Rate ....................................................... 23 Microprocessor Interfacing ....................................................... 24 Application Hints ....................................................................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27 REVISION HISTORY 12/12—Rev. C to Rev. D Changes to Figure 4 and Table 4 ............................................................. 7 Updated Outline Dimensions (Changed CP-32-2 to CP-32-7) ..... 26 Changes to Ordering Guide ........................................................... 27 6/09—Rev. B to Rev. C Change to IDD Auto Standby Mode Parameter, Table 1 ............... 4 5/08—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Table 1 ............................................................................ 3 Changes to Figure 12 and Figure 13 ............................................. 14 Changes to Figure 14 ...................................................................... 15 Changes to Reference Section ....................................................... 19 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 10/02—Rev. 0 to Rev. A Addition to General Description..................................................... 1 Changes to Timing Specification Notes ......................................... 4 Change to Absolute Maximum Ratings ......................................... 5 Addition to Ordering Guide ............................................................ 5 Changes to Typical Performance Characteristics .......................... 8 Added new Figure 9 .......................................................................... 8 Changes to Figure 12 and Figure 14............................................. 11 Changes to Figure 20 ...................................................................... 13 Changes to Figure 20 to Figure 26 ................................................ 14 Addition to Analog Input section ................................................ 14 Change to Figure 29 caption ......................................................... 18 Change to Figure 30 to Figure 32 ................................................. 18 Added Application Hints section ................................................. 20 1/02—Revision 0: Initial Version

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Data Sheet AD7490 Rev. D | Page 3 of 28 SPECIFICATIONS VDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK1 = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Temperature range (B Version): −40°C to +85°C. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal-to-(Noise + Distortion) (SINAD)2 VDD = 5 V 69 70.5 dB VDD = 3 V 68 69.5 dB Signal-to-Noise Ratio (SNR)2 69.5 dB Total Harmonic Distortion (THD)2 VDD = 5 V −84 −74 dB VDD = 3 V −77 −71 dB Peak Harmonic or Spurious Noise (SFDR)2 VDD = 5 V −86 −75 dB VDD = 3 V −80 −73 dB Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −85 dB Third-Order Terms −85 dB Aperture Delay 10 ns Aperture Jitter 50 ps Channel-to-Channel Isolation2 fIN = 400 kHz −82 dB Full Power Bandwidth 3 dB 8.2 MHz 0.1 dB 1.6 MHz DC ACCURACY2 Resolution 12 Bits Integral Nonlinearity ±1 LSB Differential Nonlinearity Guaranteed no missed codes to 12 bits −0.95/+1.5 LSB 0 V to REFIN Input Range Straight binary output coding Offset Error ±0.6 ±8 LSB Offset Error Match ±0.5 LSB Gain Error ±2 LSB Gain Error Match ±0.6 LSB 0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos complement output coding offset Positive Gain Error ±2 LSB Positive Gain Error Match ±0.5 LSB Zero Code Error ±0.6 ±8 LSB Zero Code Error Match ±0.5 LSB Negative Gain Error ±1 LSB Negative Gain Error Match ±0.5 LSB ANALOG INPUT Input Voltage Range RANGE bit set to 1 0 REFIN V RANGE bit set to 0, VDD = 4.75 V to 5.25 V for 0 V to 2 × REFIN 0 2 × REFIN V DC Leakage Current ±1 µA Input Capacitance 20 pF REFERENCE INPUT REFIN Input Voltage ±1% specified performance 2.5 V DC Leakage Current ±1 µA REFIN Input Impedance fSAMPLE = 1 MSPS 36 kΩ

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AD7490 Data Sheet Rev. D | Page 4 of 28 Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL 0.3 × VDRIVE V Input Current, IIN VIN = 0 V or VDRIVE ±0.01 ±1 µA Input Capacitance, CIN+3 10 pF LOGIC OUTPUTS Output High Voltage, VOH ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V VDRIVE − 0.2 V Output Low Voltage, VOL ISINK = 200 µA 0.4 V Floating State Leakage Current WEAK/TRI bit set to 0 ±10 µA Floating State Output Capacitance3 WEAK/TRI bit set to 0 10 pF Output Coding Coding bit set to 1 Straight (Natural) Binary Coding bit set to 0 Twos Complement CONVERSION RATE Conversion Time 16 SCLK cycles, SCLK = 20 MHz 800 ns Track-and-Hold Acquisition Time2 Sine wave input 300 ns Full-scale step input 300 ns Throughput Rate VDD = 5 V (see the Serial Interface section) 1 MSPS POWER REQUIREMENTS VDD 2.7 5.25 V VDRIVE 2.7 5.25 V IDD4 Digital inputs = 0 V or VDRIVE Normal Mode (Static) VDD = 2.7 V to 5.25 V, SCLK on or off 600 µA Normal Mode (Operational) VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2.5 mA (fS = Maximum Throughput) VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz 1.8 mA Auto Standby Mode fSAMPLE = 500 kSPS 1.55 mA Static 100 µA Auto Shutdown Mode fSAMPLE = 250 kSPS 960 µA Static 0.5 µA Full Shutdown Mode SCLK on or off 0.02 0.5 µA Power Dissipation4 Normal Mode (Operational) VDD = 5 V, fSCLK = 20 MHz 12.5 mW VDD = 3 V, fSCLK = 20 MHz 5.4 mW Auto Standby Mode (Static) VDD = 5 V 460 µW VDD = 3 V 276 µW Auto Shutdown Mode (Static) VDD = 5 V 2.5 µW VDD = 3 V 1.5 µW Full Shutdown Mode VDD = 5 V 2.5 µW VDD = 3 V 1.5 µW 1 Specifications apply for fSCLK up to 20 MHz. However, for serial interfacing requirements, see the Timing Specifications section. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section.

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Data Sheet AD7490 Rev. D | Page 5 of 28 TIMING SPECIFICATIONS VDD = 2.7 V to 5.25 V, VDRIVE ≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Table 2. Timing Specifications1 Limit at TMIN, TMAX Parameter VDD = 3 V VDD = 5 V Unit Description fSCLK2 10 10 kHz min 16 20 MHz max tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t2 12 10 ns min CS to SCLK setup time t33 20 14 ns max Delay from CS until DOUT three-state disabled t3b4 30 20 ns max Delay from CS to DOUT valid t43 60 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 15 15 ns min SCLK to DOUT valid hold time t85 15/50 15/50 ns min/max SCLK falling edge to DOUT high impedance t9 20 20 ns min DIN setup time prior to SCLK falling edge t10 5 5 ns min DIN hold time after SCLK falling edge t11 20 20 ns min 16th SCLK falling edge to CS high t12 1 1 µs max Power-up time from full power-down/auto shutdown/auto standby modes 1 Guaranteed by characterization. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2). The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 The mark/space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with VDD = 3 V to give a throughput of 870 kSPS. Care must be taken when interfacing to account for data access time, t4, and the setup time required for the user’s processor. These two times determine the maximum SCLK frequency with which the user’s system can operate (see the Serial Interface section). 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE . 4 t3b represents a worst-case figure for having ADD3 available on the DOUT line, that is, if the AD7490 goes back into three-state at the end of a conversion and some other device takes control of the bus between conversions, the user has to wait a maximum time of t3b before having ADD3 valid on the DOUT line. If the DOUT line is weakly driven to ADD3 between conversions, the user typically has to wait 17 ns at 3 V and 12 ns at 5 V after the CS falling edge before seeing ADD3 valid on DOUT. 5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading. 02 69 1- 00 2 200µA IOL 200µA IOH 1.6VTO OUTPUTPIN CL 25pF Figure 2. Load Circuit for Digital Output Timing Specifications

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AD7490 Data Sheet Rev. D | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to GND −0.3 V to +7 V VDRIVE to GND −0.3 V to VDD + 0.3 V Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V REFIN to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Ranges Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C LFCSP, TSSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 108.2°C/W (LFCSP) 97.9°C/W (TSSOP) θJC Thermal Impedance 32.71°C/W (LFCSP) 14°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 1 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

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Data Sheet AD7490 Rev. D | Page 7 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 02 69 1- 00 3 AD7490 TOP VIEW (Not to Scale) VIN11 1 VIN1228 VIN10 2 VIN1327 VIN9 3 VIN1426 NC 4 VIN1525 VIN8 5 AGND24 VIN7 6 REFIN23 VIN6 7 VDD22 VIN5 8 AGND21 VIN4 9 CS20 VIN3 10 DIN19 VIN2 11 NC18 VIN1 12 VDRIVE17 VIN0 13 SCLK16 AGND 14 DOUT15 NC = NO CONNECT ALL NC PINS SHOULD BE CONNECTED STRAIGHT TO AGND Figure 3. 28-Lead TSSOP Pin Configuration 02 69 1- 03 2 NOTES 1. NC = NO CONNECT. ALL NC PINS SHOULD BE CONNECTED STRAIGHT TO AGND. 2. CONNECT EXPOSED PAD TO GND AD7490 TOP VIEW (Not to Scale) 1 VIN15 2 NC 3 AGND 4 REFIN 5 VDD 6 AGND 7 CS 8 DIN 24 23 22 21 20 19 18 17 NC VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 NC 9 10 11 12 13 14 15 16 V I N 2 V I N 1 V I N 0 A G N D D O U T SC LK V D R IV E N C 32 31 30 29 28 27 26 25 N C V I N 9 V I N 10 V I N 11 V I N 12 V I N 13 V I N 14 N C Figure 4. 32-Lead LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description TSSOP LFCSP 20 18 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7490 and also frames the serial data transfer. 23 21 REFIN Reference Input for the AD7490. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. 22 20 VDD Power Supply Input. The VDD range for the AD7490 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, VDD should be from 4.75 V to 5.25 V. 14, 21, 24 12, 19, 22 AGND Analog Ground. Ground reference point for all circuitry on the AD7490. All analog/digital input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. 13 to 5, 3 to 1, 28 to 25 11 to 9, 7 to 2, 31 to 26, 24 VIN0 to VIN15 Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed into the on chip track-and-hold. The analog input channel to be converted is selected by using the address bits ADD3 through ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the sequence register to be programmed. The input range for all input channels can extend from 0 V to REFIN or 0 V to 2 × REFIN as selected via the RANGE bit in the control register. Any unused input channels should be connected to AGND to avoid noise pickup. 19 17 DIN Data In. Logic input. Data to be written to the control register of the AD7490 is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section). 15 13 DOUT Data Out. Logic output. The conversion result from the AD7490 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, which is provided by MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register. 16 14 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7490. 17 15 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the AD7490 operates. N/A EP EPAD Exposed Pad. Connect exposed pad to GND.

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AD7490 Data Sheet Rev. D | Page 8 of 28 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 shows a typical FFT plot for the AD7490 at 1 MSPS sample rate and 50 kHz input frequency. Figure 7 shows the power supply rejection ratio vs. supply ripple frequency for the AD7490. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency fS. ( )       ×= sPf Pf PSRR log10dB where: Pf is equal to the power at frequency f in ADC output. PfS is equal to power at frequency fS coupled onto the ADC VDD supply input. Here, a 200 mV p-p sine wave is coupled onto the VDD supply. 10 nF decoupling was used on the supply, and a 1 µF decoupling capacitor was used on the REFIN pin. 5 –95 –75 –55 –35 –15 0 50 100 150 200 250 300 350 400 500450 8192 POINT FFT fSAMPLE = 1MSPS fIN = 50kHZ SINAD = 70.697dB THD = –79.171dB SFDR = –79.93dB 02 69 1- 00 4 FREQUENCY (kHz) SN R (d B ) Figure 5. Dynamic Performance at 1 MSPS 75 55 60 65 70 10 100 1000 02 69 1- 00 5 INPUT FREQUENCY (kHz) SI N A D (d B ) fS = MAX THROUGHPUT TA = 25°C RANGE = 0V TO REFIN VDD = VDRIVE = 5.25V VDD = VDRIVE = 4.75V VDD = VDRIVE = 3.6V VDD = VDRIVE = 2.7V Figure 6. SINAD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS –20 –90 –80 –70 –60 –50 –40 –30 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M 02 69 1- 00 6 INPUT FREQUENCY (Hz) PS R R (d B ) VDD = 5V VDD = 3V VDD = 3V/5V, 10nF CAP 200mV p-p SINE WAVE ON VDD REFIN = 2.5V, 1µF CAP TA = 25°C Figure 7. PSRR vs. Supply Ripple Frequency –50 –90 –85 –80 –75 –70 –65 –60 –55 10 100 1000 02 69 1- 00 7 INPUT FREQUENCY (kHz) TH D (d B ) VDD = VDRIVE = 2.7V VDD = VDRIVE = 3.6V VDD = VDRIVE = 4.75V VDD = VDRIVE = 5.25V fS = MAX THROUGHPUT TA = 25°C RANGE = 0V TO REFIN Figure 8. THD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS

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Data Sheet AD7490 Rev. D | Page 9 of 28 –50 –85 –80 –75 –70 –65 –60 –55 10 100 1000 02 69 1- 00 8 INPUT FREQUENCY (Hz) TH D (d B ) RIN = 1000Ω RIN = 100Ω RIN = 10Ω RIN = 5Ω fS = 1MSPS TA = 25°C VDD = 5.25V RANGE = 0V TO REFIN Figure 9. THD vs. Analog Input Frequency for Various Analog Source Impedances 1.0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 3584 4096 02 69 1- 00 9 CODE IN L ER R O R (L SB ) VDD = VDRIVE = 5V TEMPERATURE = 25°C Figure 10. Typical INL 1.0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 3584 4096 02 69 1- 01 0 CODE D N L ER R O R (L SB ) VDD = VDRIVE = 5V TEMPERATURE = 25°C Figure 11. Typical DNL

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Jova*****Massey

May 25, 2020

I am always amazed at the cost of automotive or marine costs when a rectifier is needed while these will do the exact same thing if you are a bit technically minded to wire them up.

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May 22, 2020

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May 20, 2020

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May 18, 2020

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May 12, 2020

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May 9, 2020

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April 30, 2020

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April 29, 2020

Every little component you can always find in here, and good suggestion for relative times too.

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April 24, 2020

Very quick dispatch, arrived the next day. Item as described. Thanks!

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