AD7606BSTZ-4RL

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8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC Data Sheet AD7606/AD7606-6/AD7606-4 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 8/6/4 simultaneously sampled inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 16-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Performance 7 kV ESD rating on analog input channels 95.5 dB SNR, −107 dB THD ±0.5 LSB INL, ±0.5 LSB DNL Low power: 100 mW Standby mode: 25 mW Temperature range: −40°C to +85°C 64-lead LQFP package APPLICATIONS Power-line monitoring and protection systems Multiphase motor control Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions Resolution Single- Ended Inputs True Differential Inputs Number of Simultaneous Sampling Channels 18 Bits AD7608 AD7609 8 16 Bits AD7606 8 AD7606-6 6 AD7606-4 4 14 Bits AD7607 8 FUNCTIONAL BLOCK DIAGRAM V1 V1GND RFB1MΩ 1MΩ RFB CLAMP CLAMP SECOND-ORDER LPF T/H V2 V2GND RFB1MΩ 1MΩ RFB CLAMP CLAMP SECOND- ORDER LPF T/H V3 V3GND RFB1MΩ 1MΩ RFB CLAMP CLAMP SECOND-ORDER LPF T/H V4 V4GND RFB1MΩ 1MΩ RFB CLAMP CLAMP SECOND-ORDER LPF T/H V5 V5GND RFB1MΩ 1MΩ RFB CLAMP CLAMP SECOND- ORDER LPF T/H V6 V6GND RFB1MΩ 1MΩ RFB CLAMP CLAMP SECOND-ORDER LPF T/H V7 V7GND RFB1MΩ 1MΩ RFB CLAMP CLAMP SECOND-ORDER LPF T/H V8 V8GND RFB1MΩ 1MΩ RFB CLAMP CLAMP SECOND- ORDER LPF T/H 8:1 MUX AGND BUSY FRSTDATA CONVST A CONVST B RESET RANGE CONTROL INPUTS CLK OSC REFIN/REFOUT REF SELECT AGND OS 2 OS 1 OS 0 DOUTA DOUTB RD/SCLK CS PAR/SER/BYTE SEL VDRIVE 16-BIT SAR DIGITAL FILTER PARALLEL/ SERIAL INTERFACE 2.5V REF REFCAPB REFCAPA SERIAL PARALLEL REGCAP 2.5V LDO REGCAP 2.5V LDO AVCCAVCC DB[15:0] AD7606 08 47 9- 00 1 Figure 1.

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AD7606/AD7606-6/AD7606-4 Data Sheet Rev. E | Page 2 of 36 TABLE OF CONTENTS Features........................................................................................... 1 Applications ................................................................................... 1 Functional Block Diagram ............................................................ 1 Revision History ............................................................................ 2 General Description ...................................................................... 3 Specifications ................................................................................. 4 Timing Specifications ................................................................ 7 Absolute Maximum Ratings ....................................................... 11 Thermal Resistance ................................................................. 11 ESD Caution............................................................................. 11 Pin Configurations and Function Descriptions ........................ 12 Typical Performance Characteristics.......................................... 17 Terminology ................................................................................. 21 Theory of Operation.................................................................... 22 Converter Details..................................................................... 22 Analog Input ............................................................................ 22 ADC Transfer Function .......................................................... 23 Internal/External Reference .................................................... 24 Typical Connection Diagram.................................................. 25 Power-Down Modes ................................................................ 25 Conversion Control ................................................................. 26 Digital Interface ........................................................................... 27 Parallel Interface (PAR/SER/BYTE SEL = 0)......................... 27 Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) .............. 27 Serial Interface (PAR/SER/BYTE SEL = 1)............................ 27 Reading During Conversion ................................................... 28 Digital Filter ............................................................................. 29 Layout Guidelines .................................................................... 32 Outline Dimensions .................................................................... 34 Ordering Guide........................................................................ 34 REVISION HISTORY 5/2018—Rev. D to Rev. E Changes to Patent Note, Note 1 .....................................................3 Changes to tCONV Parameter, Table 3..............................................7 11/2017—Rev. C to Rev. D Changes to Features Section ..........................................................1 Changes to Specifications Table Summary ...................................3 Deleted Endnote 1, Table 1; Renumbered Sequentially ...............6 Change to Table 6 .........................................................................14 Changes to Typical Performance Characteristics Section .........17 Changes to Terminology Section.................................................21 Changes to Ordering Guide .........................................................34 1/2012—Rev. B to Rev. C Changes to Analog Input Ranges Section ...................................22 10/2011—Rev. A to Rev. B Changes to Input High Voltage (VINH) and Input Low Voltage (VINL ) Parameters and Endnote 6, Table 2 ....................................4 Changes to Table 3 ..........................................................................7 Changes to Table 4 ........................................................................11 Changes to Pin 32 Description, Table 6 ......................................13 Changes to Analog Input Clamp Protection Section .................22 Changes to Typical Connection Diagram Section .....................25 8/2010—Rev. 0 to Rev. A Changes to Note 1, Table 2.............................................................6 5/2010—Revision 0: Initial Version

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Data Sheet AD7606/AD7606-6/AD7606-4 Rev. E | Page 3 of 36 GENERAL DESCRIPTION The AD76061/AD7606-6/AD7606-4 are 16-bit, simultaneous sampling, analog-to-digital data acquisition systems (DAS) with eight, six, and four channels, respectively. Each part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, a 16-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7606/AD7606-6/AD7606-4 operate from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5 V. The AD7606 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth. 1 Protected by US Patent Number 8,072,360.

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AD7606/AD7606-6/AD7606-4 Data Sheet Rev. E | Page 4 of 36 SPECIFICATIONS VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 200 kSPS, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE fIN = 1 kHz sine wave unless otherwise noted Signal-to-Noise Ratio (SNR)1, 2 Oversampling by 16; ±10 V range; fIN = 130 Hz 94 95.5 dB Oversampling by 16; ±5 V range; fIN = 130 Hz 93 94.5 dB No oversampling; ±10 V Range 88.5 90 dB No oversampling; ±5 V range 87.5 89 dB Signal-to-(Noise + Distortion) (SINAD)1 No oversampling; ±10 V range 88 90 dB No oversampling; ±5 V range 87 89 dB Dynamic Range No oversampling; ±10 V range 90.5 dB No oversampling; ±5 V range 90 dB Total Harmonic Distortion (THD)1 −107 −95 dB Peak Harmonic or Spurious Noise (SFDR)1 −108 dB Intermodulation Distortion (IMD)1 fa = 1 kHz, fb = 1.1 kHz Second-Order Terms −110 dB Third-Order Terms −106 dB Channel-to-Channel Isolation1 fIN on unselected channels up to 160 kHz −95 dB ANALOG INPUT FILTER Full Power Bandwidth −3 dB, ±10 V range 23 kHz −3 dB, ±5 V range 15 kHz −0.1 dB, ±10 V range 10 kHz −0.1 dB, ±5 V range 5 kHz tGROUP DELAY ±10 V Range 11 µs ±5 V Range 15 µs DC ACCURACY Resolution No missing codes 16 Bits Differential Nonlinearity1 ±0.5 ±0.99 LSB3 Integral Nonlinearity1 ±0.5 ±2 LSB Total Unadjusted Error (TUE) ±10 V range ±6 LSB ±5 V range ±12 LSB Positive Full-Scale Error1, 4 External reference ±8 ±32 LSB Internal reference ±8 LSB Positive Full-Scale Error Drift External reference ±2 ppm/°C Internal reference ±7 ppm/°C Positive Full-Scale Error Matching1 ±10 V range 5 32 LSB ±5 V range 16 40 LSB Bipolar Zero Code Error1, 5 ±10 V range ±1 ±6 LSB ± 5 V range ±3 ±12 LSB Bipolar Zero Code Error Drift ±10 V range 10 µV/°C ± 5 V range 5 µV/°C Bipolar Zero Code Error Matching1 ±10 V range 1 8 LSB ±5 V range 6 22 LSB Negative Full-Scale Error1, 4 External reference ±8 ±32 LSB Internal reference ±8 LSB Negative Full-Scale Error Drift External reference ±4 ppm/°C Internal reference ±8 ppm/°C Negative Full-Scale Error Matching1 ±10 V range 5 32 LSB ±5 V range 16 40 LSB

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Data Sheet AD7606/AD7606-6/AD7606-4 Rev. E | Page 5 of 36 Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUT Input Voltage Ranges RANGE = 1 ±10 V RANGE = 0 ±5 V Analog Input Current 10 V; see Figure 31 5.4 µA 5 V; see Figure 31 2.5 µA Input Capacitance6 5 pF Input Impedance See the Analog Input section 1 MΩ REFERENCE INPUT/OUTPUT Reference Input Voltage Range See the ADC Transfer Function section 2.475 2.5 2.525 V DC Leakage Current ±1 µA Input Capacitance6 REF SELECT = 1 7.5 pF Reference Output Voltage REFIN/REFOUT 2.49/ 2.505 V Reference Temperature Coefficient ±10 ppm/°C LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDRIVE V Input Low Voltage (VINL) 0.3 × VDRIVE V Input Current (IIN) ±2 µA Input Capacitance (CIN)6 5 pF LOGIC OUTPUTS Output High Voltage (VOH) ISOURCE = 100 µA VDRIVE − 0.2 V Output Low Voltage (VOL) ISINK = 100 µA 0.2 V Floating-State Leakage Current ±1 ±20 µA Floating-State Output Capacitance6 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time All eight channels included; see Table 3 4 µs Track-and-Hold Acquisition Time 1 µs Throughput Rate Per channel, all eight channels included 200 kSPS POWER REQUIREMENTS AVCC 4.75 5.25 V VDRIVE 2.3 5.25 V ITOTAL Digital inputs = 0 V or VDRIVE Normal Mode (Static) AD7606 16 22 mA AD7606-6 14 20 mA AD7606-4 12 17 mA Normal Mode (Operational)7 fSAMPLE = 200 kSPS AD7606 20 27 mA AD7606-6 18 24 mA AD7606-4 15 21 mA Standby Mode 5 8 mA Shutdown Mode 2 6 µA

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AD7606/AD7606-6/AD7606-4 Data Sheet Rev. E | Page 6 of 36 Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation Normal Mode (Static) AD7606 80 115.5 mW Normal Mode (Operational)7 fSAMPLE = 200 kSPS AD7606 100 142 mW AD7606-6 90 126 mW AD7606-4 75 111 mW Standby Mode 25 42 mW Shutdown Mode 10 31.5 µW 1See the Terminology section. 2 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 3 LSB means least significant bit. With ±5 V input range, 1 LSB = 152.58 µV. With ±10 V input range, 1 LSB = 305.175 µV. 4 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 5 Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section. 6 Sample tested during initial release to ensure compliance. 7 Operational power/current figure includes contribution when running in oversampling mode.

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Data Sheet AD7606/AD7606-6/AD7606-4 Rev. E | Page 7 of 36 TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted.1 Table 3. Limit at TMIN, TMAX (0.1 × VDRIVE and 0.9 × VDRIVE Logic Input Levels) Limit at TMIN, TMAX (0.3 × VDRIVE and 0.7 × VDRIVE Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description PARALLEL/SERIAL/BYTE MODE tCYCLE 1/throughput rate 5 5 µs Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines 9.4 µs Serial mode reading after a conversion; VDRIVE = 2.7 V 9.7 10.7 µs Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines tCONV2 Conversion time 3.45 4 4.2 3.45 4 4.2 µs Oversampling off; AD7606 3 3 µs Oversampling off; AD7606-6 2 2 µs Oversampling off; AD7606-4 7.87 9.1 7.87 9.1 µs Oversampling by 2; AD7606 16.05 18.8 16.05 18.8 µs Oversampling by 4; AD7606 33 39 33 39 µs Oversampling by 8; AD7606 66 78 66 78 µs Oversampling by 16; AD7606 133 158 133 158 µs Oversampling by 32; AD7606 257 315 257 315 µs Oversampling by 64; AD7606 tWAKE-UP STANDBY 100 100 µs STBY rising edge to CONVST x rising edge; power-up time from standby mode tWAKE-UP SHUTDOWN Internal Reference 30 30 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode External Reference 13 13 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode tRESET 50 50 ns RESET high pulse width tOS_SETUP 20 20 ns BUSY to OS x pin setup time tOS_HOLD 20 20 ns BUSY to OS x pin hold time t1 40 45 ns CONVST x high to BUSY high t2 25 25 ns Minimum CONVST x low pulse t3 25 25 ns Minimum CONVST x high pulse t4 0 0 ns BUSY falling edge to CS falling edge setup time t53 0.5 0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges t6 25 25 ns Maximum time between last CS rising edge and BUSY falling edge t7 25 25 ns Minimum delay between RESET low to CONVST x high PARALLEL/BYTE READ OPERATION t8 0 0 ns CS to RD setup time t9 0 0 ns CS to RD hold time t10 RD low pulse width 16 19 ns VDRIVE above 4.75 V 21 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 32 37 ns VDRIVE above 2.3 V t11 15 15 ns RD high pulse width t12 22 22 ns CS high pulse width (see Figure 5); CS and RD linked

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AD7606/AD7606-6/AD7606-4 Data Sheet Rev. E | Page 8 of 36 Limit at TMIN, TMAX (0.1 × VDRIVE and 0.9 × VDRIVE Logic Input Levels) Limit at TMIN, TMAX (0.3 × VDRIVE and 0.7 × VDRIVE Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description t13 Delay from CS until DB[15:0] three-state disabled 16 19 ns VDRIVE above 4.75 V 20 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 37 ns VDRIVE above 2.3 V t144 Data access time after RD falling edge 16 19 ns VDRIVE above 4.75 V 21 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 32 37 ns VDRIVE above 2.3 V t15 6 6 ns Data hold time after RD falling edge t16 6 6 ns CS to DB[15:0] hold time t17 22 22 ns Delay from CS rising edge to DB[15:0] three-state enabled SERIAL READ OPERATION fSCLK Frequency of serial read clock 23.5 20 MHz VDRIVE above 4.75 V 17 15 MHz VDRIVE above 3.3 V 14.5 12.5 MHz VDRIVE above 2.7 V 11.5 10 MHz VDRIVE above 2.3 V t18 Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid 15 18 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 30 35 ns VDRIVE = 2.3 V to 2.7 V t194 Data access time after SCLK rising edge 17 20 ns VDRIVE above 4.75 V 23 26 ns VDRIVE above 3.3 V 27 32 ns VDRIVE above 2.7 V 34 39 ns VDRIVE above 2.3 V t20 0.4 tSCLK 0.4 tSCLK ns SCLK low pulse width t21 0.4 tSCLK 0.4 tSCLK ns SCLK high pulse width t22 7 7 SCLK rising edge to DOUTA/DOUTB valid hold time t23 22 22 ns CS rising edge to DOUTA/DOUTB three-state enabled FRSTDATA OPERATION t24 Delay from CS falling edge until FRSTDATA three- state disabled 15 18 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns VDRIVE above 2.3 V t25 ns Delay from CS falling edge until FRSTDATA high, serial mode 15 18 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns VDRIVE above 2.3 V t26 Delay from RD falling edge to FRSTDATA high 16 19 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns VDRIVE above 2.3 V

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Data Sheet AD7606/AD7606-6/AD7606-4 Rev. E | Page 9 of 36 Limit at TMIN, TMAX (0.1 × VDRIVE and 0.9 × VDRIVE Logic Input Levels) Limit at TMIN, TMAX (0.3 × VDRIVE and 0.7 × VDRIVE Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description t27 Delay from RD falling edge to FRSTDATA low 19 22 ns VDRIVE = 3.3 V to 5.25V 24 29 ns VDRIVE = 2.3 V to 2.7V t28 Delay from 16th SCLK falling edge to FRSTDATA low 17 20 ns VDRIVE = 3.3 V to 5.25V 22 27 ns VDRIVE = 2.3 V to 2.7V t29 24 29 ns Delay from CS rising edge until FRSTDATA three- state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N × tCONV) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6, tCONV = 3 µs; and for the AD7606-4, tCONV = 2 µs. 3 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets. 4 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins. Timing Diagrams tCYCLE t3 t5 t2 t4 t1 t7 tRESET tCONV CONVST A, CONVST B CONVST A, CONVST B BUSY CS RESET 08 47 9- 00 2 Figure 2. CONVST Timing—Reading After a Conversion tCYCLE t3 t5 t6 t2 t1 tCONV CONVST A, CONVST B CONVST A, CONVST B BUSY CS t7 tRESET RESET 08 47 9- 00 3 Figure 3. CONVST Timing—Reading During a Conversion