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AD7609BSTZ

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AD7609BSTZ

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Part Number AD7609BSTZ
Manufacturer Analog Devices Inc.
Description IC DAS 18BIT 8CHANNEL 64-LQFP
Datasheet AD7609BSTZ Datasheet
Package 64-LQFP
In Stock 4,396 piece(s)
Unit Price $ 41.1500 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 8 - Jun 13 (Choose Expedited Shipping)
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Part Number # AD7609BSTZ (Data Acquisition - ADCs/DACs - Special Purpose) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7609BSTZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - ADCs/DACs - Special Purpose
Datasheet AD7609BSTZDatasheet
Package64-LQFP
Series-
TypeData Acquisition System (DAS), ADC
Number of Channels-
Resolution (Bits)18 b
Sampling Rate (Per Second)200k
Data InterfaceSPI, DSP
Voltage Supply SourceAnalog and Digital
Voltage - Supply2.3 V ~ 5 V, 4.75 V ~ 5.25 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case64-LQFP
Supplier Device Package64-LQFP (10x10)

AD7609BSTZ Datasheet

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8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC Data Sheet AD7609 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 8 simultaneously sampled inputs True differential inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 18-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Performance 7 kV ESD rating on analog input channels 98 dB SNR, −107 dB THD Dynamic range: up to 105 dB typical Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package APPLICATIONS Power line monitoring and protection systems Multiphase motor control Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) COMPANION PRODUCTS External References: ADR421, ADR431 Digital Isolators: ADuM1402, ADuM5000, ADuM5402 Power: ADIsimPower, Supervisor Parametric Search Additional companion products on the AD7609 product page Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions Resolution Single- Ended Inputs True Differential Inputs Number of Simultaneous Sampling Channels 18 Bits AD7608 AD76091 8 16 Bits AD7606 8 AD7606-6 6 AD7606-4 4 14 Bits AD7607 8 1 Protected by U.S. Patent Number 8,072,360. FUNCTIONAL BLOCK DIAGRAM V1+ V1– RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB 1MΩ 1MΩ CLAMP CLAMP T/H V2+ V2– 1MΩ 1MΩ CLAMP CLAMP T/H V3+ V3– 1MΩ 1MΩ CLAMP CLAMP T/H V4+ V4– 1MΩ 1MΩ CLAMP CLAMP T/H V5+ V5– 1MΩ 1MΩ CLAMP CLAMP T/H V6+ V6– 1MΩ 1MΩ CLAMP CLAMP T/H V7+ V7– 1MΩ 1MΩ CLAMP CLAMP T/H V8+ V8– 1MΩ 1MΩ CLAMP CLAMP T/H 8:1 MUX AGND BUSY FRSTDATA CONVST A CONVST B RESET RANGE CONTROL INPUTS CLK OSC REFIN/REFOUT REF SELECT AGND OS 2 OS 1 OS 0 DOUTA DOUTB RD/SCLK CS PAR/SER SEL VDRIVE 18-BIT SAR DIGITAL FILTER PARALLEL/ SERIAL INTERFACE 2.5V REF REFCAPB REFCAPA SERIAL PARALLEL REGCAP 2.5V LDO REGCAP 2.5V LDO AVCCAVCC DB[15:0] AD7609 09 76 0- 00 1 SECOND- ORDER LPF SECOND- ORDER LPF SECOND- ORDER LPF SECOND- ORDER LPF SECOND- ORDER LPF SECOND- ORDER LPF SECOND- ORDER LPF SECOND- ORDER LPF Figure 1.

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AD7609 Data Sheet Rev. C | Page 2 of 36 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Companion Products ....................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 Timing Specifications .................................................................. 7 Absolute Maximum Ratings .......................................................... 11 Thermal Resistance .................................................................... 11 ESD Caution ................................................................................ 11 Pin Configuration and Function Descriptions ........................... 12 Typical Performance Characteristics ........................................... 15 Terminology .................................................................................... 19 Theory of Operation ...................................................................... 21 Converter Details ....................................................................... 21 Analog Input ............................................................................... 21 ADC Transfer Function ............................................................. 22 Internal/External Reference ...................................................... 23 Typical Connection Diagram ................................................... 24 Power-Down Modes .................................................................. 24 Conversion Control ................................................................... 25 Digital Interface .............................................................................. 26 Parallel Interface (PAR/SER SEL = 0) ...................................... 26 Serial Interface (PAR/SER SEL = 1) ......................................... 26 Reading During Conversion ..................................................... 27 Digital Filter ................................................................................ 28 Layout Guidelines....................................................................... 32 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34 REVISION HISTORY 5/2018—Rev. B to Rev. C Changes to Patent Note, Note 1 ...................................................... 1 Change to tCONV Parameter, Table 3 ................................................ 7 5/2014—Rev. A to Rev. B Changes to Patent Footnote ............................................................ 1 Changes to Figure 37 ...................................................................... 22 Changes to Figure 39 and Figure 40............................................. 23 2/2012—Rev. 0 to Rev. A Changes to Analog Input Ranges Section ................................... 21 7/2011—Revision 0: Initial Version

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Data Sheet AD7609 Rev. C | Page 3 of 36 GENERAL DESCRIPTION The AD7609 is an 18-bit, 8-channel, true differential, simultaneous sampling analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, an 18-bit charge redistribution successive approximation analog- to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7609 operates from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar differential input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5 V. The AD7609 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance elimi- nate the need for driver op amps and external bipolar supplies. The AD7609 antialiasing filter has a −3 dB cutoff frequency of 32 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the −3 dB bandwidth.

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AD7609 Data Sheet Rev. C | Page 4 of 36 SPECIFICATIONS VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V; fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted.1 Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE fIN = 1 kHz sine wave unless otherwise noted Signal-to-Noise Ratio (SNR)2, 3 Oversampling by 16; ±10 V range; fIN = 160 Hz 98 101 dB Oversampling by 16; ±5 V range; fIN = 160 Hz 100 dB No oversampling; ±10 V range 90 91 dB No oversampling; ±5 V range 89.5 90.5 dB Signal-to-(Noise + Distortion) (SINAD)2 No oversampling; ±10 V range 89.5 91 dB No oversampling; ±5 V range 89 90 dB Dynamic Range No oversampling; ±10 V range 91.5 dB No oversampling; ±5 V range 90.5 dB Total Harmonic Distortion (THD)2, 3 No oversampling; ±10 V range −107 −97 dB No oversampling; ±5 V range −110 −96 dB Peak Harmonic or Spurious Noise (SFDR)2 −108 dB Intermodulation Distortion (IMD)2 fa = 1 kHz, fb = 1.1 kHz Second-Order Terms −110 dB Third-Order Terms −106 dB Channel-to-Channel Isolation2 fIN on unselected channels up to 160 kHz −95 dB ANALOG INPUT FILTER Full Power Bandwidth −3 dB, ±10 V range 32 kHz −3 dB, ±5 V range 23 kHz −0.1 dB, ±10 V range 13 kHz −0.1 dB, ±5 V range 10 kHz tGROUP DELAY ±10 V range 7.1 µs ±5 V range 10.2 µs DC ACCURACY Resolution No missing codes 18 Bits Differential Nonlinearity2 ±0.75 −0.99/+2 LSB4 Integral Nonlinearity2 ±3 ±7.5 LSB Total Unadjusted Error (TUE) ±10 V range ±10 LSB ±5 V range ±90 LSB Positive Full-Scale Error2, 5 External reference ±8 ±140 LSB Internal reference ±40 LSB Positive Full-Scale Error Drift External reference ±2 ppm/°C Internal reference ±7 ppm/°C Positive Full-Scale Error Matching2 ±10 V range 12 80 LSB ±5 V range 40 100 LSB Bipolar Zero Code Error2, 6 ±10 V range ±3 ±24 LSB ± 5 V range ±3 ±48 LSB Bipolar Zero Code Error Drift ±10 V range 10 µV/°C ± 5 V range 5 µV/°C Bipolar Zero Code Error Matching2 ±10 V range 2.7 30 LSB ±5 V range 13 65 LSB Negative Full-Scale Error2, 5 External reference ±8 ±140 LSB Internal reference ±40 LSB Negative Full-Scale Error Drift External reference ±4 ppm/°C Internal reference ±8 ppm/°C Negative Full-Scale Error Matching2 ±10 V range 12 80 LSB ±5 V range 40 100 LSB

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Data Sheet AD7609 Rev. C | Page 5 of 36 Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUT Differential Input Voltage Ranges VIN = Vx+ − (Vx−) RANGE = 1; ±10 V −20 +20 V RANGE = 0; ±5 V −10 +10 V Absolute Voltage Input ±10 V range, see the Analog Input Clamp Protection section −10 +10 V ±5 V range, see the Analog Input Clamp Protection section −5 +5 V Common-Mode Input Range −4 ±5 +4 V CMRR −70 dB Analog Input Current 10 V, see Figure 28 5.4 µA 5 V, see Figure 28 2.5 µA Input Capacitance7 5 pF Input Impedance 1 MΩ REFERENCE INPUT/OUTPUT Reference Input Voltage Range 2.475 2.5 2.525 V DC Leakage Current ±1 µA Input Capacitance7 REF SELECT = 1 7.5 pF Reference Output Voltage REFIN/REFOUT 2.49/ 2.505 V Reference Temperature Coefficient ±10 ppm/°C LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDRIVE V Input Low Voltage (VINL) 0.3 × VDRIVE V Input Current (IIN) ±2 µA Input Capacitance (CIN)7 5 pF LOGIC OUTPUTS Output High Voltage (VOH) ISOURCE = 100 µA VDRIVE − 0.2 V Output Low Voltage (VOL) ISINK = 100 µA 0.2 V Floating-State Leakage Current ±1 ±20 µA Floating-State Output Capacitance7 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time All eight channels included 4 µs Track-and-Hold Acquisition Time 1 µs Throughput Rate Per channel, all eight channels included 200 kSPS POWER REQUIREMENTS AVCC 4.75 5.25 V VDRIVE 2.3 5.25 V ITOTAL Digital inputs = 0 V or VDRIVE Normal Mode (Static) 16 22 mA Normal Mode (Operational)8 fSAMPLE = 200 kSPS 20 28.5 mA Standby Mode 5 8 mA Shutdown Mode 2 11 µA

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AD7609 Data Sheet Rev. C | Page 6 of 36 Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation Normal Mode (Static) 80 115.5 mW Normal Mode (Operational)8 fSAMPLE = 200 kSPS 100 157 mW Standby Mode 25 42 mW Shutdown Mode 10 60.5 µW 1 Temperature range for B version is −40°C to +85°C. 2 See the Terminology section. 3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel and serial modes with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 4 LSB means least significant bit. With ±5 V input range, 1 LSB = 76.29 µV. With ±10 V input range, 1 LSB = 152.58 µV. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode.

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Data Sheet AD7609 Rev. C | Page 7 of 36 TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/ internal reference, TA = TMIN to TMAX, unless otherwise noted.1 Table 3. Limit at TMIN, TMAX Parameter Min Typ Max Unit Description PARALLEL/SERIAL/BYTE MODE tCYCLE 1/throughput rate 5 µs Parallel mode, reading during; or after conversion VDRIVE = 2.7 V to 5.25 V; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines 5 µs Parallel mode reading after conversion VDRIVE = 2.3 V 10.1 µs Serial mode reading after conversion; VDRIVE = 2.7 V, DOUTA and DOUTB lines 11.5 µs Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines tCONV Conversion time 3.45 4 4.2 µs Oversampling off 7.87 9.1 µs Oversampling by 2 16.05 18.8 µs Oversampling by 4 33 39 µs Oversampling by 8 66 78 µs Oversampling by 16 133 158 µs Oversampling by 32 257 315 µs Oversampling by 64 tWAKE-UP STANDBY 100 µs STBY rising edge to CONVST x rising edge; power-up time from standby mode tWAKE-UP SHUTDOWN Internal Reference 30 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode External Reference 13 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode tRESET 50 ns RESET high pulse width tOS_SETUP 20 ns BUSY to OS x pin setup time tOS_HOLD 20 ns BUSY to OS x pin hold time t1 45 ns CONVST x high to BUSY high t2 25 ns Minimum CONVST x low pulse t3 25 ns Minimum CONVST x high pulse t4 0 ns BUSY falling edge to CS falling edge setup time t52 0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges t6 25 ns Maximum time between last CS rising edge and BUSY falling edge t7 25 ns Minimum delay between RESET low to CONVST x high PARALLEL READ OPERATION t8 0 ns CS to RD setup time t9 0 ns CS to RD hold time t10 RD low pulse width 19 ns VDRIVE above 4.75 V 24 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 37 ns VDRIVE above 2.3 V t11 15 ns RD high pulse width t12 22 ns CS high pulse width (see Figure 5); CS and RD linked

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AD7609 Data Sheet Rev. C | Page 8 of 36 Limit at TMIN, TMAX Parameter Min Typ Max Unit Description t13 Delay from CS until DB[15:0] three-state disabled 19 ns VDRIVE above 4.75 V 24 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 37 ns VDRIVE above 2.3 V t143 Data access time after RD falling edge 19 ns VDRIVE above 4.75 V 24 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 37 ns VDRIVE above 2.3 V t15 6 ns Data hold time after RD falling edge t16 6 ns CS to DB[15:0] hold time t17 22 ns Delay from CS rising edge to DB[15:0] three-state enabled SERIAL READ OPERATION fSCLK Frequency of serial read clock 20 MHz VDRIVE above 4.75 V 15 MHz VDRIVE above 3.3 V 12.5 MHz VDRIVE above 2.7 V 10 MHz VDRIVE above 2.3 V t18 Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid 18 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 35 ns VDRIVE = 2.3 V to 2.7 V t193 Data access time after SCLK rising edge 20 ns VDRIVE above 4.75 V 26 ns VDRIVE above 3.3 V 32 ns VDRIVE above 2.7 V 39 ns VDRIVE above 2.3 V t20 0.4 tSCLK ns SCLK low pulse width t21 0.4 tSCLK ns SCLK high pulse width t22 7 SCLK rising edge to DOUTA/DOUTB valid hold time t23 22 ns CS rising edge to DOUTA/DOUTB three-state enabled FRSTDATA OPERATION t24 Delay from CS falling edge until FRSTDATA three-state disabled 18 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V t25 ns Delay from CS falling edge until FRSTDATA high, serial mode 18 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V t26 Delay from RD falling edge to FRSTDATA high 19 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V

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Data Sheet AD7609 Rev. C | Page 9 of 36 Limit at TMIN, TMAX Parameter Min Typ Max Unit Description t27 Delay from RD falling edge to FRSTDATA low 22 ns VDRIVE = 3.3 V to 5.25 V 29 ns VDRIVE = 2.3 V to 2.7 V t28 Delay from 18th SCLK falling edge to FRSTDATA low 20 ns VDRIVE = 3.3 V to 5.25 V 27 ns VDRIVE = 2.3 V to 2.7 V t29 29 ns Delay from CS rising edge until FRSTDATA three-state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (30% to 70% of VDD) and timed from a voltage level of 1.6 V. 2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets. 3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins. Timing Diagrams tCYCLE t3 t5 t2 t4 t1 t7 tRESET tCONV CONVST A/ CONVST B CONVST A/ CONVST B BUSY CS RESET 09 76 0- 00 2 Figure 2. CONVST x Timing—Reading After a Conversion tCYCLE t3 t5 t6 t2 t1 tCONV CONVST A/ CONVST B CONVST A/ CONVST B BUSY CS t7 tRESET RESET 09 76 0- 00 3 Figure 3. CONVST x Timing—Reading During a Conversion DATA: DB[15:0] FRSTDATA CS RD INVALID V1 [17:2] V1 [1:0] V2 [17:2] V8 [17:2] V8 [1:0] V2 [1:0] t10t8 t13 t24 t26 t27 t14 t11 t9 t16 t17 t29 t15 09 76 0- 00 4 Figure 4. Parallel Mode Separate CS and RD Pulses

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May 25, 2020

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May 24, 2020

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I have always get a fast response from Heisener with my orders. As a small business owner I greatly appreciate that I can order as little as 1 item as opposed to other companies who require you place a larger minimum order.

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