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AD7683ARMZRL7

hot AD7683ARMZRL7

AD7683ARMZRL7

For Reference Only

Part Number AD7683ARMZRL7
Manufacturer Analog Devices Inc.
Description IC ADC 16BIT SAR 100KSPS 8MSOP
Datasheet AD7683ARMZRL7 Datasheet
Package 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
In Stock 471 piece(s)
Unit Price $ 8.0464 *
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AD7683ARMZRL7

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AD7683ARMZRL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7683ARMZRL7 Datasheet
Package8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
SeriesPulSAR?
Number of Bits16
Sampling Rate (Per Second)100k
Number of Inputs1
Input TypePseudo-Differential
Data InterfaceSPI, DSP
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeExternal
Voltage - Supply, Analog2.7 V ~ 5.5 V
Voltage - Supply, Digital2.7 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C
Package / Case8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Supplier Device Package8-MSOP

AD7683ARMZRL7 Datasheet

Page 1

Page 2

16-Bit, 100 kSPS, Single-Ended PulSAR ADC in MSOP/QFN Data Sheet AD7683 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 16-bit resolution with no missing codes Throughput: 100 kSPS INL: ±1 LSB typical, ±3 LSB maximum Pseudo differential analog input range 0 V to VREF with VREF up to VDD Single-supply operation: 2.7 V to 5.5 V Serial interface SPI/QSPI/MICROWIRE/DSP compatible Power dissipation: 4 mW @ 5 V, 1.5 mW @ 2.7 V, 150 μW @ 2.7 V/10 kSPS Standby current: 1 nA 8-lead packages: MSOP 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) Improved second source to ADS8320 and ADS8325 APPLICATIONS Battery-powered equipment Data acquisition Instrumentation Medical instruments Process control APPLICATION DIAGRAM AD7683 REF GND VDD +IN –IN DCLOCK DOUT CS 3-WIRE SPI INTERFACE 0.5V TO VDD 2.7V TO 5.5V 0V TO VREF 04 30 1- 00 1 Figure 1. Table 1. MSOP, QFN (LFCSP)/SOT-23, 14-/16-/18-Bit PulSAR ADC Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver 18-Bit True Differential AD7691 AD7690 AD7982 AD7984 ADA4941-1 ADA4841-1 16-Bit True Differential AD7684 AD7687 AD7688 AD7693 ADA4941-1 ADA4841-1 16-Bit Pseudo Differential AD7680 AD7683 AD7685 AD7694 AD7686 AD7980 ADA4841-1 14-Bit Pseudo Differential AD7940 AD7942 AD7946 ADA4841-1 GENERAL DESCRIPTION The AD7683 is a 16-bit, charge redistribution, successive approximation, PulSAR® analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.7 V and 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes (B grade), an internal conversion clock, and a serial, SPI-compatible interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CS falling edge, it samples an analog input, +IN, between 0 V to REF with respect to a ground sense, –IN. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput. The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN (LFCSP) package, with an operating temperature specified from −40°C to +85°C.

Page 3

AD7683 Data Sheet Rev. B | Page 2 of 16 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Application Diagram ........................................................................ 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications ..................................................................................... 3  Timing Specifications .................................................................. 5  Absolute Maximum Ratings ............................................................ 6  Thermal Resistance ...................................................................... 6  ESD Caution .................................................................................. 6  Pin Configurations and Function Descriptions ........................... 7  Terminology ...................................................................................... 8  Typical Performance Characteristics ............................................. 9  Applications Information .............................................................. 12  Circuit Information .................................................................... 12  Converter Operation .................................................................. 12  Transfer Functions ..................................................................... 12  Typical Connection Diagram ................................................... 13  Analog Input ............................................................................... 13  Driver Amplifier Choice ........................................................... 13  Voltage Reference Input ............................................................ 14  Power Supply ............................................................................... 14  Digital Interface .......................................................................... 14  Layout .......................................................................................... 14  Evaluating the AD7683 Performance ...................................... 14  Outline Dimensions ....................................................................... 15  Ordering Guide .......................................................................... 16  REVISION HISTORY 2/16—Rev. A to Rev. B Changes to Table 1 ............................................................................ 1 Added Figure 7 and Table 9; Renumbered Sequentially ............. 7 Changes to Table 10 ........................................................................ 13 Changes to Digital Interface Section ............................................ 14 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 2/08—Rev. 0 to Rev. A Change to Title .................................................................................. 1 Moved Figure 3, Figure 4, and Figure 5 ......................................... 5 Changes to Figure 4 .......................................................................... 5 Moved Figure 17 and Figure 18 .................................................... 11 Changes to Figure 22 ...................................................................... 13 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 9/04—Initial Version: Revision 0

Page 4

Data Sheet AD7683 Rev. B | Page 3 of 16 SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted. Table 2. Parameter Conditions AD7683 All Grades Unit Min Typ Max RESOLUTION 16 Bits ANALOG INPUT Voltage Range +IN − (–IN) 0 VREF V Absolute Input Voltage +IN −0.1 VDD + 0.1 V −IN −0.1 0.1 V Analog Input CMRR fIN = 100 kHz 65 dB Leakage Current at 25°C Acquisition phase 1 nA Input Impedance See the Analog Input section THROUGHPUT SPEED Complete Cycle 10 µs Throughput Rate 0 100 kSPS DCLOCK Frequency 0 2.9 MHz REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 100 kSPS, V+IN − V−IN = VREF/2 = 2.5 V 50 µA DIGITAL INPUTS Logic Levels VIL −0.3 0.3 × VDD V VIH 0.7 × VDD VDD + 0.3 V IIL −1 +1 µA IIH −1 +1 µA Input Capacitance 5 pF DIGITAL OUTPUTS Data Format Serial, 16 bits straight binary VOH ISOURCE = −500 µA VDD − 0.3 V VOL ISINK = +500 µA 0.4 V POWER SUPPLIES VDD Specified performance 2.7 5.5 V VDD Range1 2.0 5.5 V Operating Current 100 kSPS throughput VDD VDD = 5 V 800 µA VDD = 2.7 V 560 µA Standby Current2, 3 VDD = 5 V, 25°C 1 50 nA Power Dissipation VDD = 5 V 4 6 mW VDD = 2.7 V 1.5 mW VDD = 2.7 V, 10 kSPS throughput2 150 µW TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 See the Typical Performance Characteristics section for more information. 2 With all digital inputs forced to VDD or GND, as required. 3 During acquisition phase.

Page 5

AD7683 Data Sheet Rev. B | Page 4 of 16 VDD = 5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted. Table 3. Parameter Conditions A Grade B Grade Unit Min Typ Max Min Typ Max ACCURACY No Missing Codes 15 16 Bits Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB Transition Noise 0.5 0.5 LSB Gain Error1, TMIN to TMAX ±2 ±24 ±2 ±15 LSB Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C Offset Error1, TMIN to TMAX ±0.7 ±1.6 ±0.4 ±1.6 mV Offset Temperature Drift ±0.3 ±0.3 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 LSB AC ACCURACY Signal-to-Noise fIN = 1 kHz 90 88 91 dB2 Spurious-Free Dynamic Range fIN = 1 kHz −100 −108 dB Total Harmonic Distortion fIN = 1 kHz −100 −106 dB Signal-to-(Noise + Distortion) fIN = 1 kHz 90 88 91 dB Effective Number of Bits fIN = 1 kHz 14.7 14.8 Bits 1 See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference. 2 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. VDD = 2.7 V; VREF = 2.5V; TA = –40°C to +85°C, unless otherwise noted. Table 4. A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit ACCURACY No Missing Codes 15 16 Bits Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB Transition Noise 0.85 0.85 LSB Gain Error1, TMIN to TMAX ±2 ±30 ±2 ±15 LSB Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C Offset Error1, TMIN to TMAX ±0.7 ±3.5 ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ±0.3 ppm/°C Power Supply Sensitivity VDD = 2.7 V ±5% ±0.05 ±0.05 LSB AC ACCURACY Signal-to-Noise fIN = 1 kHz 85 86 dB2 Spurious-Free Dynamic Range fIN = 1 kHz −96 −100 dB Total Harmonic Distortion fIN = 1 kHz −94 −98 dB Signal-to-(Noise + Distortion) fIN = 1 kHz 85 86 dB Effective Number of Bits fIN = 1 kHz 13.8 14 Bits 1 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 2 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

Page 6

Data Sheet AD7683 Rev. B | Page 5 of 16 TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted. Table 5. Parameter Symbol Min Typ Max Unit Throughput Rate tCYC 100 kHz CS Falling to DCLOCK Low tCSD 0 μs CS Falling to DCLOCK Rising tSUCS 20 ns DCLOCK Falling to Data Remains Valid tHDO 5 16 ns CS Rising Edge to DOUT High Impedance tDIS 14 100 ns DCLOCK Falling to Data Valid tEN 16 50 ns Acquisition Time tACQ 400 ns DOUT Fall Time tF 11 25 ns DOUT Rise Time tR 11 25 ns Timing and Circuit Diagrams 04 30 1- 00 2 DOUT DCLOCK COMPLETE CYCLE POWER DOWN CS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) HIGH-Z 0 HIGH-Z tACQ tDIS 0 1 4 5 tHDOtENtCSD tSUCS tCYC NOTES 1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES. DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING. Figure 2. Serial Interface Timing 04 30 1- 00 3 500µA IOL 500µA IOH 1.4VTO DOUT CL 100pF Figure 3. Load Circuit for Digital Interface Timing 0.8V 2V 2V 0.8V0.8V 2V tEN tEN 04 30 1- 00 4 Figure 4. Voltage Reference Levels for Timing 04 30 1- 00 6 DOUT 90% 10% tR tF Figure 5. DOUT Rise and Fall Timing

Page 7

AD7683 Data Sheet Rev. B | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Analog Inputs +IN1, –IN1 GND − 0.3 V to VDD + 0.3 V or ±130 mA REF GND − 0.3 V to VDD + 0.3 V Supply Voltages VDD to GND −0.3 V to +6 V Digital Inputs to GND −0.3 V to VDD + 0.3 V Digital Outputs to GND −0.3 V to VDD + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Lead Temperature Range JEDEC J-STD-20 Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 See the Analog Input section. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Table 7. Thermal Resistance Package Type θJA θJC Unit 8-Lead MSOP 200 44 °C/W ESD CAUTION

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Data Sheet AD7683 Rev. B | Page 7 of 16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 04 30 1- 00 5 REF 1 +IN 2 –IN 3 GND 4 VDD8 DCLOCK7 DOUT6 CS5 AD7683 TOP VIEW (Not to Scale) Figure 6. 8-Lead MSOP Pin Configuration Table 8. 8-Lead MSOP Pin Function Descriptions Pin No. Mnemonic Type1 Function 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the REF pin closely to the GND pin with a ceramic capacitor of a few μF. 2 +IN AI Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V to VREF. 3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground. 4 GND P Power Supply Ground. 5 CS DI Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as soon as the conversion is completed. It also enables DOUT. When high, DOUT is high impedance. 6 DOUT DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK. 7 DCLOCK DI Serial Data Clock Input. 8 VDD P Power Supply. 1 AI = analog input; DI = digital input; DO = digital output; and P = power. 04 30 1- 10 7 3–IN 4GND 1REF 2+IN 6 DOUT 5 CS NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET SPECIFIED ELECTRICAL PERFORMANCE. 8 VDD 7 DCLOCKAD7683 TOP VIEW (Not to Scale) Figure 7. 8-Lead QFN (LFCSP) Pin Configuration Table 9. 8-Lead QFN (LFCSP) Pin Function Descriptions Pin No. Mnemonic Type1 Function 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the REF pin closely to the GND pin with a ceramic capacitor of a few μF. 2 +IN AI Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V to VREF. 3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground. 4 GND P Power Supply Ground. 5 CS DI Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as soon as the conversion is completed. It also enables DOUT. When high, DOUT is high impedance. 6 DOUT DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK. 7 DCLOCK DI Serial Data Clock Input. 8 VDD P Power Supply. EPAD Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet specified electrical performance. 1 AI = analog input; DI = digital input; DO = digital output; and P = power.

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AD7683 Data Sheet Rev. B | Page 8 of 16 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level ½ LSB above analog ground (38.1 µV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111...10 to 111...11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD (as represented by S/(N+D)) by the following formula and is expressed in bits: [ ]( ) 02.6/76.1/ −+= dBDNSENOB Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Aperture Delay Aperture delay is a measure of the acquisition performance and is the time between the falling edge of the CS input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.

Page 10

Data Sheet AD7683 Rev. B | Page 9 of 16 TYPICAL PERFORMANCE CHARACTERISTICS 3 2 1 0 –1 –2 –3 0 16384 32768 49152 65536 04 30 1- 01 2 CODE IN L ( L S B ) POSITIVE INL = +0.43LSB NEGATIVE INL = –0.97LSB Figure 8. Integral Nonlinearity vs. Code 7000 6000 5000 4000 3000 2000 1000 0 79FD 79FE 79FF 7A00 7A01 7A02 7A03 7A04 7A05 7A06 7A07 7A08 04 30 1- 00 9 CODE IN HEX C O U N T S VDD = REF = 2.5V 0 0 1 4604 130 0 0 2755 25440 50 62564 35528 Figure 9. Histogram of a DC Input at the Code Center 0 –180 –160 –140 –120 –100 –80 –60 –40 –20 0 10 20 30 40 50 04 30 1- 00 8 FREQUENCY (kHz) A M P L IT U D E ( d B O F F U LL S C A L E ) 16384 POINT FFT VDD = REF = 5V fS = 100kSPS fIN = 20.43kHz SNR = 92.7dB THD = –105.7dB SFDR = –106.4dB Figure 10. FFT Plot 3 2 1 0 –1 –2 –3 0 16384 32768 49152 65536 04 30 1- 01 1 CODE D N L ( L S B ) POSITIVE DNL = +0.43LSB NEGATIVE DNL = –0.41LSB Figure 11. Differential Nonlinearity vs. Code 120000 100000 80000 60000 40000 20000 0 7A0E 7A0F 7A10 7A11 7A12 7A13 7A14 7A15 7A16 04 30 1- 01 0 CODE IN HEX C O U N T S 0 0 6 0 0 102287 1361915152 8 VDD = REF = 5V Figure 12. Histogram of a DC Input at the Code Center 0 –180 –160 –140 –120 –100 –80 –60 –40 –20 0 10 20 30 40 50 04 30 1- 00 7 FREQUENCY (kHz) A M P L IT U D E ( d B O F F U LL S C A L E ) 16384 POINT FFT VDD = REF = 2.5V fS = 100kSPS fIN = 20.43kHz SNR = 88.7dB THD = –102.6dB SFDR = –104.6dB Figure 13. FFT Plot

AD7683ARMZRL7 Reviews

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Yah*****Dixit

August 28, 2019

Components all tested within limits of specifications. Components came packaged in an easy to identify resealable bag and will work well for my projects.

Bray*****Lall

August 23, 2019

Serves its purpose. All that's needed.

Ken*****Jain

July 15, 2019

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June 12, 2019

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June 8, 2019

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May 31, 2019

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April 7, 2019

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March 19, 2019

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Kail*****olanki

March 7, 2019

Parts received and tested, all can work, thank you

Bray*****Bala

March 6, 2019

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