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AD7685CCPZRL7

hot AD7685CCPZRL7

AD7685CCPZRL7

For Reference Only

Part Number AD7685CCPZRL7
Manufacturer Analog Devices Inc.
Description IC ADC 16BIT SAR 250KSPS 10LFCSP
Datasheet AD7685CCPZRL7 Datasheet
Package 10-WFDFN Exposed Pad, CSP
In Stock 281 piece(s)
Unit Price $ 13.1431 *
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AD7685CCPZRL7

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AD7685CCPZRL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7685CCPZRL7 Datasheet
Package10-WFDFN Exposed Pad, CSP
SeriesPulSAR?
Number of Bits16
Sampling Rate (Per Second)250k
Number of Inputs1
Input TypePseudo-Differential
Data InterfaceSPI, DSP
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeExternal
Voltage - Supply, Analog2.3 V ~ 5.5 V
Voltage - Supply, Digital2.3 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C
Package / Case10-WFDFN Exposed Pad, CSP
Supplier Device Package10-LFCSP-WD (3x3)

AD7685CCPZRL7 Datasheet

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16-Bit, 250 kSPS PulSAR ADC in MSOP Data Sheet AD7685 FEATURES 16-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR) SINAD: 93.5 dB at 20 kHz THD: −110 dB at 20 kHz Pseudo differential analog input range 0 V to VREF with VREF up to VDD No pipeline delay Single-supply operation 2.3 V to 5.5 V with 1.8 V to 5 V logic interface Proprietary serial interface: SPI-/QSPI™-/MICROWIRE™-/DSP- compatible Daisy-chain multiple ADCs, BUSY indicator Power dissipation 1.4 µW at 2.5 V/100 SPS 1.35 mW at 2.5 V/100 kSPS, 4 mW at 5 V/100 kSPS Standby current: 1 nA 10-lead package: MSOP (MSOP-8 size) and 3 mm × 3 mm LFCSP (SOT-23 size) Pin-for-pin-compatible with 10-lead MSOP/PulSAR® ADCs APPLICATIONS Battery-powered equipment Medical instruments Mobile communications Personal digital assistants (PDAs) Data acquisition Instrumentation Process controls 02 96 8- 00 5 CODE 655360 16384 32768 49152 IN L (L SB ) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 POSITIVE INL = +0.33LSB NEGATIVE INL = –0.50LSB Figure 1. Integral Nonlinearity vs. Code TYPICAL APPLICATION CIRCUIT AD7685 REF GND VDD IN+ IN– VIO SDI SCK SDO CNV 1.8V TO VDD 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS) 0.5V TO VDD 2.5V TO 5V 0 TO VREF 02 96 8- 00 1 Figure 2. Table 1. MSOP, LFCSP/SOT-23 14-/16-/18-Bit PulSAR ADC Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS 1000 kSPS ADC Driver 18-Bit True AD7691 AD7690 AD7982 ADA4941 Differential AD7982 ADA4841 16-Bit True AD7684 AD7687 AD7688 ADA4941 Differential AD7693 ADA4841 16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841 Differential AD7683 AD7694 14-Bit Pseudo AD7940 AD7942 AD7946 ADA4841 Differential GENERAL DESCRIPTION The AD76851 is a 16-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Power dissipation scales linearly with throughput. The SPI-compatible serial interface also features the ability, using the SDI input, to daisy chain several ADCs on a single 3-wire bus or provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply VIO. The AD7685 is housed in a 10-lead MSOP or a 10-lead LFCSP with operation specified from −40°C to +85°C. 1 Protected by U.S. Patent 6,703,961. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

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AD7685 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuit ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications ....................................................................... 5 Absolute Maximum Ratings ............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Terminology ...................................................................................... 9 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 13 Circuit Information .................................................................... 13 Converter Operation .................................................................. 13 Typical Connection Diagram.................................................... 14 Analog Inputs .............................................................................. 15 Driver Amplifier Choice ........................................................... 16 Voltage Reference Input ............................................................ 16 Power Supply ............................................................................... 16 Supplying the ADC from the Reference .................................. 17 Digital Interface .......................................................................... 17 CS Mode 3-Wire, No BUSY Indicator ..................................... 18 CS Mode 3-Wire with BUSY Indicator ................................... 19 CS Mode 4-Wire, No BUSY Indicator ..................................... 20 CS Mode 4-Wire with BUSY Indicator ................................... 21 Chain Mode, No BUSY Indicator ............................................ 22 Chain Mode with BUSY Indicator ........................................... 23 Application Hints ........................................................................... 24 Layout .......................................................................................... 24 Evaluating the Performance of the AD7685 ............................... 24 True 16-Bit Isolated Application Example .............................. 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27 REVISION HISTORY 7/14—Rev. C to Rev. D Deleted QFN .................................................................. Throughout Changed Application Diagram to Typical Application Circuit ................................................................................................ 1 Change to Features Section ............................................................. 1 Added Patent Note, Note 1 .............................................................. 1 Changes to Evaluating the Performance of the AD7685 Section .............................................................................................. 24 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 8/11—Rev. B to Rev. C Changes to Figure 6 and Table 7 ..................................................... 8 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 3/07—Rev. A to Rev. B Changes to Features and Table 1..................................................... 1 Changes to Table 3 ............................................................................ 4 Moved Figure 3 and Figure 4 to Page ............................................. 6 Inserted Figure 6; Renumbered Sequentially ................................ 8 Changes to Figure 13 and Figure 14 ............................................. 11 Changes to Figure 27 ...................................................................... 14 Changes to Table 9 .......................................................................... 16 Changes to Figure 32 ...................................................................... 17 Changes to Figure 43 ...................................................................... 22 Changes to Figure 45 ...................................................................... 23 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 12/04—Rev. 0 to Rev. A Changes to Specifications ................................................................. 3 Changes to Figure 17 Captions ..................................................... 11 Changes to Power Supply Section ................................................ 17 Changes to Digital Interface Section ........................................... 18 Changes to CS Mode 4-Wire No Busy Indicator Section ......... 21 Changes to CS Mode 4-Wire with Busy Indicator Section ....... 22 Changes to Chain Mode, No Busy Indicator Section ................ 23 Changes to Chain Mode with Busy Indicator Section .............. 24 Added True 16-Bit Isolated Application Example Section ....... 26 Added Figure 47 ............................................................................. 26 Changes to Ordering Guide .......................................................... 28 4/04—Revision 0: Initial Revision Rev. D | Page 2 of 28

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Data Sheet AD7685 SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 2. A Grade B Grade C Grade Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 16 16 16 Bits ANALOG INPUT Voltage Range IN+ − IN− 0 VREF 0 VREF 0 VREF V Absolute Input Voltage IN+ −0.1 VDD + 0.1 −0.1 VDD + 0.1 −0.1 VDD + 0.1 V IN− −0.1 +0.1 −0.1 +0.1 −0.1 +0.1 V Analog Input CMRR fIN = 250 kHz 65 65 65 dB Leakage Current at 25°C Acquisition phase 1 1 1 nA Input Impedance See the Analog Inputs section See the Analog Inputs section See the Analog Inputs section ACCURACY No Missing Codes 15 16 16 Bits Differential Linearity Error −1 ±0.7 −1 ±0.5 +1.5 LSB1 Integral Linearity Error −6 +6 −3 ±1 +3 −2 ±0.6 +2 LSB Transition Noise REF = VDD = 5 V 0.5 0.5 0.45 LSB Gain Error2, TMIN to TMAX ±2 ±30 ±2 ±30 ±2 ±15 LSB Gain Error Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C Offset Error2, TMIN to TMAX VDD = 4.5 V to 5.5 V ±0.1 ±1.6 ±0.1 ±1.6 ±0.1 ±1.6 mV VDD = 2.3 V to 4.5 V ±0.7 ±3.5 ±0.7 ±3.5 ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 ±0.05 LSB THROUGHPUT Conversion Rate VDD = 4.5 V to 5.5 V 0 250 0 250 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 0 200 0 200 kSPS Transient Response Full-scale step 1.8 1.8 1.8 µs AC ACCURACY Signal-to-Noise Ratio fIN = 20 kHz, VREF = 5 V 90 90 92 91.5 93.5 dB3 fIN = 20 kHz, VREF = 2.5 V 86 86 88 87.5 88.5 dB Spurious-Free Dynamic Range fIN = 20 kHz −100 −106 −110 dB Total Harmonic Distortion fIN = 20 kHz −100 −106 −110 dB Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 5 V 89 90 92 91.5 93.5 dB fIN = 20 kHz, VREF = 5 V, −60 dB input 32 33.5 dB fIN = 20 kHz, VREF = 2.5 V 86 85.5 87.5 87 88.5 dB Intermodulation Distortion4 −110 −115 dB 1 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV. 2 See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full scale. Rev. D | Page 3 of 28

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AD7685 Data Sheet VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 250 kSPS, REF = 5 V 50 µA SAMPLING DYNAMICS −3 dB Input Bandwidth 2 MHz Aperture Delay VDD = 5 V 2.5 ns DIGITAL INPUTS Logic Levels VIL –0.3 0.3 × VIO V VIH 0.7 × VIO VIO + 0.3 V IIL −1 +1 µA IIH −1 +1 µA DIGITAL OUTPUTS Data Format Serial 16 bits straight binary Pipeline Delay Conversion results available immediately after completed conversion VOL ISINK = +500 µA 0.4 V VOH ISOURCE = −500 µA VIO − 0.3 V POWER SUPPLIES VDD Specified performance 2.3 5.5 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V Standby Current1, 2 VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.4 µW VDD = 2.5 V, 100 kSPS throughput 1.35 2.4 mW VDD = 2.5 V, 200 kSPS throughput 2.7 4.8 mW VDD = 5 V, 100 kSPS throughput 4 6 mW VDD = 5 V, 250 kSPS throughput 10 15 mW TEMPERATURE RANGE3 Specified Performance TMIN to TMAX −40 +85 °C 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact sales for extended temperature range. Rev. D | Page 4 of 28

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Data Sheet AD7685 TIMING SPECIFICATIONS −40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. Table 4. VDD = 4.5 V to 5.5 V1 Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge To Data Available tCONV 0.5 2.2 µs Acquisition Time tACQ 1.8 µs Time Between Conversions tCYC 4 µs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 15 ns SCK Period (Chain Mode) tSCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time tSCKL 7 ns SCK High Time tSCKH 7 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 3 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns 1 See Figure 3 and Figure 4 for load conditions. Rev. D | Page 5 of 28

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AD7685 Data Sheet −40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. Table 5. VDD = 2.3V to 4.5 V1 Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 0.7 3.2 µs Acquisition Time tACQ 1.8 µs Time Between Conversions tCYC 5 µs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns VIO Above 2.3 V 40 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 5 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36 ns 1 See Figure 3 and Figure 4 for load conditions. 500µA IOL 500µA IOH 1.4VTO SDO CL 50pF 02 96 8- 00 2 Figure 3. Load Circuit for Digital Interface Timing 30% VIO 70% VIO 2V OR VIO – 0.5V1 0.8V OR 0.5V20.8V OR 0.5V2 2V OR VIO – 0.5V1 tDELAY tDELAY 02 96 8- 00 3NOTES 1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 4. Voltage Levels for Timing Rev. D | Page 6 of 28

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Data Sheet AD7685 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Analog Inputs IN+1, IN−1, REF GND − 0.3 V to VDD + 0.3 V or ±130 mA Supply Voltages VDD, VIO to GND −0.3 V to +7 V VDD to VIO ±7 V Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 200°C/W (MSOP-10) θJC Thermal Impedance 44°C/W (MSOP-10) Lead Temperature Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 See the Analog Inputs section. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. D | Page 7 of 28

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AD7685 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 VDD 2 IN+ 3 IN– 4 GND 5 VIO10 SDI9 SCK8 SDO7 CNV6 AD7685 TOP VIEW (Not to Scale) 02 96 8- 00 4 Figure 5. 10-Lead MSOP Pin Configuration 1REF 2VDD 3IN+ 4IN– 5GND 10 VIO 9 SDI 8 SCK 7 SDO 6 CNV TOP VIEW (Not to Scale) AD7685 02 96 8- 00 5NOTES1. EXPOSED PAD CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. Figure 6. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No Mnemonic Type1 Description 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 µF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to VREF. 4 IN− AI Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). EPAD N/A Exposed Pad. Exposed pad connected to GND. This connection is not required to meet the electrical performances. 1AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. D | Page 8 of 28

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Data Sheet AD7685 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 26). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level ½ LSB above analog ground (38.1 µV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by ENOB = (SINADdB − 1.76)/6.02 and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion), SINAD SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Aperture Delay Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response The time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. D | Page 9 of 28

AD7685CCPZRL7 Reviews

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Nadia*****kburn

November 3, 2019

Excellent service over extended period of time. Incredibly fast shipping, never any errors. Couldn't be more pleased.

Evel*****hopra

August 23, 2019

Very good connector, easy to realise and with Low price

Mai*****urns

August 10, 2019

Very Quick,no problems - Thank you.

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July 26, 2019

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June 12, 2019

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June 4, 2019

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May 1, 2019

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April 27, 2019

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February 16, 2019

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January 30, 2019

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hotAD7685CCPZRL7 AD7612BSTZ-RL Analog Devices Inc., IC ADC 16BIT 750KSPS SAR 48-LQFP, 48-LQFP, PulSAR? View
hotAD7685CCPZRL7 AD7625BCPZRL7 Analog Devices Inc., IC ADC 16BIT 6MSPS SAR 32LFCSP, 32-WFQFN Exposed Pad, CSP, PulSAR? View
hotAD7685CCPZRL7 AD7610BCPZ-RL Analog Devices Inc., IC ADC 16BIT 250KSPS 48-LFCSP, 48-VFQFN Exposed Pad, CSP, PulSAR? View
hotAD7685CCPZRL7 AD7667ACPZRL Analog Devices Inc., IC ADC 16BIT UNIPOLAR 48LFCSP, 48-VFQFN Exposed Pad, CSP, PulSAR? View

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