Page 2
16-Bit, 250 kSPS PulSAR® ADC in MSOP
Data Sheet AD7694
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
16-bit resolution with no missing codes
Throughput: 250 kSPS at 5 V
INL: ±4 LSB max
S/(N + D): 92 dB at 20 kHz
THD: –106 dB at 20 kHz
Pseudo-differential analog input range:
0 V to VREF with VREF up to VDD
No pipeline delay
Single-supply operation: 2.7 V or 5 V
Proprietary serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible1
Supply Current: 540 μA at 2.7 V/100 kSPS,
800 μA at 5 V/100 kSPS
Standby current: 1 nA
8-lead MSOP package
Improved second source to LTC1864 and LTC1864L
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
GENERAL DESCRIPTION
The AD7694 is a 16-bit, charge redistribution, successive
approximation, PulSAR analog-to-digital converter (ADC) that
operates from a single power supply, VDD, between 2.7 V to
5.25 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes (B grade), an internal conversion
clock, and a serial, SPI-compatible interface port. The part also
contains a low noise, wide bandwidth, short aperture delay
track-and-hold circuit. On the CNV rising edge, it samples an
analog input, IN+, between 0 V to REF with respect to a ground
sense, IN−. The reference voltage, REF, is applied externally and
can be set up to the supply voltage.
Its power scales linearly with throughput.
The AD7694 is housed in an 8-lead MSOP package with an
operating temperature specified from −40°C to +85°C.
APPLICATION DIAGRAM
AD7694
REF
GND
VDD
IN+
IN–
SCK
SDO
CNV
3-WIRE SPI
INTERFACE
1V TO VDD 2.5V TO 5V
0 TO VREF
05
00
3-
00
1
Figure 1.
Table 1. MSOP, LFCSP (QFN)/SOT-23, 16-Bit PulSAR ADC
Type 100 kSPS 250 kSPS 500 kSPS
True Differential AD7684 AD7687 AD7688
Pseudo AD7683 AD7685 AD7686
Differential/Unipolar AD7694
Unipolar AD7680
1 Protected by U.S. Patent 6,703,961.
Page 3
AD7694 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Application Diagram ........................................................................ 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications ....................................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Application Information ................................................................ 12
Circuit Information .................................................................... 12
Converter Operation .................................................................. 12
Transfer Functions ..................................................................... 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 13
Driver Amplifier Choice ........................................................... 13
Voltage Reference Input ............................................................ 14
Power Supply ............................................................................... 14
Supplying the ADC from the Reference .................................. 14
Digital Interface .......................................................................... 15
Layout .......................................................................................... 15
Evaluating the AD7694 Performance ...................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
6/14—Rev. A to Rev. B
Added Patent Footnote .................................................................... 1
Changes to Evaluating the AD7694 Performance Section ........ 15
Changes to Ordering Guide .......................................................... 16
5/05—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Digital Interface Section ............................................ 14
Changes to Figure 25 ...................................................................... 15
Changes to Evaluating the AD7694’s Performance Section ...... 15
7/04—Revision 0: Initial Version
Rev. B | Page 2 of 16
Page 4
Data Sheet AD7694
SPECIFICATIONS
VDD = 2.7 V to 5.25 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted.
Table 2.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
RESOLUTION 16 16 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 VREF 0 VREF V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 −0.1 VDD + 0.1 V
IN− −0.1 +0.1 −0.1 +0.1 V
Leakage Current at 25°C Acquisition phase 1 1 nA
Input Impedance See the Analog Input section
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 +6 −4 +4 LSB
Transition Noise REF = VDD = 5 V 0.5 0.5 LSB
Gain Error1, TMIN to TMAX ±2 ±30 ±2 ±15 LSB
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, TMIN to TMAX ±0.7 ±3.5 ±0.7 ±3.5 mV
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 LSB
THROUGHPUT
Conversion Rate VDD = 4.75 V to 5.25 V 0 250 0 250 kSPS
VDD = 2.7 V to 4.75 V 0 150 0 150 kSPS
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, VREF = 5 V 90 88 92 dB2
fIN = 20 kHz, VREF = 2.5 V 86 87 dB
Spurious-Free Dynamic Range fIN = 20 kHz −100 −106 dB
Total Harmonic Distortion fIN = 20 kHz −100 −106 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 5 V 89 88 92 dB
fIN = 20 kHz, VREF = 2.5 V 86 87 dB
1 See the Terminology section. These specifications include full temperature range variation, but do not include the error contribution from the external reference.
2 All specifications in dB refer to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. B | Page 3 of 16
Page 5
AD7694 Data Sheet
VDD = 2.7 V to 5.25 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 1 VDD V
Load Current 250 kSPS, VIN+ − VIN− = VREF/2 = 2.5 V 50 µA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 9 MHz
DIGITAL INPUTS
Logic Levels
VIL VDD = 4.75 V 0.8 V
VDD = 2.7 V 0.45 V
VIH VDD = 5.25 V 3.15 V
VDD = 3.3 V 1.9 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format Serial, 16 bits straight binary
Pipeline Delay Conversion results available immediately
after completed conversion
VOL ISINK = +500 µA 0.4 V
VOH ISOURCE = −500 µA VDD − 0.3 V
POWER SUPPLIES
VDD Specified performance 2.7 5.25 V
Operating Current
VDD VDD = 5 V, 100 kSPS throughput 0.8 1.2 mA
VDD = 2.7 V, 100 kSPS throughput 540 960 µA
Standby Current1, 2 VDD = 5 V, 25°C 1 50 nA
TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +85 °C
1 With all digital inputs forced to VDD or GND, as required.
2 During acquisition phase.
Rev. B | Page 4 of 16
Page 6
Data Sheet AD7694
TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V; TA = −40°C to +85°C, unless otherwise stated.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 3.2 µs
Time Between Conversions tCYC 4 µs
SCK Period tSCK 50 ns
SCK Low Time tSCKL 20 ns
SCK High Time tSCKH 20 ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data Valid Delay tDSDO 20 ns
CNV Low to SDO, D15 MSB Valid tEN 60 ns
CNV High to SDO High Impedance tDIS 60 ns
VDD = 2.7 V to 4.75 V; TA = −40°C to +85°C, unless otherwise stated.
Table 5.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 4.66 µs
Time Between Conversions tCYC 6.66 µs
SCK Period tSCK 125 ns
SCK Low Time tSCKL 50 ns
SCK High Time tSCKH 50 ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data Valid Delay tDSDO 50 ns
CNV Low to SDO, D15 MSB Valid tEN 120 ns
CNV High to SDO High Impedance tDIS 120 ns
Rev. B | Page 5 of 16
Page 7
AD7694 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
IN+1, IN−1 GND − 0.3 V to VDD + 0.3 V
or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD to GND −0.3 V to +7 V
Digital Inputs to GND −0.3 V to VDD + 0.3 V
Digital Outputs to GND −0.3 V to VDD + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-8)
θJC Thermal Impedance 44°C/W (MSOP-8)
Lead Temperature Range
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
05
00
3-
00
2
500µA IOL
500µA IOH
1.4VTO SDO
CL
50pF
Figure 2. Load Circuit for Digital Interface Timing
VIL
VIH
VOH
VOLVOL
VOH
tDELAY tDELAY
05
00
3-
00
3
Figure 3. Voltage Reference Levels for Timing
ESD CAUTION
Rev. B | Page 6 of 16
Page 8
Data Sheet AD7694
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05
00
3-
00
4
REF 1
IN+ 2
IN– 3
GND 4
VDD8
SCK7
SDO6
CNV5
AD7694
TOP VIEW
(Not to Scale)
Figure 4. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Function
1 REF AI Reference Input Voltage. The REF range is from 1 V to VDD. It is referred to the GND pin. This pin should be
decoupled closely to the pin with a ceramic capacitor of a few µF.
2 IN+ AI Analog Input. It is referred to in IN−. The voltage range, that is, the difference between IN+ and IN−, which
is 0 V to VREF.
3 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
4 GND P Power Supply Ground.
5 CNV DI Convert Input. On its leading edge, it initiates the conversions. It enables the SDO pin when low.
6 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
7 SCK DI Serial Data Clock Input. When CNV is low, the conversion result is shifted out by this clock.
8 VDD P Power Supply.
1AI = analog input; DI = digital input; DO = digital output; and P = power.
Rev. B | Page 7 of 16
Page 9
AD7694 Data Sheet
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale to positive full scale.
The point used as negative full scale occurs ½ LSB before the
first code transition. Positive full scale is defined as a level
1 ½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line
(see Figure 19).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111...10 to 111...11) should occur for
an analog voltage 1 ½ LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N + D) by
ENOB = (S/[N + D]dB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (S/[N + D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
the time between the rising edge of the CNV input and the time
the input signal is held for conversion.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function is applied.
Rev. B | Page 8 of 16
Page 10
Data Sheet AD7694
TYPICAL PERFORMANCE CHARACTERISTICS
4
–4
–3
–2
–1
0
1
2
3
0 3276816384 49152 65536
05
00
3-
00
5
CODE
IN
L
(L
SB
)
POSITIVE INL = +0.68 LSB
NEGATIVE INL = –1.14 LSB
Figure 5. Integral Nonlinearity vs. Code
12000
10000
8000
6000
4000
2000
0
24E0 24E1 24E2 24E3 24E4 24E5 24E6 24E7 24E8
05
00
3-
00
6
CODE IN HEX
C
O
U
N
TS
0 0 1 0 0
1250010003
0
108568 VDD = REF = 5V
Figure 6. Histogram of a DC Input at the Code Center
0
–180
–160
–140
–120
–100
–80
–60
–40
–20
0 20 40 60 80 100 120
05
00
3-
00
7
FREQUENCY (kHz)
A
M
PL
IT
U
D
E
(d
B
O
F
FU
LL
S
C
A
LE
)
16384 POINT FFT
VDD = REF = 5V
fS = 250kSPS
fIN = 20.43kHz
SNR = 92.5dB
THD = –109.9dB
SFDR = –111.0dB
Figure 7. FFT Plot
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0 3276816384 49152 65536
05
00
3-
00
8
CODE
D
N
L
(L
SB
)
POSITIVE DNL = +0.59 LSB
NEGATIVE DNL = –0.56 LSB
Figure 8. Differential Nonlinearity vs. Code
8000
7000
6000
5000
4000
3000
2000
1000
0
251B 251C 251D 251E 251F 2520 2521 2522 2523 2524 2525 2526
05
00
3-
00
9
CODE IN HEX
C
O
U
N
TS
VDD = REF = 2.5V
0 0 27
2808
50 1 0 0
28148
65487
2133
32418
Figure 9. Histogram of a DC Input at the Code Center
0
–180
–160
–140
–120
–100
–80
–60
–40
–20
0 10 20 30 40 50 60 70
05
00
3-
01
0
FREQUENCY (kHz)
A
M
PL
IT
U
D
E
(d
B
O
F
FU
LL
S
C
A
LE
)
16384 POINT FFT
VDD = REF = 2.5V
fS = 150kSPS
fIN = 20.43kHz
SNR = 88.5dB
THD = –102.7dB
SFDR = –105.1dB
Figure 10. FFT Plot
Rev. B | Page 9 of 16
