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AD7718BRZ

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AD7718BRZ

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Part Number AD7718BRZ
Manufacturer Analog Devices Inc.
Description IC ADC 24BIT R-R 8/10CH 28SOIC
Datasheet AD7718BRZ Datasheet
Package 28-SOIC (0.295", 7.50mm Width)
In Stock 312 piece(s)
Unit Price $ 11.7400 *
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 2 - Dec 7 (Choose Expedited Shipping)
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Part Number # AD7718BRZ (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7718BRZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7718BRZDatasheet
Package28-SOIC (0.295", 7.50mm Width)
Series-
Number of Bits24
Sampling Rate (Per Second)1.37k
Number of Inputs4/5, 8/10
Input TypeDifferential, Pseudo-Differential
Data InterfaceSPI, DSP
ConfigurationMUX-PGA-ADC
Ratio - S/H:ADC-
Number of A/D Converters1
ArchitectureSigma-Delta
Reference TypeExternal
Voltage - Supply, Analog2.7 V ~ 3.6 V, 5V
Voltage - Supply, Digital2.7 V ~ 3.6 V, 5V
FeaturesPGA
Operating Temperature-40°C ~ 85°C
Package / Case28-SOIC (0.295", 7.50mm Width)
Supplier Device Package28-SOIC
Mounting Type-

AD7718BRZ Datasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD7708/AD7718 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 8-/10-Channel, Low Voltage, Low Power, - ADCs FUNCTIONAL BLOCK DIAGRAM DVDD XTAL1 XTAL2 MUX POS BUF - ADC* AIN1 AIN2 AIN3 AIN4 PGA OSC AND PLL SERIAL INTERFACE AND CONTROL LOGIC DOUT DIN SCLK CS RDY RESET AVDD I/O PORT AVDD AD7708/AD7718 DGND P2 P1 REFIN2(+)/AIN9 REFIN1(+) REFIN2(–)/AIN10 REFIN1(–) AINCOM AIN5 AIN6 AIN7 AIN8 AGND *AD7708 16-BIT ADC *AD7718 24-BIT ADC REFIN(+) REFIN(–) NEG BUF FEATURES 8-/10-Channel, High Resolution - ADCs AD7708 Has 16-Bit Resolution AD7718 Has 24-Bit Resolution Factory-Calibrated Single Conversion Cycle Setting Programmable Gain Front End Simultaneous 50 Hz and 60 Hz Rejection VREF Select™ Allows Absolute and Ratiometric Measurement Capability Operation Can Be Optimized for Analog Performance (CHOP = 0) or Channel Throughput (CHOP = 1) INTERFACE 3-Wire Serial SPITM, QSPITM, MICROWIRETM, and DSP-Compatible Schmitt Trigger on SCLK POWER Specified for Single 3 V and 5 V Operation Normal: 1.28 mA Typ @ 3 V Power-Down: 30 A (32 kHz Crystal Running) On-Chip Functions Rail-to-Rail Input Buffer and PGA 2-Bit Digital I/O Port APPLICATIONS Industrial Process Control Instrumentation Pressure Transducers Portable Instrumentation Smart Transmitters SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp. VREF Select is a trademark of Analog Devices, Inc. GENERAL DESCRIPTION The AD7708/AD7718 are complete analog front-ends for low frequency measurement applications. The AD7718 contains a 24-bit Σ-∆ ADC with PGA and can be configured as 4/5 fully- differential input channels or 8/10 pseudo-differential input channels. Two pins on the device are configurable as analog inputs or reference inputs. The AD7708 is a 16-bit version of the AD7718. Input signal ranges from 20 mV to 2.56 V can be directly converted using these ADCs. Signals can be converted directly from a transducer without the need for signal conditioning. The device operates from a 32 kHz crystal with an on-board PLL generating the required internal operating frequency. The output data rate from the part is software programmable. The peak-to- peak resolution from the part varies with the programmed gain and output data rate. The part operates from a single 3 V or 5 V supply. When operating from 3 V supplies, the power dissipation for the part is 3.84 mW typ. Both parts are pin-for-pin compatible allowing an upgradable path from 16 to 24 bits without the need for hardware modifica- tions. The AD7708/AD7718 are housed in 28-lead SOIC and TSSOP packages.

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REV. 0–2– AD7708/AD7718 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 AD7718 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 3 AD7708 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 6 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 9 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 10 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . 15 Signal Chain Overview (CHOP Enabled, CHOP = 0) . . . 15 ADC NOISE PERFORMANCE CHOP ENABLED (CHOP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Chain Overview (CHOP Disabled CHOP = 1) . . . 19 ADC NOISE PERFORMANCE CHOP DISABLED (CHOP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Communications Register . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating Characteristics when Addressing the Mode and Control Registers . . . . . . . . . . . . . . . . . . . . . . . 28 ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 I/O Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ADC Offset Calibration Coefficient Registers . . . . . . . . . . . 31 ADC Gain Calibration Coefficient Register . . . . . . . . . . . . . 31 ID Register (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 User Nonprogrammable Test Registers . . . . . . . . . . . . . . . . 31 Configuring the AD7708/AD7718 . . . . . . . . . . . . . . . . . . . . 32 DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MICROCOMPUTER/MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AD7708/AD7718 to 68HC11 Interface . . . . . . . . . . . . . . . . 34 AD7708/AD7718-to-8051 Interface . . . . . . . . . . . . . . . . . . 35 AD7708/AD7718-to-ADSP-2103/ADSP-2105 Interface . . . 36 BASIC CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . 36 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Single-Ended Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chop Mode of Operation (CHOP = 0) . . . . . . . . . . . . . . . . 37 Nonchop Mode of Operation (CHOP = 1) . . . . . . . . . . . . . 38 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . 38 Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . . . 38 Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Programmable Logic Controllers . . . . . . . . . . . . . . . . . . . . . 41 Converting Single-Ended Inputs. . . . . . . . . . . . . . . . . . . . . 42 Combined Ratiometric and Absolute Value Measurement System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Optimizing Throughput while Maximizing 50 Hz and 60 Hz Rejection in a Multiplexed Data Acquisition System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44 TABLE OF CONTENTS

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REV. 0 –3– AD7708/AD7718 Parameter B Grade Unit Test Conditions AD7718 (CHOP DISABLED) Output Update Rate 16.06 Hz min CHOP = 1 1.365 kHz max No Missing Codes2 24 Bits min Resolution 13 Bits p-p ±20 mV Range, SF = 69 18 Bits p-p ±2.56 V Range, SF = 69 Output Noise and Update Rates See Tables in ADC Description Integral Nonlinearity ±10 ppm of FSR max 2 ppm Typical Offset Error3 Table VII µV typ Offset Error is in the order of the noise for the programmed gain and update rate following a calibration Offset Error Drift vs. Temp4 ±200 nV/°C typ Full-Scale Error3 ±10 µV typ Gain Drift vs. Temp4 ±0.5 ppm/°C typ Negative Full-Scale Error ±0.003 % FSR max ANALOG INPUTS Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and REFIN2. REFIN = REFIN(+) –REFIN(–) GAIN = 1 to 128 Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with AVDD – 100 mV V max NEGBUF = 1 Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0 AVDD + 30 mV V max Analog Input Current AIN1–AIN10 and AINCOM with NEGBUF = 1 DC Input Current2 ±1 nA max DC Bias Current Drift ±5 pA/°C typ AINCOM Input Current NEGBUF = 0 DC Input Current2 ±125 nA/V typ ±2.56 V Range DC Bias Current Drift ±2 pA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection @ DC 90 dB min 100 dB typ, Analog Input = 1 V, Input Range = ± 2.56 V 110 dB typ on ± 20 mV Range @ 50 Hz 100 dB typ 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB typ 60 Hz ± 1 Hz, SF Word = 68 REFERENCE INPUTS (REFIN1 AND REFIN2) REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and REFIN2 REFIN(+) to REFIN(–) Range2 1 V min AVDD V max REFIN Common-Mode Range AGND – 30 mV V min AVDD + 30 mV V max Reference DC Input Current 0.5 µA/V typ Reference DC Input Current Drift ±0.1 nA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection Input Range = ± 2.56 V @ DC 100 dB typ Analog Input = 1 V. Input Range = ± 2.56 V @ 50 Hz 100 dB typ @ 60 Hz 100 dB typ AD7718 SPECIFICATIONS1 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications TMIN to TMAX unless otherwise noted.)

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REV. 0–4– AD7718–SPECIFICATIONS1 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications TMIN to TMAX unless otherwise noted.) Parameter B Grade Unit Test Conditions AD7718 (CHOP ENABLED) Output Update Rate 5.4 Hz min CHOP = 0 105 Hz max No Missing Codes2 24 Bits min 20 Hz Update Rate Resolution 13 Bits p-p ± 20 mV Range, 20 Hz Update Rate 18 Bits p-p ± 2.56 V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables in ADC Description Integral Nonlinearity ± 10 ppm of FSR max 2 ppm Typical Offset Error3 ± 3 µV typ Offset Error Drift vs. Temp4 10 nV/°C typ Full-Scale Error3 ± 10 µV/°C typ Gain Drift vs. Temp4 ± 0.5 ppm/°C typ ANALOG INPUTS Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and REFIN2. REFIN = REFIN(+) REFIN(–) GAIN = 1 to 128 Range Matching ± 2 µV typ Analog Input = 18 mV Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with AVDD – 100 mV V max NEGBUF = 1 Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0 AVDD + 30 mV V max Analog Input Current AIN1–AIN10 and AINCOM with NEGBUF = 1 DC Input Current2 ± 1 nA max DC Input Current Drift ± 5 pA/°C typ AINCOM Input Current NEGBUF = 0 DC Input Current2 ± 125 nA/V typ ± 2.56 V Range DC Bias Current Drift ± 2 pA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection @ DC 90 dB min 100 dB typ, Analog Input = 1 V, Input Range = ±2.56 V 110 dB typ on ± 20 mV Range @ 50 Hz2 100 dB min 50 Hz ± 1 Hz, 20 Hz Update Rate @ 60 Hz2 100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate REFERENCE INPUTS (REFIN1 AND REFIN2) REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and REFIN2 REFIN(+) to REFIN(–) Range2 1 V min AVDD V max REFIN Common-Mode Range AGND – 30 mV V min AVDD + 30 mV V max Reference DC Input Current2 ± 0.5 µA/V typ Reference DC Input Current Drift ± 0.01 nA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection2 Input Range = ± 2.56 V @ DC 110 dB typ Analog Input = 1 V @ 50 Hz 110 dB typ 50 Hz ± 1 Hz, 20 Hz Update Rate @ 60 Hz 110 dB typ 60 Hz ± 1 Hz, 20 Hz Update Rate LOGIC INPUTS5 All Inputs Except SCLK and XTAL12 VINL, Input Low Voltage 0.8 V max DVDD = 5 V VINL, Input Low Voltage 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.0 V min DVDD = 3 V or 5 V

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REV. 0 –5– AD7708/AD7718 Parameter B Grade Unit Test Conditions LOGIC INPUTS (Continued) SCLK Only (Schmitt-Triggered Input)2 VT(+) 1.4/2 V min/V max DVDD = 5 V VT(–) 0.8/1.4 V min/V max DVDD = 5 V VT(+) – VT(–) 0.3/0.85 V min/V max DVDD = 5 V VT(+) 0.95/2 V min/V max DVDD = 3 V VT(–) 0.4/1.1 V min/V max DVDD = 3 V VT(+)–VT(–) 0.3/0.85 V min/V max DVDD = 3 V XTAL1 Only2 VINL, Input Low Voltage 0.8 V max DVDD = 5 V VINH, Input High Voltage 3.5 V min DVDD = 5 V VINL, Input Low Voltage 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.5 V min DVDD = 3 V Input Currents ± 10 µA max Logic Input = DVDD –70 µA max Logic Input = DGND, Typical –40 µA @ 5 V and –20 µA at 3 V Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTS (Excluding XTAL2)5 VOH, Output High Voltage 2 DVDD – 0.6 V min DVDD = 3 V, ISOURCE = 100 µA VOL, Output Low Voltage 2 0.4 V max DVDD = 3 V, ISINK = 100 µA VOH, Output High Voltage 2 4 V min DVDD = 5 V, ISOURCE = 200 µA VOL, Output Low Voltage 2 0.4 V max DVDD = 5 V, ISINK = 1.6 mA Floating State Leakage Current ± 10 µA max Floating State Output Capacitance ± 10 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit –1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max START-UP TIME From Power-On 300 ms typ From Power-Down Mode 1 ms typ Oscillator Enabled 300 ms typ Oscillator Powered Down POWER REQUIREMENTS Power Supply Voltages AVDD and DVDD can be operated independently of each other. AVDD–AGND 2.7/3.6 V min/max AVDD = 3 V nom 4.75/5.25 V min/max AVDD = 5 V nom DVDD–DGND 2.7/3.6 V min/max DVDD = 3 V nom 4.75/5.25 V min DVDD = 5 V nom DIDD (Normal Mode) 0.55 mA max DVDD = 3 V, 0.43 mA typ 0.65 mA max DVDD = 5 V, 0.5 mA typ AIDD (Normal Mode) 1.1 mA max AVDD = 3 V or 5 V, 0.85 mA typ DIDD (Power-Down Mode) 10 µA max DVDD = 3 V, 32.768 kHz Osc. Running 2 µA max DVDD = 3 V, Oscillator Powered Down 30 µA max DVDD = 5 V, 32.768 kHz Osc. Running 8 µA max DVDD = 5 V, Oscillator Powered Down AIDD (Power-Down Mode) 1 µA max AVDD = 3 V or 5 V Power Supply Rejection (PSR) Input Range = ±2.56 V, AIN = 1 V Chop Disabled 70 dB min 95 dB typ Chop Enabled 100 dB typ NOTES 1Temperature range is –40°C to +85°C. 2Not production tested, guaranteed by design and/or characterization data at release. 3Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely remove this error. 4Recalibration at any temperature will remove these errors. 5I/O Port Logic Levels are with respect to AVDD and AGND. Specifications are subject to change without notice.

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REV. 0–6– AD7708/AD7718 AD7708 SPECIFICATIONS1 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffers Enabled. All specifications TMIN to TMAX unless otherwise noted.) Parameter B Grade Unit Test Conditions AD7708 (CHOP DISABLED) Output Update Rate 16.06 Hz min CHOP = 1 1.365 kHz max No Missing Codes2 16 Bits min Resolution 13 Bits p-p ±20 mV Range, SF Word = 69 16 Bits p-p ±2.56 V Range, SF Word = 69 Output Noise and Update Rates See Tables in ADC Description Integral Nonlinearity ±15 ppm of FSR max 2ppm Typical Offset Error3 ±0.65 LSB typ Following a Self-Calibration Offset Error Drift vs. Temp4 ±200 nV/°C typ Full-Scale Error3 ±0.75 LSB typ Gain Drift vs. Temp4 ±0.5 ppm/°C typ Negative Full-Scale Error ±0.003 % FSR typ ANALOG INPUTS Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and REFIN2. REFIN = REFIN(+) – REFIN(–) GAIN = 1 to 128 Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with AVDD – 100 mV V max NEGBUF = 1 Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0 AVDD + 30 mV V max Analog Input Current AIN1–AIN10 and AINCOM with NEGBUF = 1 DC Input Current2 ±1 nA max DC Bias Current Drift ±5 pA/°C typ AINCOM Input Current NEGBUF = 0 DC Input Current2 ±125 nA/V typ ±2.56 V Range DC Bias Current Drift ±2 pA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection @ DC 90 dB min 100 dB typ, Analog Input = 1 V, Input Range = ±2.56 V 110 dB typ on ± 20 mV Range @ 50 Hz 100 dB typ 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB typ 60 Hz ± 1 Hz, SF Word = 68 REFERENCE INPUTS (REFIN1 AND REFIN2) REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and REFIN2 REFIN(+) to REFIN(–) Range2 1 V min AVDD V max REFIN Common-Mode Range AGND – 30 mV V min AVDD + 30 mV V max Reference DC Input Current 0.5 µA/V typ Reference DC Input Current Drift ±0.1 nA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection Input Range = ± 2.56 V @ DC 100 dB typ Analog Input = 1 V. Input Range = ±2.56 V @ 50 Hz 100 dB typ @ 60 Hz 100 dB typ

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REV. 0 –7– AD7708/AD7718 Parameter B Grade Unit Test Conditions AD7708 (CHOP ENABLED) Output Update Rate 5.4 Hz min CHOP = 1 105 Hz max 0.732 ms Increments No Missing Codes2 16 Bits min 20 Hz Update Rate Resolution 13 Bits p-p ± 20 mV Range, 20 Hz Update Rate 16 Bits p-p ± 2.56 V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables in ADC Description Integral Nonlinearity ± 15 ppm of FSR max 2 ppm Typical Offset Error3 ± 3 µV typ Calibration is Accurate to ± 0.5 LSB Offset Error Drift vs. Temp4 10 nV/°C typ Full-Scale Error3 ± 0.75 LSB typ Includes Positive and Negative ERRORS Gain Drift vs. Temp4 ± 0.5 ppm/°C typ ANALOG INPUTS Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and REFIN2. REFIN = REFIN(+) REFIN(–) GAIN = 1 to 128 Range Matching ± 2 µV typ Analog Input = 18 mV Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with AVDD – 100 mV V max NEGBUF = 1 Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0 AVDD + 30 mV V max Analog Input Current AIN1–AIN10 and AINCOM with NEGBUF = 1 DC Input Current2 ± 1 nA max DC Input Current Drift ± 5 pA/°C typ AINCOM Input Current NEGBUF = 0 DC Input Current2 ± 125 nA/V typ DC Bias Current Drift ± 2 pA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 94 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection @ DC 90 dB min 100 dB typ, Analog Input = 1 V, Input Range = ±2.56 V 110 dB typ on ± 20 mV Range @ 50 Hz2 100 dB min 50 Hz ± 1 Hz, 20 Hz Update Rate @ 60 Hz2 100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate REFERENCE INPUTS (REFIN1 AND REFIN2) REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and REFIN2 REFIN(+) to REFIN(–) Range2 1 V min AVDD V max REFIN Common-Mode Range AGND – 30 mV V min AVDD + 30 mV V max Reference DC Input Current2 ± 0.5 µA/V typ Reference DC Input Current Drift ± 0.01 nA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection Input Range = ± 2.56 V @ DC 110 dB typ Analog Input = 1 V @ 50 Hz 110 dB typ 50 Hz ± 1 Hz, 20 Hz Update Rate @ 60 Hz 110 dB typ 60 Hz ± 1 Hz, 20 Hz Update Rate LOGIC INPUTS5 All Inputs Except SCLK and XTAL12 VINL, Input Low Voltage 0.8 V max DVDD = 5 V 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.0 V min DVDD = 3 V or 5 V

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REV. 0–8– AD7718–SPECIFICATIONS1 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications TMIN to TMAX unless otherwise noted.) 0 Parameter B Grade Unit Test Conditions LOGIC INPUTS (Continued) SCLK Only (Schmitt-Triggered Input)2 VT(+) 1.4/2 V min/V max DVDD = 5 V VT(–) 0.8/1.4 V min/V max DVDD = 5 V VT(+)–VT(–) 0.3/0.85 V min/V max DVDD = 5 V VT(+) 0.95/2 V min/V max DVDD = 3 V VT(–) 0.4/1.1 V min/V max DVDD = 3 V VT(+)–VT(–) 0.3/0.85 V min/V max DVDD = 3 V XTAL1 Only2 VINL, Input Low Voltage 0.8 V max DVDD = 5 V VINH, Input High Voltage 3.5 V min DVDD = 5 V VINL, Input Low Voltage 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.5 V min DVDD = 3 V Input Currents ± 10 µA max Logic Input = DVDD –70 µA max Logic Input = DGND, Typical –40 µA @ 5 V and –20 µA at 3 V Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTS (Excluding XTAL2)5 VOH, Output High Voltage 2 DVDD – 0.6 V min DVDD = 3 V, ISOURCE = 100 µA VOL, Output Low Voltage 2 0.4 V max DVDD = 3 V, ISINK = 100 µA VOH, Output High Voltage 2 4 V min DVDD = 5 V, ISOURCE = 200 µA VOL, Output Low Voltage 2 0.4 V max DVDD = 5 V, ISINK = 1.6 mA Floating State Leakage Current ± 10 µA max Floating State Output Capacitance ± 10 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit –1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max START-UP TIME From Power-On 300 ms typ From Power-Down Mode 1 ms typ 300 ms typ Oscillator Powered Down POWER REQUIREMENTS Power Supply Voltages AVDD and DVDD can be operated independently of each other. AVDD–AGND 2.7/3.6 V min/max AVDD = 3 V nom 4.75/5.25 V min/max AVDD = 5 V nom DVDD–DGND 2.7/3.6 V min/max DVDD = 3 V nom 4.75/5.25 V min DVDD = 5 V nom DIDD (Normal Mode) 0.55 mA max DVDD = 3 V, 0.43 mA typ 0.65 mA DVDD = 5 V, 0.5 mA typ AIDD (Normal Mode) 1.1 mA AVDD = 3 V or 5 V, 0.85 mA typ DIDD (Power-Down Mode) 10 µA max DVDD = 3 V, 32.768 kHz Osc. Running 2 µA max DVDD = 3 V, Oscillator Powered Down 30 µA max DVDD = 5 V, 32.768 kHz Osc. Running 8 µA max DVDD = 5 V, Oscillator Powered Down AIDD (Power-Down Mode) 1 µA max AVDD = 3 V or 5 V Power Supply Rejection (PSR) Input Range = ± 2.56 V, AIN = 1 V Chop Disabled 70 dB min 95 dB typ Chop Enabled 100 dB typ NOTES 1Temperature range is –40°C to +85°C. 2Not production tested, guaranteed by design and/or characterization data at release. 3Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely remove this error. 4Recalibration at any temperature will remove these errors. 5I/O Port Logic Levels are with respect to AVDD and AGND. Specifications are subject to change without notice.

Page 10

REV. 0 AD7708/AD7718 –9– TIMING CHARACTERISTICS1, 2 (AVDD = 2.7 V to 3.6 V or AVDD = 5 V  5%; DVDD = 2.7 V to 3.6 V or DVDD = 5 V  5%; AGND = DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted. Limit at TMIN, TMAX Parameter (B Version) Unit Conditions/Comments t1 32.768 kHz typ Crystal Oscillator Frequency t2 50 ns min RESET Pulsewidth Read Operation t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 3 t5 4 0 ns min SCLK Active Edge to Data Valid Delay3 60 ns max DVDD = 4.5 V to 5.5 V 80 ns max DVDD = 2.7 V to 3.6 V t5A 4, 5 0 ns min CS Falling Edge to Data Valid Delay3 60 ns max DVDD = 4.5 V to 5.5 V 80 ns max DVDD = 2.7 V to 3.6 V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time 3 t9 6 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 80 ns max t10 100 ns max SCLK Active Edge to RDY High 3, 7 Write Operation t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V. 2See Figures 1 and 2. 3SCLK active edge is falling edge of SCLK. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 5This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the load circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. Specifications subject to change without notice. TO OUTPUT PIN 50pF ISINK ISOURCE 1.6V (1.6mA WITH DVDD = 5V 100A WITH DVDD = 3V) (200A WITH DVDD = 5V 100A WITH DVDD = 3V) Figure 1. Load Circuit for Timing Characterization

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