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AD7870JN

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AD7870JN

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Part Number AD7870JN
Manufacturer Analog Devices Inc.
Description IC ADC 12BIT LC2MOS 100KHZ 24DIP
Datasheet AD7870JN Datasheet
Package 24-DIP (0.300", 7.62mm)
In Stock 1,149 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 26 - Oct 1 (Choose Expedited Shipping)
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Part Number # AD7870JN (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7870JN Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7870JNDatasheet
Package24-DIP (0.300", 7.62mm)
Series-
Number of Bits12
Sampling Rate (Per Second)100k
Number of Inputs1
Input TypeSingle Ended
Data InterfaceSPI, Parallel
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeInternal
Voltage - Supply, Analog��5V
Voltage - Supply, Digital��5V
Features-
Operating Temperature0°C ~ 70°C
Package / Case24-DIP (0.300", 7.62mm)
Supplier Device Package24-PDIP
Mounting Type-

AD7870JN Datasheet

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LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCs AD7870/AD7875/AD7876 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1997–2009 Analog Devices, Inc. All rights reserved. FEATURES Complete monolithic 12-bit ADCs with 2 μs track-and-hold amplifier 8 μs ADC On-chip reference Laser-trimmed clock Parallel, byte, and serial digital interface 72 dB SNR at 10 kHz input frequency (AD7870, AD7875) 57 ns data access time Low power: −60 mW typical Variety of input ranges ±3 V for AD7870 0 V to +5 V for AD7875 ±10 V for AD7876 FUNCTIONAL BLOCK DIAGRAM REF OUT VIN INPUT SCALING 12-BIT DAC PARALLEL AND SERIAL INTERFACE AD7870/AD7875/ AD7876 CONTROL LOGIC CLOCK 3V REFERENCE SAR + COUNTER COMP TRACK-AND-HOLD VDD VSSDGND 07 7 30 -0 0 1 DB11 DB0CS RD BUSY/INT AGND CLK CONVST 12/8/CLK Figure 1. GENERAL DESCRIPTION The AD7870/AD7875/AD7876 are fast, complete, 12-bit analog-to-digital converters (ADCs). These converters consist of a track-and-hold amplifier, an 8 μs successive approximation ADC, a 3 V buried Zener reference, and versatile interface logic. The ADCs feature a self-contained internal clock which is laser trimmed to guarantee accurate control of conversion time. No external clock timing components are required; the on-chip clock may be overridden by an external clock if required. The parts offer a choice of three data output formats: a single, parallel, 12-bit word; two 8-bit bytes or serial data. Fast bus access times and standard control inputs ensure easy interfacing to modern microprocessors and digital signal processors. All parts operate from ±5 V power supplies. The AD7870 and AD7876 accept input signal ranges of ±3 V and ±10 V, respec- tively, while the AD7875 accepts a unipolar 0 V to +5 V input range. The parts can convert full power signals up to 50 kHz. The AD7870/AD7875/AD7876 feature dc accuracy specifica- tions, such as linearity, full-scale and offset error. In addition, the AD7870 and AD7875 are fully specified for dynamic performance parameters including distortion and signal-to- noise ratio. The parts are available in a 24-pin, 0.3 inch-wide, plastic or hermetic dual-in-line package (DIP). The AD7870 and AD7875 are available in a 28-pin plastic leaded chip carrier (PLCC), while the AD7876 is available and in a 24-pin small outline (SOIC) package. PRODUCT HIGHLIGHTS 1. Complete 12-bit ADC on a chip. The AD7870/AD7875/AD7876 provide all the functions necessary for analog-to-digital conversion and combine a 12-bit ADC with internal clock, track-and-hold amplifier and reference on a single chip. 2. Dynamic specifications for DSP users. The AD7870 and AD7875 are fully specified and tested for ac parameters, including signal-to-noise ratio, harmonic distortion and intermodulation distortion. 3. Fast microprocessor interface. Data access times of 57 ns make the parts compatible with modern 8-bit and 16-bit microprocessors and digital signal processors. Key digital timing parameters are tested and guaranteed over the full operating temperature range.

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AD7870/AD7875/AD7876 Rev. C | Page 2 of 28 TABLE OF CONTENTS Features .............................................................................................. 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Product Highlights ........................................................................... 1  Revision History ............................................................................... 2  Specifications ..................................................................................... 3  AD7870 Specifications ................................................................. 3  AD7875/AD7876 Specifications ................................................. 4  Timing Characteristics ................................................................ 6  Absolute Maximum Ratings ............................................................ 7  ESD Caution .................................................................................. 7  Pin Configurations and Function Descriptions ........................... 8  Load Circuits ................................................................................... 10  Converter Details ............................................................................ 11  Internal Reference ...................................................................... 11  Track-and-Hold Amplifier ........................................................ 11  Analog Input ............................................................................... 11  Offset And Full-Scale Adjustment—AD7870 ........................ 12  Offset And Full-Scale Adjustment—AD7876 ........................ 13  Offset And Full-Scale Adjustment—AD7875 ........................ 13  Timing and Control ....................................................................... 14  Data Output Formats ................................................................. 14  Mode 1 Interface ......................................................................... 14  Mode 2 Interface ......................................................................... 15  Dynamic Specifications ............................................................. 16  Microprocessor Interface ............................................................... 19  Parallel Read Interfacing ........................................................... 19  Two-Byte Read Interfacing ....................................................... 19  Serial Interfacing ........................................................................ 20  Standalone Operation ................................................................ 21  Applications Information .............................................................. 22  Layout Hints ................................................................................ 22  Noise ............................................................................................ 22  Outline Dimensions ....................................................................... 23  Ordering Guide .......................................................................... 25  REVISION HISTORY 2/09—Rev. B to Rev. C Updated Format .................................................................. Universal Reorganized Layout ............................................................ Universal Deleted S Version ................................................................ Universal Changes to Internal Clock Parameter, Table 1 and Added Endnote to Table 1 ............................................................... 4 Changes to Internal Clock Parameter, Table 2 .............................. 5 Changes to Mode 1 Interface Section .......................................... 14 Deleted Data Acquisition Board and Interface Connections Sections and Figure 26 ................................................................... 15 Deleted Figure 27 and Power Supply Connections, Shorting Plug Options and Components List Sections ............................. 16 Deleted Figure 28 and Figure 29 ................................................... 17 Deleted Figure 30 and Figure 31 ................................................... 18 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 25

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AD7870/AD7875/AD7876 Rev. C | Page 3 of 28 SPECIFICATIONS VDD = +5 V ± 5%, VSS = −5 V ± 5%, AGND = DGND = 0 V, fCLK = 2.5 MHz external, unless otherwise stated. All Specifications Tmin to Tmax, unless otherwise noted. AD7870 SPECIFICATIONS Table 1. ADN78701 Parameter J, A K, B L, C T Units Test Conditions/Comments DYNAMIC PERFORMANCE2 Signal-to-Noise Ratio3 (SNR) @ +25°C 70 70 72 69 dB min VIN = 10 kHz sine wave, fSAMPLE = 100 kHz TMIN to TMAX 70 70 71 69 dB min Typically 71.5 dB for 0 < VIN < 50 kHz Total Harmonic Distortion (THD) −80 −80 −80 −78 dB max VIN = 10 kHz sine wave, fSAMPLE = 100 kHz Typically −86 dB for 0 < VIN < 50 kHz Peak Harmonic or Spurious Noise −80 −80 −80 −78 dB max VIN = 10 kHz, fSAMPLE = 100 kHz Typically −86 dB for 0 < VIN < 50 kHz Intermodulation Distortion (IMD) Second Order Terms −80 −80 −80 −78 dB max fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz Third Order Terms −80 −80 −80 −78 dB max fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz Track-and-Hold Acquisition Time 2 2 2 2 μs max DC ACCURACY Resolution 12 12 12 12 Bits Minimum Resolution for which No Missing Codes are Guaranteed 12 12 12 12 Bits Integral Nonlinearity ±1/2 ±1/2 ±1/4 ±1/2 LSB typ Integral Nonlinearity ±1 ±1/2 ±1 LSB max Differential Nonlinearity ±1 ±1 ±1 LSB max Bipolar Zero Error ±5 ±5 ±5 ±5 LSB max Positive Full-Scale Error4 ±5 ±5 ±5 ±5 LSB max Negative Full-Scale Error4 ±5 ±5 ±5 ±5 LSB max ANALOG INPUT Input Voltage Range ±3 ±3 ±3 ±3 V Input Current ±500 ±500 ±500 ±500 μA max REFERENCE OUTPUT REF OUT @ +25°C 2.99 2.99 2.99 2.99 V min 3.01 3.01 3.01 3.01 V max REF OUT Tempco ±60 ±60 ±35 ±35 ppm/°C max Reference Load Sensitivity (ΔREF OUT/ΔI) ±1 ±1 ±1 ±1 mV max Reference load current change (0 μA to 500 μA). Reference load should not be changed during conversion. LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 2.4 2.4 V min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 0.8 0.8 0.8 V max VDD = 5 V ± 5% Input Current, IIN ±10 ±10 ±10 ±10 μA max VIN = 0 V to VDD Input Current (12/8/CLK Input Only) ±10 ±10 ±10 ±10 μA max VIN = VSS to VDD Input Capacitance, CIN5 10 10 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH 4.0 4.0 4.0 4.0 V min ISOURCE = 40 μA Output Low Voltage, VOL 0.4 0.4 0.4 0.4 V max ISINK = 1.6 mA DB11 to DB0 Floating-State Leakage Current ±10 ±10 ±10 ±10 μA max Floating-State Output Capacitance5 15 15 15 15 pF max

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AD7870/AD7875/AD7876 Rev. C | Page 4 of 28 ADN78701 Parameter J, A K, B L, C T Units Test Conditions/Comments CONVERSION TIME External Clock (fCLK = 2.5 MHz) 8 8 8 8 μs max Internal Clock6 6.5/9 6.5/9 6.5/9 6.5/9 μs min/ μs max POWER REQUIREMENTS VDD +5 +5 +5 +5 V nom ±5% for specified performance VSS −5 −5 −5 −5 V nom ±5% for specified performance IDD 13 13 13 13 mA max Typically 8 mA ISS 6 6 6 6 mA max Typically 4 mA Power Dissipation 95 95 95 95 mW max Typically 60 mW 1 The temperature range for the J, K, and L versions is from 0°C to +70°C; for the A, B, and C versions is−40°C to +85°C; and for the T version is −55°C to +125°C. 2 VIN (p-p) = ±3 V. 3 SNR calculation includes distortion and noise components. 4 Measured with respect to internal reference and includes bipolar offset error. 5 Sample tested @ +25°C to ensure compliance. 6 Conversion time specification for the AD7870A device with internal clock used is 8 μs/10 μs minimum/maximum. AD7875/AD7876 SPECIFICATIONS Table 2. Parameter AD7875/AD78761 Units Test Conditions/Comments K, B L, C T DC ACCURACY Resolution 12 12 12 Bits Min Resolution for which No Missing Codes Are Guaranteed 12 12 12 Bits Integral Nonlinearity @ +25°C ±1 ±1/2 ±1 LSB max TMIN to TMAX (AD7875 Only) ±1 ±1 ±1 LSB max TMIN to TMAX (AD7876 Only) ±1 ±1/2 ±1 LSB max Differential Nonlinearity ±1 ±1 ±1.5/−1.0 LSB max Unipolar Offset Error (AD7875 Only) ±5 ±5 ±5 LSB max Bipolar Zero Error (AD7876 Only) ±6 ±2 ±6 LSB max Full-Scale Error at +25°C2 ±8 ±8 ±8 LSB max Typical full-scale error is ±1 LSB Full-Scale TC2 ±60 ±35 ±60 ppm/°C max Typical TC is ±20 ppm/°C Track-and-Hold Acquisition Time 2 2 2 μs max DYNAMIC PERFORMANCE3 (AD7875 ONLY) Signal-to-Noise Ratio4 (SNR) @ +25°C 70 72 69 dB min VIN = 10 kHz sine wave, fSAMPLE = 100 kHz TMIN to TMAX 70 71 69 dB min Typically 71.5 dB for 0 < VIN < 50 kHz Total Harmonic Distortion (THD) −80 −80 −78 dB max VIN = 10 kHz sine wave, fSAMPLE = 100 kHz Typically −86 dB for 0 < VIN < 50 kHz Peak Harmonic or Spurious Noise −80 −80 −78 dB max VIN = 10 kHz, fSAMPLE = 100 kHz Typically −86 dB for 0 < VIN < 50 kHz Intermodulation Distortion (IMD) Second Order Terms −80 −80 −78 dB max fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz Third Order Terms −80 −80 −78 dB max fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz

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AD7870/AD7875/AD7876 Rev. C | Page 5 of 28 Parameter AD7875/AD78761 Units Test Conditions/Comments K, B L, C T ANALOG INPUT AD7875 Input Voltage Range 0 to +5 0 to +5 0 to +5 V AD7875 Input Current 500 500 500 μA max AD7876 Input Voltage Range ±10 ±10 ±10 V AD7876 Input Current ±600 ±600 ±600 μA max REFERENCE OUTPUT REF OUT @ +25°C 2.99 2.99 2.99 V min 3.01 3.01 3.01 V max REF OUT Tempco ±60 ±35 ±60 ppm/°C max Typical tempco Is ±20 ppm/°C Reference Load Sensitivity (ΔREF OUT/ΔI) −1 −1 −1 mV max Reference load current change (0 μA to 500 μA). Reference load should not be changed during conversion. LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 2.4 V min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 0.8 0.8 V max VDD = 5 V ± 5% Input Current, IIN ±10 ±10 ±10 μA max VIN = 0 V to VDD Input Current (12/8/CLK Input Only) ±10 ±10 ±10 μA max VIN = VSS to VDD Input Capacitance, CIN5 10 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH 4.0 4.0 4.0 V min ISOURCE = 40 mA Output Low Voltage, VOL 0.4 0.4 0.4 V max ISINK = 1.6 mA DB11–DB0 Floating-State Leakage Current 10 10 10 μA max Floating-State Output Capacitance5 15 15 15 pF max CONVERSION TIME External Clock (fCLK = 2.5 MHz) 8 8 8 μs max Internal Clock 6.5/9 6.5/9 6.5/9 μs min/μs max POWER REQUIREMENTS As per AD7870 Refer to the power requirements in Table 1. 1 For the AD7875, the temperature range for the K and L versions is from 0°C to +70°C; for the B and C versions is−40°C to +85°C; and for the T version is −55°C to +125°C. For the AD7876, the temperature range for the B and C versions is from −40°C to +85°C and for the T version is−55°C to +125°C. 2 Includes internal reference error and is calculated after unipolar offset error (AD7875) or bipolar zero error (AD7876) has been adjusted out. Full-scale error refers to both positive and negative full-scale error for the AD7876. 3 Dynamic performance parameters are not tested on the AD7876, but these are typically the same as for the AD7875. 4 SNR calculation includes distortion and noise components. 5 Sample tested @ +25°C to ensure compliance.

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AD7870/AD7875/AD7876 Rev. C | Page 6 of 28 TIMING CHARACTERISTICS VDD = +5 V ± 5%, VSS = −5 V ± 5%, AGND = DGND = 0 V. See Figure 14, Figure 15, Figure 16, and Figure 17. Timing specifications are sample tested at 25°C to ensure compliance, unless otherwise noted. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Table 3. Parameter1 Limit at TMIN, TMAX (J, K, L, A, B, C Versions) Limit at TMIN, TMAX (T Version) Units Conditions/Comments t1 50 50 ns min CONVST pulse width t2 0 0 ns min CS to RD setup time (Mode 1) t32 60 75 ns min RD pulse width t4 0 0 ns min CS to RD hold time (Mode 1) t5 70 70 ns max RD to INT delay t62, 3 57 70 ns max Data access time after RD t72, 4 5 5 ns min Bus relinquish time after RD 50 50 ns max t8 0 0 ns min HBEN to RD setup time t9 0 0 ns min HBEN to RD hold time t10 100 100 ns min SSTRB to SCLK falling edge setup time t115 370 370 ns min SCLK cycle time t126 135 150 ns max SCLK to valid data delay. CL = 35 pF t13 20 20 ns min SCLK rising edge to SSTRB 100 100 ns max t14 10 10 ns min Bus relinquish time after SCLK 100 100 ns max t15 60 60 ns min CS to RD setup time (Mode 2) t16 120 120 ns max CS to BUSY propagation delay t17 200 200 ns min Data setup time prior to BUSY t18 0 0 ns min CS to RD hold time (Mode 2) t19 0 0 ns min HBEN to CS setup time t20 0 0 ns min HBEN to CS hold time 1 Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF. 2 Timing specifications for t3, t6, and for the maximum limit at t7 are 100% production tested. 3 t6 is measured with the load circuits of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4 t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 5. 5 SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40. 6 SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 kΩ||CL) and thus the time to reach 2.4 V.

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AD7870/AD7875/AD7876 Rev. C | Page 7 of 28 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating VDD to AGND −0.3 V to +7 V VSS to AGND +0.3 V to −7 V AGND to DGND −0.3 V to VDD +0.3 V VIN to AGND −15 V to +15 V REF OUT to AGND 0 V to VDD Digital Inputs to DGND −0.3 V to VDD +0.3 V Digital Outputs to DGND −0.3 V to VDD +0.3 V Operating Temperature Range Commercial (J, K, L Versions–AD7870) 0°C to +70°C Commercial (K, L Versions–AD7875) 0°C to +70°C Industrial (A, B, C Versions–AD7870) −25°C to +85°C Industrial (B, C Versions–AD7875/ AD7876) −40°C to +85°C Extended (T Version) −55°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) +300°C Power Dissipation (Any Package) to +75°C 450 mW Derates above +75°C by 10 mW/°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

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AD7870/AD7875/AD7876 Rev. C | Page 8 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS RD 1 BUSY/INT 2 CLK 3 DB11/HBEN 4 CS24 CONVST23 12/8/CLK22 VSS21 DB10/SSTRB 5 DB9/SCLK 6 DB8/SDATA 7 VIN20 REF OUT19 AGND18 DB7/LOW 8 VDD17 DB6/LOW 9 DB0/DB816 DB5/LOW 10 DB1/DB915 DB4/LOW 11 DB2/DB1014 DGND 12 DB3/DB1113 AD7870/ AD7875/ AD7876 TOP VIEW (Not to Scale) 07 73 0- 0 04 Figure 2. DIP and SOIC Pin Configuration 1 28 27 26234 5 6 7 8 9 10 11 25 24 23 22 21 20 19 NC = NO CONNECT DB11/HBEN DB10/SSTRB DB9/SCLK NC DB8/SDATA DB7/LOW DB6/LOW VSS VIN REF OUT NC AGND VDD DB0/DB8 C L K B U S Y /I N T R D N C C S C O N V S T 12 /8 /C L K D B 5/ L O W D B 4/ L O W D G N D N C D B 3/ D B 11 D B 2/ D B 10 D B 1/ D B 9 PIN 1 INDENTFIER 12 13 14 15 16 17 18 07 73 0- 0 05 AD7870/AD7875/ AD7876 TOP VIEW (Not to Scale) Figure 3. PLCC Pin Configuration Table 5. Pin Function Descriptions DIP and SOIC Pin No. PLCC Pin No. Mnemonic Function N/A 1, 8, 15, 22 NC No Connect. 1 2 RD Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs. 2 3 BUSY/INT Busy/Interrupt. Active low logic output indicating converter status. See Figure 14, Figure 15, Figure 16, and Figure 17. 3 4 CLK Clock Input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying this pin to VSS enables the internal laser-trimmed clock oscillator. 4 5 DB11/HBEN Data Bit 11 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 12/8/CLK input. When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is low, DB7/LOW to DB0/DB8 become DB7 to DB0. With HBEN high, DB7/LOW to DB0/DB8 are used for the upper byte of data (see ). Table 6 5 6 DB10/SSTRB Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output. SSTRB is an active low open-drain output that provides a strobe or framing pulse for serial data. An external 4.7 kΩ pull-up resistor is required on SSTRB. 6 7 DB9/SCLK Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is the gated serial clock output derived from the internal or external ADC clock. If the 12/8/CLK input is at −5 V, then SCLK runs continuously. If 12/8/CLK is at 0 V, then SCLK is gated off after serial transmission is complete. SCLK is an open-drain output and requires an external 2 kΩ pull-up resistor. 7 9 DB8/SDATA Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA is an open-drain serial data output which is used with SCLK and SSTRB for serial data transfer. Serial data is valid on the falling edge of SCLK while SSTRB is low. An external 4.7 kΩ pull-up resistor is required on SDATA. 8 to11 10 to 13 DB7/LOW– DB4/LOW Three-state data outputs controlled by CS and RD. Their function depends on the 12/8/CLK and HBEN inputs. With 12/8/CLK high, they are always DB7–DB4. With 12/8/CLK low or −5 V, their function is controlled by HBEN (see ). Table 6 12 14 DGND Digital Ground. Ground reference for digital circuitry. 13 to 16 16 to 19 DB3/DB11– DB0/DB8 Three-state data outputs which are controlled by CS and RD. Their function depends on the 12/8/CLK and HBEN inputs. With 12/8/CLK high, they are always DB3–DB0. With 12/8/CLK low or −5 V, their function is controlled by HBEN (see ). Table 6 17 20 VDD Positive Supply, +5 V ± 5%.

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AD7870/AD7875/AD7876 Rev. C | Page 9 of 28 DIP and SOIC Pin No. PLCC Pin No. Mnemonic Function 18 21 AGND Analog Ground. Ground reference for track-and-hold, reference and DAC. 19 23 REF OUT Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is 500 μA. 20 24 VIN Analog Input. The analog input range is ±3 V for the AD7870, ±10 V for the AD7876, and 0 V to +5 V for the AD7875. 21 25 VSS Negative Supply, −5 V ± 5%. 22 26 12/8/CLK Three Function Input. Defines the data format and serial clock format. With this pin at +5 V, the output data for-mat is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK is not continuous. With this pin at −5 V, either byte or serial data is again available but SCLK is now continuous. 23 27 CONVST Convert Start. A low to high transition on this input puts the track-and-hold into its hold mode and starts conversion. This input is asynchronous to the CLK input. 24 28 CS Chip Select. Active low logic input. The device is selected when this input is active. With CONVST tied low, a new conversion is initiated when CS goes low. Table 6. Output Data for Byte Interfacing HBEN DB7/Low DB6/Low DB5/Low DB4/Low DB3/DB11 DB2/DB10 DB1/DB9 DB0/DB8 High Low Low Low Low DB11(MSB) DB10 DB9 DB8 Low DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB)

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August 19, 2020

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August 12, 2020

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August 10, 2020

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August 3, 2020

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July 26, 2020

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July 17, 2020

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July 14, 2020

These function just as well. You do need to spend some time modifying the harness, but no big deal.

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July 14, 2020

Can't speak to the long term reliability as of yet, but they seem to be of decent quality and I don't expect any issues.

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July 4, 2020

Went well this time Now have the IC and very pleased.

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July 3, 2020

I had no problems with this product. Would I recommend it. Yes.

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