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AD7894AR-10

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AD7894AR-10

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Part Number AD7894AR-10
Manufacturer Analog Devices Inc.
Description IC ADC 14BIT SRL T/H LP 8-SOIC
Datasheet AD7894AR-10 Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 10,000 piece(s)
Unit Price $ 17.7696 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 14 - Jul 19 (Choose Expedited Shipping)
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Part Number # AD7894AR-10 (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7894AR-10 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7894AR-10Datasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
Number of Bits14
Sampling Rate (Per Second)200k
Number of Inputs1
Input TypeSingle Ended
Data InterfaceSPI
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeExternal
Voltage - Supply, Analog5V
Voltage - Supply, Digital5V
Features-
Operating Temperature-40°C ~ 85°C
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC
Mounting Type-

AD7894AR-10 Datasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD7894 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 5 V, 14-Bit Serial, 5 ms ADC in SO-8 Package FUNCTIONAL BLOCK DIAGRAM SIGNAL SCALING* TRACK/ HOLD 14-BIT ADC AD7894 OUTPUT REGISTER REF IN VDD VIN CONVST GND BUSY SCLK SDATA *AD7894-10, AD7894-3 FEATURES Fast 14-Bit ADC with 5 ms Conversion Time 8-Lead SOIC Package Single 5 V Supply Operation High Speed, Easy-to-Use, Serial Interface On-Chip Track/Hold Amplifier Selection of Input Ranges 610 V for AD7894-10 62.5 V for AD7894-3 0 V to +2.5 V for AD7894-2 High Input Impedance Low Power: 20 mW Typ Pin Compatible Upgrade of 12-Bit AD7895 GENERAL DESCRIPTION The AD7894 is a fast, 14-bit ADC that operates from a single +5 V supply and is housed in a small 8-lead SOIC. The part contains a 5 µs successive approximation A/D converter, an on- chip track/hold amplifier, an on-chip clock and a high speed serial interface. Output data from the AD7894 is provided via a high speed, serial interface port. This two-wire serial interface has a serial clock input and a serial data output with the external serial clock accessing the serial data from the part. In addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the AD7894 is also speci- fied for dynamic performance parameters including harmonic distortion and signal-to-noise ratio. The part accepts an analog input range of ±10 V (AD7894-10), ±2.5 V (AD7894-3), 0 V to +2.5 V (AD7894-2), and operates from a single +5 V supply consuming only 20 mW typical. The AD7894 features a high sampling rate mode and, for low power applications, a proprietary automatic power-down mode where the part automatically goes into power-down once conver- sion is complete and “wakes up” before the next conversion cycle. The part is available in a small outline IC (SOIC). PRODUCT HIGHLIGHTS 1. Fast, 14-Bit ADC in 8-Lead Package The AD7894 contains a 5␣ µs ADC, a track/hold amplifier, control logic and a high speed serial interface, all in an 8-lead package. This offers considerable space saving over alterna- tive solutions. 2. Low Power, Single Supply Operation The AD7894 operates from a single +5 V supply and con- sumes only 20 mW. The automatic power-down mode, where the part goes into power-down once conversion is complete and “wakes up” before the next conversion cycle, makes the AD7894 ideal for battery powered or portable applications. 3. High Speed Serial Interface The part provides high speed serial data and serial clock lines allowing for an easy, two-wire serial interface arrangement.

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–2– REV. 0 AD7894–SPECIFICATIONS (VDD = +5 V 6 5%, GND = 0 V, REF IN = +2.5 V. All specifications TMIN to TMAX unless otherwise noted.) Parameter A Versionsl B Versions1 Units Test Conditions/Comments DYNAMIC PERFORMANCE2 Signal to (Noise + Distortion) Ratio3 @ +25°C 78 78 dB min fIN = 70 kHz Sine Wave, fSAMPLE = 160 kHz TMIN to TMAX 77 77 dB min See Figure 14 Total Harmonic Distortion (THD)3 –86 –86 dB max fIN = 10 kHz Sine Wave, fSAMPLE = 160 kHz, Typically –87 dB. See Figure 15 Peak Harmonic or Spurious Noise3 –92 –92 dB typ fIN = 10 kHz Sine Wave, fSAMPLE = 160 kHz Intermodulation Distortion (IMD)3 fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 160 kHz 2nd Order Terms –92 –92 dB typ 3rd Order Terms –92 –92 dB typ DC ACCURACY Resolution 14 14 Bits Minimum Resolution for Which No Missing Codes Are Guaranteed 14 14 Bits Relative Accuracy3 ±2 ±1.5 LSB max Differential Nonlinearity3 –1 to +1.5 –1 to +1.5 LSB max AD7894-2 Positive Gain Error3 ±12 ±10 LSB max Unipolar Offset Error ±8 ±6 LSB max AD7894-10, AD7894-3 Only Positive Gain Error3 ±8 ±6 LSB max Negative Gain Error3 ±8 ±6 LSB max Bipolar Zero Error ±10 ±8 LSB max ANALOG INPUT AD7894-10 Input Voltage Range ±10 ±10 V Input Current 2 2 mA max See Analog Input Section AD7894-3 Input Voltage Range ±2.5 ±2.5 V Input Current 1.5 1.5 mA max See Analog Input Section AD7894-2 Input Voltage Range 0 to +2.5 0 to +2.5 V Input Current 500 500 nA max REFERENCE INPUT REF IN Input Voltage Range 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5% Input Current 1 1 µA max Input Capacitance4 10 10 pF max LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 V min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V ± 5% Input Current, IIN ±10 ±10 µA max VIN = 0 V to VDD Input Capacitance, CIN 4 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH 4.0 4.0 V min ISOURCE = 400 µA Output Low Voltage, VOL 0.4 0.4 V max ISINK = 1.6 mA Output Coding AD7894-10, AD7894-3 Twos Complement AD7894-2 Straight (Natural) Binary CONVERSION RATE Conversion Time Mode 1 Operation 5 5 µs max Mode 2 Operation5 10 10 µs max Track/Hold Acquisition Time3 0.35 0.35 µs max SAMPLE AND HOLD –3 dB Small Signal Bandwidth 7.5 7.5 MHz typ Aperture Jitter 50 50 ps typ

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–3–REV. 0 AD7894 Parameter A Versionsl B Versions1 Units Test Conditions/Comments POWER REQUIREMENTS VDD +5 +5 V nom ±5% for Specified Performance IDD 5.5 5.5 mA max Digital Inputs @ VDD, VDD = 5 V ± 5% Power Dissipation 27.5 27.5 mW max Typically 20 mW Power-Down Mode IDD @ TMIN to TMAX 20 20 µA max Digital Inputs @ GND, VDD = 5 V ± 5% Power Dissipation TMIN to TMAX 100 100 µW max Typ 15 µW NOTES 1Temperature ranges are as follows: A, B Versions: –40°C to +85°C. 2Applies to Mode 1 operation. See Operating Modes section. 3See Terminology. 4Sample tested @ +25°C to ensure compliance. 5This 10 µs includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for narrow CONVST pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10 µs. This can be seen from Figure 3. Note that if the CONVST pulsewidth is greater than 5 µs, the effective conversion time will increase beyond 10 µs. Specifications subject to change without notice. TIMING CHARACTERISTICS1, 2 Parameter A, B Versions Units Test Conditions/Comments t1 40 ns min CONVST Pulsewidth t2 31.25 2 ns min SCLK High Pulsewidth t3 31.25 2 ns min SCLK Low Pulsewidth t4 60 3 ns max Data Access Time after Falling Edge of SCLK VDD = 5 V ± 5% t5 10 ns min Data Hold Time after Falling Edge of SCLK t6 20 4 ns max Bus Relinquish Time after Falling Edge of SCLK NOTES 1Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2The SCLK maximum frequency is 16 MHz. Care must be taken when interfacing to account for the data access time, t4, and the setup time required for the user’s processor. These two times will determine the maximum SCLK frequency with which the user’s system can operate. See Serial Interface section for more information. 3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 6, quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. (VDD = +5 V 6 5%, GND = 0 V, REF IN = +2.5 V) ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7 V Analog Input Voltage to GND ␣ ␣ AD7894-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V ␣ ␣ AD7894-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V ␣ ␣ AD7894-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +10 V Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range ␣ ␣ Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C ␣ ␣ Storage Temperature Range . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW ␣ ␣ θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 170°C/W ␣ ␣ Lead Temperature, Soldering ␣ ␣ ␣ ␣ Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C ␣ ␣ ␣ ␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7894 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

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AD7894 –4– REV. 0 ORDERING GUIDE Temperature Package Package Model Range INL Input Range SNR Description Option AD7894AR-10 –40°C to +85°C ±2 LSB ±10 V 77 dB 8-Lead Narrow Body SOIC SO-8 AD7894BR-10 –40°C to +85°C ±1.5 LSB ±10 V 77 dB 8-Lead Narrow Body SOIC SO-8 AD7894AR-3 –40°C to +85°C ±2 LSB ±2.5 V 77 dB 8-Lead Narrow Body SOIC SO-8 AD7894BR-3 –40°C to +85°C ±1.5 LSB ±2.5 V 77 dB 8-Lead Narrow Body SOIC SO-8 AD7894AR-2 –40°C to +85°C ±2 LSB 0 V to +2.5 V 77 dB 8-Lead Narrow Body SOIC SO-8 PIN FUNCTION DESCRIPTIONS Pin Pin No. Mnemonic Description 1 REF IN Voltage Reference Input. An external reference source should be connected to this pin to provide the reference voltage for the AD7894’s conversion process. The REF IN input is buffered on-chip. The nominal reference voltage for correct operation of the AD7894 is +2.5␣ V. 2 VIN Analog Input Channel. The analog input range is ±10 V (AD7894-10), ±2.5 V (AD7894-3) and 0 V to +2.5␣ V (AD7894-2). 3 GND Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC. 4 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7894. A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for 10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used. The serial clock input should be taken low at the end of the serial data transmission. 5 SDATA Serial Data Output. Serial data from the AD7894 is provided at this output. The serial data is clocked out by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is pos- sible because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see Figure 5). Sixteen bits of serial data are provided as two leading zeroes followed by the 14 bits of conver- sion data. On the 16th falling edge of SCLK, the SDATA line is held for the data hold time and then disabled (three-stated). Output data coding is twos complement for the AD7894-10 and AD7894-3, and straight binary for the AD7894-2. 6 BUSY The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on the falling edge of CONVST and will return low when the conversion is complete. 7 CONVST Conversion Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its hold mode and conversion is initiated. If CONVST is low at the end of conversion, the part goes into power-down mode. In this case, the rising edge of CONVST will cause the part to begin waking up. 8 VDD Positive supply voltage, +5 V ± 5%. 1.6mA 400mA +1.6V TO OUTPUT PIN 50pF Figure 1. Load Circuit for Access Time and Bus Relinquish Time PIN CONFIGURATION SOIC (SO-8) TOP VIEW (Not to Scale) 8 7 6 5 1 2 3 4 REF IN VIN GND VDD CONVST BUSY SDATASCLK AD7894

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AD7894 –5–REV. 0 TERMINOLOGY Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quan- tization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02␣ N + 1.76) dB Thus for a 14-bit converter, this is 86.04 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7894, it is defined as: THD dB V V V V V V ( ) log= + + + + 20 2 2 3 2 4 2 5 2 6 2 1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. The value of this specification is normally deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n is equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The AD7894 is tested using two input frequencies. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Relative Accuracy Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1␣ LSB change between any two adjacent codes in the ADC. Positive Gain Error (AD7894-10) This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal (4 × VREF – 1 LSB) after the Bipolar Zero Error has been adjusted out. Positive Gain Error (AD7894-3) This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal (VREF – 1 LSB) after the Bipolar Zero Error has been adjusted out. Positive Gain Error (AD7894-2) This is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal (VREF – 1 LSB) after the Unipolar Offset Error has been adjusted out. Bipolar Zero Error (AD7894-10, AD7894-3) This is the deviation of the midscale transition (all 0s to all 1s) from the ideal 0 V (GND). Unipolar Offset Error (AD7894-2) This is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal 1 LSB. Negative Gain Error (AD7894-10) This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal (–4 × VREF + 1 LSB) after Bipolar Zero Error has been adjusted out. Negative Gain Error (AD7894-3) This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal (– VREF + 1 LSB) after Bipolar Zero Error has been adjusted out. Track/Hold Acquisition Time Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ±1/2␣ LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the VIN input of the AD7894. This means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to VIN before starting another conversion, to ensure that the part operates to specification.

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AD7894 –6– REV. 0 CONVERTER DETAILS The AD7894 is a fast, 14-bit single supply A/D converter. It provides the user with signal scaling, track/hold, A/D converter and serial interface logic functions on a single chip. The A/D converter section of the AD7894 consists of a conventional successive-approximation converter based around an R-2R ladder structure. The signal scaling on the AD7894-10 and AD7894-3 allows the part to handle ±10 V and ±2.5 V input signals respectively while operating from a single +5␣ V supply. The AD7894-2 accepts an analog input range of 0 V to +2.5 V. The part requires an external +2.5 V reference. The reference input to the part is buffered on-chip. The AD7894 has two operating modes, the high sampling mode and the “auto-sleep” mode where the part automatically goes into sleep after the end of conversion. These modes are discussed in more detail in the Timing and Control Section. A major advantage of the AD7894 is that it provides all of the above functions in an 8-lead SOIC package. This offers the user considerable space saving advantages over alternative solutions. The AD7894 typically consumes only 20␣ mW, making it ideal for battery powered applications. Conversion is initiated on the AD7894 by pulsing the CONVST input. On the falling edge of CONVST, the on-chip track/hold goes from track-to-hold mode and the conversion sequence is started. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. Conversion time for the AD7894 is 5␣ µs in the high sampling mode (10 µs for the auto sleep mode), and the track/hold acquisition time is 0.35␣ µs. To obtain optimum performance from the part, the read operation should not occur during the conversion or during 250 ns prior to the next conversion. This allows the part to operate at through- put rates up to 160 kHz and achieve data sheet specifications. CIRCUIT DESCRIPTION Analog Input Section The AD7894 is offered as three part types, the AD7894-10, which handles a ±10 V input voltage range, the AD7894-3, which handles input voltage range ±2.5 V and the AD7894-2, which handles a 0␣ V to +2.5␣ V input voltage range. TRACK/ HOLD AD7894-10/AD7894-3 REF IN VIN GND R1 R2 R3 TO ADC REFERENCE CIRCUITRY TO INTERNAL COMPARATOR Figure 2. AD7894-10/AD7894-3 Analog Input Structure Figure 2 shows the analog input section for the AD7894-10 and AD7894-3. The analog input range of the AD7894-10 is ±10 V and the analog input range for the AD7894-3 is ±2.5 V. This input is benign, with no dynamic charging currents as the resis- tor stage is followed by a high input impedance stage of the track/hold amplifier. For the AD7894-10, R1 = 8 kΩ, R2 = 2 kΩ and R3 = 2 kΩ. For the AD7894-3, R1 = R2 = 2 kΩ and R3 is open circuit. The current flowing in the analog input is di- rectly related to the analog input voltage. The maximum input current flows when the analog input is at negative full scale. For the AD7894-10 and AD7894-3, the designed code transi- tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs, 3 LSBs . . .). Output coding is twos complement binary with 1 LSB = FS/16384. The ideal input/output transfer function for the AD7894-10 and AD7894-3 is shown in Table I. Table I. Ideal Input/Output Code Table for the AD7894-10/ AD7894-3 Digital Output Analog Inputl Code Transition +FSR/2 – 1 LSB2 011 . . . 110 to 011 . . . 111 +FSR/2 – 2 LSBs 011 . . . 101 to 011 . . . 110 +FSR/2 – 3 LSBs 011 . . . 100 to 011 . . . 101 GND + 1 LSB 000 . . . 000 to 000 . . . 001 GND 111 . . . 111 to 000 . . . 000 GND – 1 LSB 111 . . . 110 to 111 . . . 111 –FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011 –FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010 –FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001 NOTES 1FSR is full-scale range = 20 V (AD7894-10) and = 5 V (AD7894-3) with REF IN = +2.5 V. 21 LSB = FSR/16384 = 1.22 mV (AD7894-10) and 0.3 mV (AD7894-3) with REF IN = +2.5 V. The analog input section for the AD7894-2 contains no biasing resistors and the VIN pin drives the input directly to the track/ hold amplifier. The analog input range is 0 V to +2.5 V into a high impedance stage with an input current of less than 500␣ nA. This input is benign, with no dynamic charging currents. Once again, the designed code transitions occur on successive integer LSB values. Output coding is straight (natural) binary with 1 LSB = FS/16384 = 2.5 V/16384 = 0.15 mV. Table II shows the ideal input/output transfer function for the AD7894-2. Table II. Ideal Input/Output Code Table for AD7894-2 Digital Output Analog Input1 Code Transition +FSR – 1 LSB2 111 . . . 110 to 111 . . . 111 +FSR – 2 LSB 111 . . . 101 to 111 . . . 110 +FSR – 3 LSB 111 . . . 100 to 111 . . . 101 GND + 3 LSB 000 . . . 010 to 000 . . . 011 GND + 2 LSB 000 . . . 001 to 000 . . . 010 GND + 1 LSB 000 . . . 000 to 000 . . . 001 NOTES 1FSR is full-scale range and is 2.5 V for AD7894-2 with VREF = +2.5 V. 21 LSB = FSR/16384 and is 0.15 mV for AD7894-2 with VREF = +2.5 V.

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AD7894 –7–REV. 0 Track/Hold Section The track/hold amplifier on the analog input of the AD7894 allows the ADC to accurately convert an input sine wave of full- scale amplitude to 14-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC, even when the ADC is operated at its maximum throughput rate of 160 kHz (i.e., the track/hold can handle input frequencies in excess of 100 kHz). The track/hold amplifier acquires an input signal to 14-bit accu- racy in less than 0.35␣ µs. The operation of the track/hold is essentially transparent to the user. With the high sampling operating mode the track/hold amplifier goes from its tracking mode to its hold mode at the start of conversion (i.e., the falling edge of CONVST). The aperture time for the track/hold (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) is typically 15␣ ns. At the end of conversion (on the falling edge of BUSY) the part re- turns to its tracking mode. The acquisition time of the track/ hold amplifier begins at this point. For the auto shutdown mode, the rising edge of CONVST wakes up the part and the track and hold amplifier goes from its tracking mode to its hold mode 5 µs after the rising edge of CONVST (provided that the CONVST high time is less than 5 µs). Once again the part re- turns to its tracking mode at the end of conversion when the BUSY signal goes low. Reference Input The reference input to the AD7894 is buffered on-chip with a maximum reference input current of 1␣ µA. The part is specified with a +2.5 V reference input voltage. Errors in the reference source will result in gain errors in the AD7894’s transfer func- tion and will add to the specified full-scale errors on the part. Suitable reference sources for the AD7894 include the AD780 and AD680 precision +2.5 V references. Timing and Control Section Figure 3 shows the timing and control sequence required to obtain optimum performance from the AD7894. In the se- quence shown, conversion is initiated on the falling edge of CONVST and new data from this conversion is available in the output register of the AD7894 5␣ µs later. Once the read opera- tion has taken place, a further 250␣ ns should be allowed before the next falling edge of CONVST to optimize the settling of the track/hold amplifier before the next conversion is initiated. With the serial clock frequency at its maximum of 16␣ MHz, the achievable throughput rate for the part is 5␣ µs (conversion time) plus 1.0␣ µs (read time) plus 250␣ ns (quiet time). This results in a minimum throughput time of 6.25␣ µs (equivalent to a throughput rate of 160 kHz). A serial clock of less than 16 MHz can be used, but this will in turn mean that the throughput time will increase. The read operation consists of 16 serial clock pulses to the output shift register of the AD7894. After 16 serial clock pulses the shift register is reset and the SDATA line is three-stated. If there are more serial clock pulses after the 16th clock, the shift register will be moved on past its reset state. However, the shift register will be reset again on the falling edge of the CONVST signal to ensure that the part returns to a known state every conversion cycle. As a result, a read operation from the output register should not straddle across the falling edge of CONVST as the output shift register will be reset in the middle of the read operation and the data read back into the microprocessor will appear invalid. OPERATING MODES Mode 1 Operation (High Sampling Performance) The timing diagram in Figure 3 is for optimum performance in operating Mode 1 where the falling edge of CONVST starts conversion and puts the Track/Hold amplifier into its hold mode. This falling edge of CONVST also causes the BUSY signal to go high to indicate that a conversion is taking place. The BUSY signal goes low when the conversion is complete, which is 5 µs max after the falling edge of CONVST and new data from this conversion is available in the output register of the AD7894. A read operation accesses this data. This read operation consists of 16 clock cycles and the length of this read operation will depend on the serial clock frequency. For the fastest throughput rate (with a serial clock of 16 MHz) the read operation will take 1.0 µs. The read operation must be com- plete at least 250 ns before the falling edge of the next CONVST and this gives a total time of 6.25 µs for the full throughput time (equivalent to 160 kHz). This mode of operation should be used for high sampling applications. 250ns MIN t1 = 40ns MIN tCONVERT = 5ms BUSY SCLK CONVST CONVERSION IS INITIATED; TRACK/HOLD GOES INTO HOLD CONVERSION ENDS 5ms LATER SERIAL READ OPERATION READ OPERATION SHOULD END 250ns PRIOR TO NEXT FALLING EDGE OF CONVST OUTPUT SERIAL SHIFT REGISTER IS RESET Figure 3. Mode 1 Timing Operation Diagram for High Sampling Performance

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AD7894 –8– REV. 0 250ns MIN BUSY SCLK CONVST CONVERSION IS INITIATED; TRACK/HOLD GOES INTO HOLD CONVERSION ENDS 10ms LATER SERIAL READ OPERATION READ OPERATION SHOULD END 250ns PRIOR TO NEXT RISING EDGE OF CONVST OUTPUT SERIAL SHIFT REGISTER IS RESET tCONVERT = 10ms PART WAKES UP Figure 4. Mode 2 Timing Diagram Where Automatic Sleep Function is Initiated t2 t3 t4 t5 t6 2 LEADING ZEROS THREE-STATE THREE- STATE 1 2 3 4 15 16 DB13 DB12 DB0 SCLK (I/P) DOUT (O/P) t2 = t3 = 31.25ns MIN, t4 = 60ns MAX, t5 = 10ns MIN, t6 = 20ns MAX @ 5V, A, B, VERSIONS Figure 5. Data Read Operation Mode 2 Operation (Auto Sleep After Conversion) The timing diagram in Figure 4 is for optimum performance in operating Mode 2, where the part automatically goes into sleep mode once BUSY goes low, after conversion and “wakes up” before the next conversion takes place. This is achieved by keep- ing CONVST low at the end of conversion, whereas it was high at the end of conversion for Mode 1 Operation. The rising edge of CONVST “wakes up” the AD7894. This wake-up time is typically 5 µs and is controlled internally by a monostable cir- cuit. While the AD7894 is waking up there is some digital activ- ity internal to the part. If the falling edge of CONVST (putting the track/hold amplifier into hold mode) should occur during this digital activity, noise will be injected into the track/hold amplifier resulting in a poor conversion. For optimum results the CONVST pulse should be between 40 ns and 2 µs or greater than 6 µs in width. The narrower pulse will allow a system to instruct the AD7894 to begin waking up and perform a conver- sion when ready, whereas the pulse greater than 6 µs will give control over when the sampling instant takes place. Note that the 10 µs wake-up time shown in Figure 4 is for a CONVST pulse less than 2 µs. If a CONVST pulse greater than 6 µs is used, the conversion will not complete for a further 5 µs after the falling edge of CONVST. Even though the part is in sleep mode, data can still be read from it. The read operation consists of 16 clock cycles as in Mode 1 Operation. For the fastest serial clock of 16 MHz, the read operation will take 1.0 µs and this must be complete at least 250 ns before the falling edge of the next CONVST, to allow the track/ hold amplifier to have enough time to settle. This mode is very useful when the part is converting at a slow rate, as the power consumption will be significantly reduced from that of Mode 1 Operation. Serial Interface The serial interface to the AD7894 consists of just three wires, a serial clock input (SCLK) and the serial data output (SDATA) and a conversion status output (BUSY). This allows for an easy-to-use interface to most microcontrollers, DSP processors and shift registers. Figure 5 shows the timing diagram for the read operation to the AD7894. The serial clock input (SCLK) provides the clock source for the serial interface. Serial data is clocked out from the SDATA line on the falling edge of this clock and is valid on both the rising and falling edges of SCLK. The advantage of having the data valid on both the rising and falling edges of the SCLK is to give the user greater flexibility in interfacing to the part and so a wider range of microprocessor and microcontrol- ler interfaces can be accommodated. This also explains the two timing figures, t4 and t5, that are quoted on the diagram. The time t4 specifies how long after the falling edge of the SCLK the next data bit becomes valid, whereas the time t5 specifies for how long after the falling edge of the SCLK the current data bit is valid. The first leading zero is clocked out on the first rising edge of SCLK. Note that the first zero will be valid on the first falling edge of SCLK even though the data access time is speci- fied at 60 ns for the other bits. The reason for this is that the first bit will be clocked out faster than the other bits is due to the internal architecture of the part. Sixteen clock pulses must be provided to the part to access to full conversion result. The AD7894 provides two leading zeros followed by the 14-bit conversion result starting with the MSB (DB13). The last data bit to be clocked out on the penultimate falling clock edge is the LSB (DB0). On the 16th falling edge of SCLK the LSB (DB0) will be valid for a specified time to allow the bit to be read on the falling edge of the SCLK and then the SDATA line is dis- abled (three-stated). After this last bit has been clocked out, the SCLK input should return low and remain low until the next serial data read operation. If there are extra clock pulses after the 16th clock, the AD7894 will start over again with outputting data from its output register and the data bus will no longer be three-stated even when the clock stops. Provided the serial clock has stopped before the next falling edge of

Page 10

AD7894 –9–REV. 0 CONVST, the AD7894 will continue to operate correctly with the output shift register being reset on the falling edge of CONVST. However, the SCLK line must be low when CONVST goes low in order to reset the output shift register correctly. The serial clock input does not have to be continuous during the serial read operation. The 16 bits of data (two leading zeros and 14-bit conversion result) can be read from the AD7894 in a number of bytes. The AD7894 counts the serial clock edges to know which bit from the output register should be placed on the SDATA out- put. To ensure that the part does not lose synchronization, the serial clock counter is reset on the falling edge of the CONVST input provided the SCLK line is low. The user should ensure that the SCLK line remains low until the end of the conversion. When the conversion is complete, BUSY goes low, the output register will be loaded with the new conversion result and can be read from with 16 clock cycles of SCLK. MICROPROCESSOR/MICROCONTROLLER INTERFACE The AD7894 provides a two-wire serial interface that can be used for connection to the serial ports of DSP processors and microcontrollers. Figures 6 through 9 show the AD7894 interfaced to a number of different microcontrollers and DSP processors. The AD7894 accepts an external serial clock and as a result, in all interfaces shown here, the processor/controller is configured as the master, providing the serial clock, with the AD7894 being the slave in the system. The BUSY signal need not be used for a two-wire interface if the read can be timed to occur 5 µs after the start of conversion (assuming Mode 1 operation). AD7894 to 8X51/L51 Interface Figure 6 shows an interface between the AD7894 and the 8X51/L51 microcontroller. The 8X51/L51 is configured for its Mode 0 serial interface mode. The diagram shows the simplest form of the interface where the AD7894 is the only part con- nected to the serial port of the 8X51/L51 and, therefore, no decoding of the serial read operations is required. To select the AD7894 in systems where more than one device is connected to the 8X51/L51’s serial port, a port bit, configured as an output from one of the 8X51/L51’s parallel ports, can be used to gate on or off the serial clock to the AD7894. A simple AND function on this port bit and the serial clock from the 8X51/L51 will provide this function. The port bit should be high to select the AD7894 and low when it is not selected. The end of conversion can be monitored by using the BUSY signal, which is shown in the interface diagram of Figure 6. With the BUSY line from the AD7894 connected to the Port P1.2 of the 8X51/L51 the BUSY line can be polled by the 8X51/L51. The BUSY line can be connected to the INT1 line of the 8X51/L51 if an interrupt driven system is preferred. These two options are shown on the diagram. Note also that the AD7894 outputs the MSB first during a read operation while the 8X51/L51 expects the LSB first. Therefore, the data that is read into the serial buffer needs to be rearranged before the correct data format from the AD7894 appears in the accumulator. The serial clock rate from the 8X51/L51 is limited to signifi- cantly less than the allowable input serial clock frequency with which the AD7894 can operate. As a result, the time to read data from the part will actually be longer than the conversion time of the part. This means that the AD7894 cannot run at its maximum throughput rate when used with the 8X51/L51. P1.2 OR INT1 P3.0 P3.1 SDATA BUSY SCLK AD78948X51/L51 Figure 6. AD7894 to 8X51/L51 Interface AD7894 to 68HC11/L11 Interface An interface circuit between the AD7894 and the 68HC11/L11 microcontroller is shown in Figure 7. For the interface shown, the 68L11 SPI port is used and the 68L11 is configured in its single-chip mode. The 68L11 is configured in the master mode with its CPOL bit set to a logic zero and its CPHA bit set to a logic one. As with the previous interface, the diagram shows the simplest form of the interface where the AD7894 is the only part connected to the serial port of the 68L11 and therefore no de- coding of the serial read operations is required. Once again, to select the AD7894 in systems where more than one device is connected to the 68HC11’s serial port, a port bit, configured as an output from one of the 68HC11’s parallel ports, can be used to gate on or off the serial clock to the AD7894. A simple AND function on this port bit and the serial clock from the 68L11 will provide this function. The port bit should be high to select the AD7894 and low when it is not selected. The end of conversion is monitored by using the BUSY signal, which is shown in the interface diagram of Figure 7. With the BUSY line from the AD7894 connected to the Port PC2 of the 68HC11/L11 the BUSY line can be polled by the 68HC11/L11. The BUSY line can be connected to the IRQ line of the 68HC11/ L11 if an interrupt driven system is preferred. These two op- tions are shown in the diagram. The serial clock rate from the 68HC11/L11 is limited to signifi- cantly less than the allowable input serial clock frequency with which the AD7894 can operate. As a result, the time to read data from the part will be longer than the conversion time of the part. This means that the AD7894 cannot run at its maximum throughput rate when used with the 68HC11/L11. PC2 OR IRQ SCK MISO SDATA BUSY SCLK AD789468HC11/L11 Figure 7. AD7894 to 68HC11/L11 Interface

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