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AD7940BRMZ-REEL7

hotAD7940BRMZ-REEL7

AD7940BRMZ-REEL7

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Part Number AD7940BRMZ-REEL7
Manufacturer Analog Devices Inc.
Description IC ADC 14BIT 100KSPS 8MSOP
Datasheet AD7940BRMZ-REEL7 Datasheet
Package 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
In Stock 4,000 piece(s)
Unit Price $ 7.1820 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 27 - Oct 2 (Choose Expedited Shipping)
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Part Number # AD7940BRMZ-REEL7 (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7940BRMZ-REEL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7940BRMZ-REEL7Datasheet
Package8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Series-
Number of Bits14
Sampling Rate (Per Second)100k
Number of Inputs1
Input TypeSingle Ended
Data InterfaceSPI, DSP
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeSupply
Voltage - Supply, Analog2.5 V ~ 5.5 V
Voltage - Supply, Digital2.5 V ~ 5.5 V
Features-
Operating Temperature-40°C ~ 85°C
Package / Case8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Supplier Device Package8-MSOP
Mounting Type-

AD7940BRMZ-REEL7 Datasheet

Page 1

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3 mW, 100 kSPS, 14-Bit ADC in 6-Lead SOT-23 AD7940 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. FEATURES Fast throughput rate: 100 kSPS Specified for VDD of 2.5 V to 5.5 V Low power 4 mW typ at 100 kSPS with 3 V supplies 17 mW typ at 100 kSPS with 5 V supplies Wide input bandwidth: 81 dB SINAD at 10 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible Standby mode: 0.5 µA max 6-Lead SOT-23 and 8-Lead MSOP packages APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Remote data acquisition systems FUNCTIONAL BLOCK DIAGRAM 03 30 5- 0- 00 1 VIN VDD GND AD7940 SCLK SDATA CS T/H 14-BIT SUCCESSIVE APPROXIMATION ADC CONTROL LOGIC Figure 1. Table 1. 16-Bit and 14-Bit ADC (MSOP and SOT-23) Type 100 kSPS 250 kSPS 500 kSPS 16-Bit True Differential AD7684 AD7687 AD7688 16-Bit Pseudo Differential AD7683 AD7685 AD7686 16-Bit Unipolar AD7680 14-Bit True Differential AD7944 AD7947 14-Bit Pseudo Differential AD7942 AD7946 14-Bit Unipolar AD7940 GENERAL DESCRIPTION The AD79401 is a 14-bit, fast, low power, successive approximation ADC. The part operates from a single 2.50 V to 5.5 V power supply and features throughput rates up to 100 kSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipelined delays associated with the part. The AD7940 uses advanced design techniques to achieve very low power dissipation at fast throughput rates. The reference for the part is taken internally from VDD, which allows the widest dynamic input range to the ADC. Thus, the analog input range for this part is 0 V to VDD. The conversion rate is determined by the SCLK frequency. 1Protected by US. Patent No. 6,681,332. This part features a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control. PRODUCT HIGHLIGHTS 1. First 14-bit ADC in a SOT-23 package. 2. High throughput with low power consumption. 3. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when a power-down mode is used while not converting. The part also features a shutdown mode to maximize power efficiency at lower throughput rates. Power consumption is 0.5 µA max when in shutdown. 4. Reference derived from the power supply. 5. No pipeline delay.

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AD7940 TABLE OF CONTENTS Table of Contents .............................................................................. 2  Specifications ..................................................................................... 3  Timing Specifications ....................................................................... 5  Absolute Maximum Ratings ............................................................ 6  ESD Caution .................................................................................. 6  Pin Configurations and Function Descriptions ........................... 7  Terminology ...................................................................................... 8  Typical Performance Characteristics ............................................. 9  Circuit Information ........................................................................ 11  Converter Operation .................................................................. 11  Analog Input ............................................................................... 11  ADC Transfer Function ................................................................. 12  Typical Connection Diagram ................................................... 12  Modes of Operation ....................................................................... 13  Normal Mode .............................................................................. 13  Power-Down Mode .................................................................... 14  Power vs. Throughput Rate ........................................................... 15  Serial Interface ................................................................................ 16  Microprocessor Interfacing ........................................................... 17  AD7940 to TMS320C541 .......................................................... 17  AD7940 to ADSP-218x .............................................................. 17  AD7940 to DSP563xx ................................................................ 18  Application Hints ........................................................................... 19  Grounding and Layout .............................................................. 19  Evaluating the AD7940 Performance ...................................... 19  Outline Dimensions ....................................................................... 20  Ordering Guide .......................................................................... 20  REVISION HISTORY 8/11—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 7/04—Revision 0: Initial Version

Page 4

AD7940 Rev. A | Page 3 of 20 SPECIFICATIONS1 VDD = 2.50 V to 5.5 V, fSCLK = 2.5 MHz, fSAMPLE = 100 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter B Version1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 10 kHz sine wave Signal-to-Noise + Distortion (SINAD)2 81 dB min Total Harmonic Distortion (THD)2 −98 dB typ Peak Harmonic or Spurious Noise (SFDR)2 −95 dB typ Intermodulation Distortion (IMD)2 Second-Order Terms −94 dB typ Third-Order Terms −100 dB typ Aperture Delay 20 ns max Aperture Jitter 30 ps typ Full Power Bandwidth 7 MHz typ @ −3 dB 2 MHz typ @ −0.1 dB DC ACCURACY Resolution 14 Bits min VDD = 2.5 V to 4.096 V 13 Bits min VDD > 4.096 V Integral Nonlinearity2 ±1 LSB max VDD = 2.5 V to 4.096 V ±2 LSB max VDD > 4.096 V Offset Error2 ±6 LSB max Gain Error2 ±8 LSB max ANALOG INPUT Input Voltage Ranges 0 to VDD V DC Leakage Current ±0.3 µA max Input Capacitance 30 pF typ LOGIC INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.4 V max VDD = 3 V 0.8 V max VDD = 5 V Input Current, IIN ±0.3 µA max Typically 10 nA, VIN = 0 V or VDD Input Capacitance, CIN 2, 3 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD – 0.2 V min ISOURCE = 200 µA; VDD = 2.50 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 µA Floating-State Leakage Current ±0.3 µA max Floating-State Output Capacitance2, 3 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 8 µs max 16 SCLK cycles Track-and-Hold Acquisition Time 500 ns max Full-scale step input 400 ns max Sine wave input ≤ 10 kHz Throughput Rate 100 kSPS max See the Serial Interface section POWER REQUIREMENTS VDD 2.50/5.5 V min/V max IDD Digital I/PS = 0 V or VDD Normal Mode (Static) 5.2 mA max VDD = 5.5 V; SCLK on or off 2 mA max VDD = 3.6 V; SCLK on or off Normal Mode (Operational) 4.8 mA max VDD = 5.5 V; fSAMPLE = 100 kSPS; 3.3 mA typ 1.9 mA max VDD = 3.6 V; fSAMPLE = 100 kSPS; 1.29 mA typ Full Power-Down Mode 0.5 µA max SCLK on or off. VDD = 5.5 V 0.3 µA max SCLK on or off. VDD = 3.6 V

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AD7940 Rev. A | Page 4 of 20 Parameter B Version1 Unit Test Conditions/Comments Power Dissipation4 VDD = 5.5 V Normal Mode (Operational) 26.4 mW max VDD = 5.5 V; fSAMPLE = 100 kSPS 6.84 mW max VDD = 3.6 V; fSAMPLE = 100 kSPS Full Power-Down 2.5 µW max VDD = 5.5 V 1.08 µW max VDD = 3.6 V 1 Temperature range for B Version is –40°C to +85°C. 2 See the Terminology section. 3 Sample tested at initial release to ensure compliance. 4 See the Power vs. Throughput Rate section.

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AD7940 Rev. A | Page 5 of 20 TIMING SPECIFICATIONS Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.50 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted. Table 3. Limit at TMIN, TMAX Parameter 3 V 5 V Unit Description fSCLK 1 250 250 kHz min 2.5 2.5 MHz max tCONVERT 16 × tSCLK 16 × tSCLK min tQUIET 50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 10 10 ns min Minimum CS pulse width t2 10 10 ns min CS to SCLK setup time t3 2 48 35 ns max Delay from CS until SDATA three-state disabled t4 2 120 80 ns max Data access time after SCLK falling edge t5 0.4 tSCLK 0.4 tSCLK ns min SCLK low pulse width t6 0.4 tSCLK 0.4 tSCLK ns min SCLK high pulse width t7 10 10 ns min SCLK to data valid hold time t8 3 45 35 ns max SCLK falling edge to SDATA high impedance tPOWER-UP 4 1 1 µs typ Power up time from full power-down 1 Mark/space ratio for the SCLK input is 40/60 to 60/40. 2 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 3 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 4 See the Power vs. Throughput Rate section. 03 30 5- 0- 00 2 200µA IOL 200µA IOH 1.6VTO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Digital Output Timing Specification

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AD7940 Rev. A | Page 6 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to GND −0.3 V to +7 V Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C SOT-23 Package, Power Dissipation 450 mW θJA Thermal Impedance 229.6°C/W θJC Thermal Impedance 91.99°C/W MSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 205.9°C/W θJC Thermal Impedance 43.74°C/W Lead Temperature, Soldering Vapor Phase (60 secs) 215°C Infared (15 secs) 220°C ESD 4 kV 1 Transient currents of up to 100 mA will not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

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AD7940 Rev. A | Page 7 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 03 30 5- 0- 02 3 CS SDATA SCLK 6 5 4 VDD 1 GND 2 VIN 3 AD7940 TOP VIEW (Not to Scale) SOT-23 Figure 3. SOT-23 Pin Configuration 033 05 -0 -0 03 NC = NO CONNECT AD7490 MSOP TOP VIEW (Not to Scale) VDD 1 GND 2 GND 3 VIN 4 CS SDATA NC SCLK 8 7 6 5 Figure 4. MSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. SOT-23 Pin No. MSOP Mnemonic Function 1 1 VDD Power Supply Input. The VDD range for the AD7940 is from 2.5 V to 5.5 V. 2 2, 3 GND Analog Ground. Ground reference point for all circuitry on the AD7940. All analog input signals should be referred to this GND voltage. 3 4 VIN Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. 4 5 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from this part. This clock input is also used as the clock source for the AD7940's conversion process. 5 7 SDATA Data Out. Logic output. The conversion result from the AD7940 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7940 consists of two leading zeros followed by 14 bits of conversion data that are provided MSB first. This will be followed by four trailing zeroes if CS is held low for a total of 24 SCLK cycles. See the Serial Interface section. 6 8 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7940 and framing the serial data transfer. N/A 6 NC No Connect. This pin should be left unconnected.

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AD7940 Rev. A | Page 8 of 20 TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB. Gain Error This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF − 1 LSB) after the offset error has been adjusted out. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of the conversion. See the Serial Interface section for more details. Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 14-bit converter, this is 86.04 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7940, it is defined as 1 2 6 2 5 2 4 2 3 2 2 V VVVVV log20(dB) ++++ =THD where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second- order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa −2fb). The AD7940 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.

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AD7940 Rev. A | Page 9 of 20 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 shows a typical FFT plot for the AD7940 at 100 kSPS sample rate and 10 kHz input frequency. Figure 6 shows the signal-to-(noise + distortion) ratio performance versus the input frequency for various supply voltages while sampling at 100 kSPS with an SCLK of 2.5 MHz. Figure 7 shows a graph of the total harmonic distortion versus the analog input frequency for various supply voltages, while Figure 8 shows a graph of the total harmonic distortion versus the analog input frequency for various source impedances (see the Analog Input section). Figure 9 and Figure 10 show the typical INL and DNL plots for the AD7940. 03 30 5- 0- 01 9 (d B ) –140 –120 –100 –80 –60 –40 –20 –160 0 10k 20k 30k 40k FREQUENCY (kHz) 50k 0 VDD = 4.75V FSAMPLE = 100kSPS FIN = 10kHz SNR = 84.48dB SINAD = 84.35dB THD = –98.97dB SFDR = –100.84dB Figure 5. AD7940 Dynamic Performance at 100 kSPS 03 30 5- 0- 02 0 SI N A D (d B ) 80 85 75 10 INPUT FREQUENCY (kHz) 100 90 FSAMPLE = 100kSPS TA = 25°C VDD = 5.25V VDD = 4.75V VDD = 2.5V VDD = 4.3V VDD = 3.6V VDD = 3V VDD = 2.7V Figure 6. AD7940 SINAD vs. Analog Input Frequency for Various Supply Voltages at 100 kSPS 03 30 5- 0- 02 1 TH D (d B ) 90 100 80 10 INPUT FREQUENCY (kHz) 100 110 85 95 105 FSAMPLE = 100kSPS TA = 25°C VDD = 3V VDD = 2.7V VDD = 4.3V VDD = 2.5V VDD = 5.25V VDD = 4.75V VDD = 3.6V Figure 7. AD7940 THD vs. Analog Input Frequency for Various Supply Voltages at 100 kSPS 03 30 5- 0- 02 2 TH D (d B ) 90 100 70 75 10 INPUT FREQUENCY (kHz) 100 110 85 80 95 105 FSAMPLE = 100kSPS TA = 25°C VDD = 4.75V RIN = 10Ω RIN = 50Ω RIN = 100Ω RIN = 1000Ω Figure 8. AD7940 THD vs. Analog Input Frequency for Various Source Impedances

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Roc*****Diaz

August 17, 2020

good item, quick delivery, prefer to recommended.

Natal*****kherjee

August 16, 2020

It fit exactly in the same location as the original. Works great and no problem. Good purchase.

Rosi*****odman

July 26, 2020

Worked like it was intended.

Xande*****nington

July 26, 2020

Can't speak to the long term reliability as of yet, but they seem to be of decent quality and I don't expect any issues.

Brin*****Magar

July 23, 2020

High level customer service, and quick response.

Eme*****d Orr

July 21, 2020

Work great, great price, I use a lot of them for battery chargers, not the first time ordered.

Heave*****eynolds

July 20, 2020

Superb pricing and super fast delivery.

Kama*****esai

July 12, 2020

So far so good. I need to see how they hold up.

Kayl*****yala

July 10, 2020

Very Quick,no problems - Thank you.

Corin*****hultz

July 5, 2020

I had no problems with this product. Would I recommend it. Yes.

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