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AD7943BRZ

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AD7943BRZ

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Part Number AD7943BRZ
Manufacturer Analog Devices Inc.
Description IC DAC 12BIT MULT SRL 16SOIC
Datasheet AD7943BRZ Datasheet
Package 16-SOIC (0.295", 7.50mm Width)
In Stock 13,044 piece(s)
Unit Price $ 10.7300 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jan 24 - Jan 29 (Choose Expedited Shipping)
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Part Number # AD7943BRZ (Data Acquisition - Digital to Analog Converters (DAC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7943BRZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet AD7943BRZDatasheet
Package16-SOIC (0.295", 7.50mm Width)
Series-
Number of Bits12
Number of D/A Converters1
Settling Time600µs (Typ)
Output TypeCurrent - Unbuffered
Differential OutputNo
Data InterfaceSerial
Reference TypeExternal
Voltage - Supply, Analog5V
Voltage - Supply, Digital5V
INL/DNL (LSB)±0.5 (Max), ±0.5 (Max)
ArchitectureR-2R
Operating Temperature-40°C ~ 85°C
Package / Case16-SOIC (0.295", 7.50mm Width)
Supplier Device Package16-SOIC
Mounting Type-

AD7943BRZ Datasheet

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FUNCTIONAL BLOCK DIAGRAMS VDD RFB DGND AD7948 DB7–DB0 DF/DOR CTRL LDAC WR CSLSB CSMSB IOUT1 AGND VREF 12-BIT DAC 12 12 DATA OVERRIDE LOGIC 12 DAC REGISTER 12 INPUT REGISTERS CONTROL LOGIC DATA STEERING LOGIC 8 CS WR VDD RFB IOUT1 AGND VREF DGNDDB11–DB0 AD7945 12-BIT DAC 12 INPUT LATCH 12 AD7943 VDD RFB IOUT1 AGND IOUT2 SRO STB1 DGNDSTB2 STB3 STB4 CLR LD1 LD2 SRI VREF 12-BIT DAC DAC REGISTER INPUT SHIFT REGISTER REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a +3.3 V/+5 V Multiplying12-Bit DACs AD7943/AD7945/AD7948 FEATURES 12-Bit Multiplying DACs Guaranteed Specifications with +3.3 V/+5 V Supply 0.5 LSBs INL and DNL Low Power: 5 mW typ Fast Interface 40 ns Strobe Pulsewidth (AD7943) 40 ns Write Pulsewidth (AD7945, AD7948) Low Glitch: 60 nV-s with Amplifier Connected Fast Settling: 600 ns to 0.01% with AD843 APPLICATIONS Battery-Powered Instrumentation Laptop Computers Upgrades for All 754x Series DACs (5 V Designs) GENERAL DESCRIPTION The AD7943, AD7945 and AD7948 are fast 12-bit multiplying DACs that operate from a single +5 V supply (Normal Mode) and a single +3.3 V to +5 V supply (Biased Mode). The AD7943 has a serial interface, the AD7945 has a 12-bit parallel interface, and the AD7948 has an 8-bit byte interface. They will replace the industry-standard AD7543, AD7545 and AD7548 in many applications, and they offer superior speed and power consumption performance. The AD7943 is available in 16-lead DIP, 16-lead SOP (Small Outline Package) and 20-lead SSOP (Shrink Small Outline Package). The AD7945 is available in 20-lead DIP, 20-lead SOP and 20- lead SSOP. The AD7948 is available in 20-lead DIP, 20-lead SOP and 20- lead SSOP. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998

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REV. B–2– AD7943/AD7945/AD7948–SPECIFICATIONS1 Parameter B Grades2 T Grade2, 3 Units Test Conditions/Comments ACCURACY Resolution 12 12 Bits 1 LSB = VREF/2 12 = 2.44 mV when VREF = 10 V Relative Accuracy ±0.5 ±0.5 LSB max Differential Nonlinearity ±0.5 ±0.5 LSB max All Grades Guaranteed Monotonic over Temperature Gain Error TMIN to TMAX ±2 ±2 LSB max Gain Temperature Coefficient4 2 2 ppm FSR/°C typ 5 5 ppm FSR/°C max Output Leakage Current IOUT1 @ +25°C 10 10 nA max See Terminology Section TMIN to TMAX 100 100 nA max Typically 20 nA over Temperature REFERENCE INPUT Input Resistance 6 6 kΩ min Typical Input Resistance = 9 kΩ 12 12 kΩ max DIGITAL INPUTS VINH, Input High Voltage 2.4 2.4 V min VINL, Input Low Voltage 0.8 0.8 V max IINH, Input Current ±1 ±1 µA max CIN, Input Capacitance 4 10 10 pF max DIGITAL OUTPUT (AD7943 SRO) For 1 CMOS Load Output Low Voltage (VOL) 0.2 0.2 V max Output High Voltage (VOH) VDD – 0.2 VDD – 0.2 V min POWER REQUIREMENTS VDD Range 4.5/5.5 4.5/5.5 V min/V max Power Supply Sensitivity4 ∆Gain/∆VDD –75 –75 dB typ IDD (AD7943) 5 5 µA max VINH = VDD – 0.1 V min, VINL = 0.1 V max. SRO Open Circuit. No STB Signal. Typically 1 µA. Typically 100 µA with a 1 MHz STB Frequency. At Input Levels of 0.8 V and 2.4 V, IDD Is Typically 2.5 mA. IDD (AD7945, AD7948) 5 5 µA max VINH = VDD – 0.1 V min, VINL = 0.1 V max. Typically 1 µA. At Input Levels of 0.8 V and 2.4 V, IDD Is Typically 2.5 mA. NOTES 1The AD7943, AD7945 and AD7948 are specified in the normal current mode configuration and in the biased current mode for single-supply applications. Figures 14 and 15 are examples of normal mode operation. 2Temperature ranges as follows: B Grades: –40°C to +85°C; T Grade: –55°C to +125°C. 3The T Grade applies to the AD7945 only. 4Guaranteed by design. Specifications subject to change without notice. NORMAL MODE (AD7943: VDD = +4.5 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX, unless otherwise noted. AD7945, AD7948: VDD = +4.5 V to +5.5 V; VIOUT1 = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX, unless otherwise noted.)

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AD7943/AD7945/AD7948 REV. B –3– Parameter A Grades2 Units Test Conditions/Comments ACCURACY Resolution 12 Bits 1 LSB = (VIOUT1 – VREF)/2 12 = 300 µV When VIOUT1 = 1.23 V and VREF = 0 V Relative Accuracy ±1 LSB max Differential Nonlinearity ±0.9 LSB max All Grades Guaranteed Monotonic over Temperature Gain Error @ +25°C ±3 LSB max TMIN to TMAX ±4 LSB max Gain Temperature Coefficient3 2 ppm FSR/°C typ 5 ppm FSR/°C max Output Leakage Current See Terminology Section IOUT1 @ +25°C 10 nA max TMIN to TMAX 100 nA max Typically 20 nA over Temperature Input Resistance This Varies with DAC Input Code @ IOUT2 Pin (AD7943) 6 kΩ min @ AGND Pin (AD7945, AD7948) 6 kΩ min DIGITAL INPUTS VINH, Input High Voltage @ VDD = +5 V 2.4 V min VINH, Input High Voltage @ VDD = +3.3 V 2.1 V min VINL, Input Low Voltage @ VDD = +5 V 0.8 V max VINL, Input Low Voltage @ VDD = +3.3 V 0.6 V max IINH, Input Current ±1 µA max CIN, Input Capacitance 3 10 pF max DIGITAL OUTPUT (SRO) For 1 CMOS Load Output Low Voltage (VOL) 0.2 V max Output High Voltage (VOH) VDD – 0.2 V min POWER REQUIREMENTS VDD Range 3.0/5.5 V min/V max Power Supply Sensitivity3 ∆Gain/∆VDD –75 dB typ IDD (AD7943) 5 µA max VINH = VDD – 0.1 V min, VINL = 0.1 V max. SRO Open Circuit; No STB Signal; Typically 1 µA. Typically 100 µA with 1 MHz STB Frequency. IDD (AD7945, AD7948) 5 µA max VINH = VDD – 0.1 V min, VINL = 0.1 V max. Typically 1 µA. NOTES 1These specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a “–B” suffix (for example: AD7943AN-B). Figure 16 is an example of Biased Mode Operation. 2Temperature ranges as follows: A Versions: –40°C to +85°C. 3Guaranteed by design. Specifications subject to change without notice. BIASED MODE SPECIFICATIONS1 (AD7943: VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 1.23 V; VREF = +0 V to 2.45 V; TA = TMIN to TMAX, unless other- wise noted. AD7945, AD7948: VDD = +3 V to +5.5 V; VIOUT1 = AGND = 1.23 V; VREF = +0 V to 2.45 V; TA = TMIN to TMAX, unless otherwise noted.)

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AD7943/AD7945/AD7948 REV. B–4– AC PERFORMANCE CHARACTERISTICS NORMAL MODE Parameter B Grades T Grade Units Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 600 700 ns typ To 0.01% of Full-Scale Range. VREF = +10 V; DAC Latch Alternately Loaded with All 0s and All 1s Digital to Analog Glitch Impulse 60 60 nV-s typ Measured with VREF = 0 V. DAC Latch Alternately Loaded with All 0s and All 1s Multiplying Feedthrough Error –75 –75 dB max DAC Latch Loaded with All 0s Output Capacitance 60 60 pF max All 1s Loaded to DAC 30 30 pF max All 0s Loaded to DAC Digital Feedthrough (AD7943) 5 5 nV-s typ Feedthrough to the DAC Output with LD1, LD2 High and Alternate Loading of All 0s and All 1s into the Input Shift Register Digital Feedthrough (AD7945, AD7948) 5 5 nV-s typ Feedthrough to the DAC Output with CS High and Alternate Loading of All 0s and All 1s to the DAC Bus Total Harmonic Distortion –83 –83 dB typ Output Noise Spectral Density @ 1 kHz 35 35 nV/√Hz typ All 1s Loaded to DAC. VREF = 0 V. Output Op Amp Is OP07 Specifications subject to change without notice. (AD7943: VDD = +4.5 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 0 V. AD7945, AD7948: VDD = +4.5 V to +5.5 V; VIOUT1 =AGND = 0 V. VREF = 6 V rms, 1 kHz sine wave; TA = TMIN to TMAX; DAC output op amp is AD843; unless otherwise noted.) These characteristics are in- cluded for Design Guidance and are not subject to test. AC PERFORMANCE CHARACTERISTICS BIASED MODE (AD7943: VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 1.23 V. AD7945, AD7948: VDD = +3 V to +5.5 V; VIOUT1 = AGND = 1.23 V. VREF = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC output op amp is AD820; TA = TMIN to TMAX; unless otherwise noted.) These characteristics are included for Design Guidance and are not subject to test. Parameter A Grades Units Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 5 µs typ To 0.01% of Full-Scale Range. VREF = 0 V DAC Latch Alternately Loaded with All 0s and All 1s Digital to Analog Glitch Impulse 60 nV-s typ VREF = 1.23 V. DAC Register Alternately Loaded with All 0s and All 1s Multiplying Feedthrough Error –75 dB max DAC Latch Loaded with All 0s Output Capacitance 60 pF max All 1s Loaded to DAC 30 pF max All 0s Loaded to DAC Digital Feedthrough 5 nV-s typ Feedthrough to the DAC Output with LD1, LD2 High and Alternate Loading of All 0s and All 1s into the Input Shift Register Digital Feedthrough (AD7945, AD7948) 5 nV-s typ Feedthrough to the DAC Output with CS High and Alternate Loading of All 0s and All 1s to the DAC Bus Total Harmonic Distortion –83 dB typ Output Noise Spectral Density @ 1 kHz 25 nV/√Hz typ All 1s Loaded to DAC. VREF = 1.23 V Specifications subject to change without notice.

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AD7943/AD7945/AD7948 REV. B –5– (TA = TMIN to TMAX, unless otherwise noted) Limit @ Limit @ Parameter VDD = +3 V to +3.6 V VDD = +4.5 V to +5.5 V Units Description tSTB 2 60 40 ns min STB Pulsewidth tDS 15 10 ns min Data Setup Time tDH 35 25 ns min Data Hold Time tSRI 55 35 ns min SRI Data Pulsewidth tLD 55 35 ns min Load Pulsewidth tCLR 55 35 ns min CLR Pulsewidth tASB 0 0 ns min Min Time Between Strobing Input Shift Register and Loading DAC Register tSV 3 60 35 ns max STB Clocking Edge to SRO Data Valid Delay NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 µs on any digital input. 2STB mark/space ratio range is 60/40 to 40/60. 3tSV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. Specifications subject to change without notice. tSTB STB1, STB2, STB4 STB3 tDS tDH tSRI SRI DB11(N) (MSB) DB10(N) DB0(N) DB0(N–1)DB10(N–1) LD1, LD2, CLR SRO tSV tLD, tCLR tASB Figure 1. AD7943 Timing Diagram TO OUTPUT PIN CL 50pF 1.6mA IOL +2.1V IOH200mA Figure 2. Load Circuit for Digital Output Timing Specifications AD7943 TIMING SPECIFICATIONS1

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AD7943/AD7945/AD7948 REV. B–6– AD7945 TIMING SPECIFICATIONS1 (TA = TMIN to TMAX, unless otherwise noted) Limit @ Limit @ Parameter VDD = +3 V to +3.6 V VDD = +4.5 V to +5.5 V Units Description tDS 35 20 ns min Data Setup Time tDH 10 10 ns min Data Hold Time tCS 60 40 ns min Chip Select Setup Time tCH 0 0 ns min Chip Select Hold Time tWR 60 40 ns min Write Pulsewidth NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. DATA VALID CS tCH tDS tDH WR DB11–DB0 tCS tWR Figure 3. AD7945 Timing Diagram AD7948 TIMING SPECIFICATIONS1 (TA = TMIN to TMAX, unless otherwise noted) Limit @ Limit @ Parameter VDD = +3 V to +3.6 V VDD = +4.5 V to +5.5 V Units Description tDS 45 30 ns min Data Setup Time tDH 10 10 ns min Data Hold Time tCWS 0 0 ns min CSMSB or CSLSB to WR Setup Time tCWH 0 0 ns min CSMSB or CSLSB to WR Hold Time tLWS 0 0 ns min LDAC to WR Setup Time tLWH 0 0 ns min LDAC to WR Hold Time tWR 60 40 ns min Write Pulsewidth NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. DATA VALID DATA VALID WR tCWS tCWH tCWS tCWH tLWHtLWS tDH tDS tWR tWR tDH tDS CSMSB CSLSB LDAC DB7–DB0 Figure 4. AD7948 Timing Diagram

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AD7943/AD7945/AD7948 REV. B –7– ORDERING GUIDE Temperature Linearity Nominal Package Model Range Error (LSBs) Supply Voltage Option1 AD7943BN –40°C to +85°C ±0.5 +5 V N-16 AD7943BR –40°C to +85°C ±0.5 +5 V R-16 AD7943BRS –40°C to +85°C ±0.5 +5 V RS-20 AD7943AN-B –40°C to +85°C ±1 +3.3 V to +5 V N-16 AD7943ARS-B –40°C to +85°C ±1 +3.3 V to +5 V RS-20 AD7945BN –40°C to +85°C ±0.5 +5 V N-20 AD7945BR –40°C to +85°C ±0.5 +5 V R-20 AD7945BRS –40°C to +85°C ±0.5 +5 V RS-20 AD7945AN-B –40°C to +85°C ±1 +3.3 V to +5 V N-20 AD7945ARS-B –40°C to +85°C ±1 +3.3 V to +5 V RS-20 AD7945TQ –55°C to +125°C ±1 +5 V Q-20 AD7948BN –40°C to +85°C ±0.5 +5 V N-20 AD7948BR –40°C to +85°C ±0.5 +5 V R-20 AD7948BRS –40°C to +85°C ±0.5 +5 V RS-20 AD7948AN-B –40°C to +85°C ±1 +3.3 V to +5 V N-20 AD7948ARS-B –40°C to +85°C ±1 +3.3 V to +5 V RS-20 NOTE 1N = Plastic DIP; R = SOP (Small Outline Package); RS = SSOP (Shrink Small Outline Package); Q = Cerdip. ABSOLUTE MAXIMUM RATINGS1 (TA = +25°C unless otherwise noted) VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V IOUT1 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V IOUT2 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA Operating Temperature Range Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C DIP Package, Power Dissipation . . . . . . . . . . . . . . . . 670 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W Lead Temperature, Soldering, (10 sec) . . . . . . . . . . +260°C SOP Package, Power Dissipation . . . . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C SSOP Package, Power Dissipation . . . . . . . . . . . . . . . . 875 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 132°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Transient currents of up to 100 mA will not cause SCR latch-up. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7943/AD7945/AD7948 feature proprietary ESD protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

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AD7943/AD7945/AD7948 REV. B–8– TERMINOLOGY Relative Accuracy Relative Accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits or as a percentage of full- scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Gain Error Gain Error is a measure of the output error between an ideal DAC and the actual device output. It is measured with all 1s in the DAC after offset error has been adjusted out and is ex- pressed in Least Significant Bits. Gain error is adjustable to zero with an external potentiometer. Output Leakage Current Output leakage current is current which flows in the DAC lad- der switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance This is the capacitance from the IOUT1 pin to AGND. Output Voltage Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified both with the AD843 as the output op amp in the normal current mode and with the AD820 in the biased current mode. Digital to Analog Glitch Impulse This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nV-s. It is measured with the reference input connected to AGND and the digital inputs toggled between all 1s and all 0s. As with Settling Time, it is specified with both the AD817 and the AD820. AC Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are loaded in the DAC. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs is capacitively coupled through the device to show up as noise on the IOUT1 pin and subsequently on the op amp output. This noise is digital feedthrough. PIN CONFIGURATIONS DIP/SOP SSOP DIP/SOP/SSOP DIP/SOP/SSOP 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 TOP VIEW (Not to Scale) AD7945 DB5 DB6 DB7 AGND DGND DB11 DB8 DB9 DB10 DB4 DB3 DB2 VREF VDD WR DB1 DB0 CS IOUT1 RFB TOP VIEW (Not to Scale) AD7943 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IOUT1 IOUT2 AGND STB1 LD1 SRO SRI STB2 RFB VREF VDD CLR DGND STB4 STB3 LD2 TOP VIEW (Not to Scale) AD7943 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 NC = NO CONNECT STB2 SRI SRO IOUT2 AGND STB1 LD1 NC NC LD2 STB3 STB4 VREF VDD CLR DGND NC NC IOUT1 RFB TOP VIEW (Not to Scale) AD7948 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10DB4 DB5 DB6 AGND DGND CSMSB DB7 (MSB) CTRL DF/DOR DB3 DB2 DB1 VREF VDD WR DB0 (LSB) LDAC CSLSB IOUT1 RFB

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AD7943/AD7945/AD7948 REV. B –9– AD7943 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description IOUT1 DAC current output terminal 1. IOUT2 DAC current output terminal 2. This should be connected to the AGND pin. AGND This pin connects to the back gates of the current steering switches. In normal operation, it should be connected to the signal ground of the system. In biased single-supply operation it may be biased to some voltage between 0 V and the 1.23 V. See Figure 11 for more details. STB1 This is the Strobe 1 input. Data is clocked into the input shift register on the rising edge of this signal. STB3 must be high. STB2, STB4 must be low. LD1, LD2 Active low inputs. When both of these are low, the DAC register is updated and the output will change to reflect this. SRI Serial Data Input. Data on this line will be clocked into the input shift register on one of the Strobe inputs, when they are enabled. STB2 This is the Strobe 2 input. Data is clocked into the input shift register on the rising edge of this signal. STB3 must be high. STB1, STB4 must be low. STB3 This is the Strobe 3 input. Data is clocked into the input shift register on the falling edge of this signal. STB1, STB2, STB4, must be low. STB4 This is the Strobe 4 input. Data is clocked into the input shift register on the rising edge of this signal. STB3 must be high. STB1, STB2 must be low. DGND Digital Ground. CLR Asynchronous CLR input. When this input is taken low, all 0s are loaded to the DAC latch. VDD Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode Operation. VREF DAC reference input. RFB DAC feedback resistor pin. AD7945 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description IOUT1 DAC current output terminal 1. AGND This pin connects to the back gates of the current steering switches. The DAC IOUT2 terminal is also connected internally to this point. DGND Digital Ground. DB11–DB0 Digital Data Inputs. CS Active Low, Chip Select Input. WR Active Low, Write Input. VDD Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode Operation. VREF DAC reference input. RFB DAC feedback resistor pin.

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AD7943BRZ

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Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

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