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AD7998BRUZ-0REEL

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AD7998BRUZ-0REEL

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Part Number AD7998BRUZ-0REEL
Manufacturer Analog Devices Inc.
Description IC ADC 12BIT 8CHAN I2C 20TSSOP
Datasheet AD7998BRUZ-0REEL Datasheet
Package 20-TSSOP (0.173", 4.40mm Width)
In Stock 16,948 piece(s)
Unit Price $ 6.0529 *
Lead Time Can Ship Immediately
Estimated Delivery Time Oct 27 - Nov 1 (Choose Expedited Shipping)
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Part Number # AD7998BRUZ-0REEL (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7998BRUZ-0REEL Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7998BRUZ-0REELDatasheet
Package20-TSSOP (0.173", 4.40mm Width)
Series-
Number of Bits12
Sampling Rate (Per Second)188k
Number of Inputs8
Input TypeSingle Ended
Data InterfaceI2C
ConfigurationMUX-S/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeExternal
Voltage - Supply, Analog2.7 V ~ 5.5 V
Voltage - Supply, Digital2.7 V ~ 5.5 V
Features-
Operating Temperature-40°C ~ 85°C
Package / Case20-TSSOP (0.173", 4.40mm Width)
Supplier Device Package20-TSSOP
Mounting Type-

AD7998BRUZ-0REEL Datasheet

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8-Channel, 10- and 12-Bit ADCs with I2C- Compatible Interface in 20-Lead TSSOP AD7997/AD7998 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES 10- and 12-bit ADC with fast conversion time: 2 µs typ 8 single-ended analog input channels Specified for VDD of 2.7 V to 5.5 V Low power consumption Fast throughput rate: up to 188 kSPS Sequencer operation Automatic cycle mode I2C®-compatible serial interface supports standard, fast, and high speed modes Out-of-range indicator/alert function Pin-selectable addressing via AS Shutdown mode: 1 µA max Temperature range: −40°C to +85°C 20-lead TSSOP package See the AD7992 and AD7994 for 2-channel and 4-channel equivalent devices, respectively GENERAL DESCRIPTION The AD7997/AD7998 are 8-channel, 10- and 12-bit, low power, successive approximation ADCs with an I2C-compatible interface. The parts operate from a single 2.7 V to 5.5 V power supply and feature a 2 µs conversion time. The parts contain an 8-channel multiplexer and track-and-hold amplifier that can handle input frequencies up to 11 MHz. The AD7997/AD7998 provide a 2-wire serial interface that is compatible with I2C interfaces. Each part comes in two versions, AD7997-0/AD7998-0 and AD7997-1/AD7998-1, and each version allows at least two different I2C addresses. The I2C interface on the AD7997-0/AD7998-0 supports standard and fast I2C interface modes. The I2C interface on the AD7997-1/ AD7998-1 supports standard, fast, and high speed I2C interface modes. The AD7997/AD7998 normally remain in a shutdown state while not converting, and power up only for conversions. The conversion process can be controlled using the CONVST pin, by a command mode where conversions occur across I2C write operations or an automatic conversion interval mode selected through software control. The AD7997/AD7998 require an external reference that should be applied to the REFIN pin and can be in the range of 1.2 V to VDD. This allows the widest dynamic input range to the ADC. FUNCTIONAL BLOCK DIAGRAM VIN1 10-/12-BIT SUCCESSIVE APPROXIMATION ADC CONTROL LOGIC8:1 I/P MUX AD7997/AD7998 VDD SCL I2C INTERFACE CYCLE TIMER REGISTER ALERT STATUS REGISTER CONFIGURATION REGISTER CONVERSION RESULT REGISTER SDA AGND ALERT/BUSY CONVSTAGND AS OSCILLATOR REFIN VIN8 DATALOWLIMIT REGISTER CH1–CH4 T/H DATAHIGHLIMIT REGISTER CH1–CH4 HYSTERESIS REGISTER CH1–CH4 0 3 4 7 3 -0 -0 0 1 Figure 1. On-chip limit registers can be programmed with high and low limits for the conversion result, and an open-drain, out-of- range indicator output (ALERT) becomes active when the programmed high or low limits are violated by the conversion result. This output can be used as an interrupt. PRODUCT HIGHLIGHTS 1. 2 µs conversion time with low power consumption. 2. I2C-compatible serial interface with pin-selectable addresses. Two AD7997/AD7998 versions allow five AD7997/AD7998 devices to be connected to the same serial bus. 3. The parts feature automatic shutdown while not converting to maximize power efficiency. Current consumption is 1 µA max when in shutdown mode at 3V. 4. Reference can be driven up to the power supply. 5. Out-of-range indicator that can be software disabled or enabled. 6. One-shot and automatic conversion rates. 7. Registers store minimum and maximum conversion results.

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AD7997/AD7998 Rev. 0 | Page 2 of 32 TABLE OF CONTENTS AD7997 Specifications..................................................................... 3 AD7998 Specifications..................................................................... 5 I2C Timing Specifications ................................................................ 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Pin Function Descriptions.................... 10 Terminology .................................................................................... 11 Typical Performance Characteristics ........................................... 12 Circuit Information ........................................................................ 15 Converter Operation.................................................................. 15 Typical Connection Diagram ................................................... 16 Analog Input ............................................................................... 16 Internal Register Structure ............................................................ 18 Address Pointer Register ........................................................... 18 Configuration Register .............................................................. 19 Conversion Result Register ....................................................... 20 Limit Registers ............................................................................ 20 Alert Status Register (CH1 to CH4) ........................................ 21 Cycle Timer Register.................................................................. 22 Sample Delay and Bit Trial Delay............................................. 22 Serial Interface ................................................................................ 23 Serial Bus Address ...................................................................... 23 Writing to the AD7997/AD7998 .................................................. 24 Writing to the Address Pointer Register for a Subsequent Read.............................................................................................. 24 Writing a Single Byte of Data to the Alert Status Register or Cycle Register.............................................................................. 24 Writing Two Bytes of Data to a Limit, Hysteresis, or Configuration Register .............................................................. 24 Reading Data from the AD7997/AD7998................................... 26 ALERT/BUSY Pin .......................................................................... 27 SMBus ALERT ............................................................................ 27 BUSY............................................................................................ 27 Placing the AD7997-1/AD7998-1 into High Speed Mode ... 27 The Address Select (AS) Pin ..................................................... 27 Modes of Operation ....................................................................... 28 Mode 1—Using the CONVST Pin ........................................... 28 Mode 2 – COMMAND MODE ............................................... 29 Mode 3—Automatic Cycle Interval Mode.............................. 30 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31 Related Parts in I2C-Compatible ADC Product Family........ 31 REVISION HISTORY 9/04—Revision 0: Initial Version

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AD7997/AD7998 Rev. 0 | Page 3 of 32 AD7997 SPECIFICATIONS Temperature range for B version is −40°C to +85°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7997-0, all specifications apply for fSCL up to 400 kHz; for the AD7997-1, all specifications apply for fSCL up to 3.4 MHz, unless otherwise noted; TA = TMIN to TMAX. Table 1. Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 FIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz FIN = 1 kHz sine wave for fSCL up to 400 kHz Signal to Noise + Distortion (SINAD)2 61 dB min Total Harmonic Distortion (THD) 2 –75 dB max Peak Harmonic or Spurious Noise (SFDR) 2 –76 dB max Intermodulation Distortion (IMD)2 fa = 10.1 kHz, fb = 9.9 kHz for fSCL from 1.7 MHz to 3.4 MHz fa = 1.1 kHz, fb = 0.9 kHz for fSCL up to 400 kHz Second-Order Terms –86 dB typ Third-Order Terms –86 dB typ Aperture Delay2 10 ns max Aperture Jitter2 50 ps typ Channel-to-Channel Isolation2 –90 dB typ FIN = 108 Hz, see the Terminology section Full-Power Bandwidth2 11 MHz typ @ 3 dB 2 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits Integral Nonlinearity1, 2 ±0.5 LSB max Differential Nonlinearity1, 2 ±0.5 LSB max Guaranteed no missed codes to 10 bits Offset Error2 ±1.5 LSB max Mode 1 (CONVST Mode) ±2.5 LSB max Mode 2 (Command Mode) Offset Error Match2 ±0.5 LSB max Gain Error2 ±1.5 LSB max Gain Error Match2 ±0.5 LSB max ANALOG INPUT Input Voltage Range 0 to REFIN V DC Leakage Current ±1 µA max Input Capacitance 30 pF typ REFERENCE INPUT REFIN Input Voltage Range 1.2 to VDD V min/V max DC Leakage Current ±1 µA max Input Impedance 69 kΩ typ During a conversion LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH 0.7 (VDD) V min Input Low Voltage, VINL 0.3 (VDD) V max Input Leakage Current, IIN ±1 µA max VIN = 0 V or VDD Input Capacitance, CIN 3 10 pF max Input Hysteresis, VHYST 0.1 (VDD) V min

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AD7997/AD7998 Rev. 0 | Page 4 of 32 Parameter B Version Unit Test Conditions/Comments LOGIC INPUTS (CONVST) Input High Voltage, VINH 2.4 V min VDD = 5 V 2.0 V min VDD = 3 V Input Low Voltage, VINL 0.8 V max VDD = 5 V 0.4 V max VDD = 3 V Input Leakage Current, IIN ±1 µA max VIN = 0 V or VDD Input Capacitance, CIN3 10 pF max LOGIC OUTPUTS (OPEN-DRAIN) Output Low Voltage, VOL 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Floating-State Leakage Current ± 1 µA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE See the Modes of Operation section Conversion Time 2 µs typ Throughput Rate Mode 1 (Reading after the Conversion) 5 kSPS typ fSCL = 100 kHz 21 kSPS typ fSCL = 400 kHz 121 kSPS typ fSCL = 3.4 MHz Mode 2 5.5 kSPS typ fSCL = 100 kHz 22 kSPS typ fSCL = 400 kHz 147 kSPS typ fSCL = 3.4 MHz, 188 kSPS typ @ 5 V POWER REQUIREMENTS VDD 2.7/5.5 V min/max IDD Digital inputs = 0 V or VDD Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 Mode 3 (I2C Inactive, TCONVERT x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V Power Dissipation Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz fSCL 1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 Power Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V 1 Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C Hs-Mode SCL frequencies. Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled. 2 See the Terminology section. 3 Guaranteed by initial characterization.

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AD7997/AD7998 Rev. 0 | Page 5 of 32 AD7998 SPECIFICATIONS Temperature range for B version is −40°C to +85°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7998-0, all specifications apply for fSCL up to 400 kHz; for the AD7998-1, all specifications apply for fSCL up to 3.4 MHz, unless otherwise noted; TA = TMIN to TMAX. Table 2. Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 FIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz FIN = 1 kHz sine wave for fSCL up to 400 kHz Signal-to-Noise + Distortion (SINAD)2 70.5 dB min Signal to Noise Ratio (SNR)2 71 dB min Total Harmonic Distortion (THD)2 –78 dB max Peak Harmonic or Spurious Noise (SFDR)2 –79 dB max Intermodulation Distortion (IMD)2 fa = 10.1 kHz, fb = 9.9 kHz fSCL from 1.7 MHz to 3.4 MHz fa = 1.1 kHz, fb = 0.9 kHz for fSCL up to 400 kHz Second-Order Terms –90 dB typ Third-Order Terms –90 dB typ Aperture Delay2 10 ns max Aperture Jitter2 50 ps typ Channel-to-Channel Isolation2 –90 dB typ FIN = 108 Hz, see the Terminology section Full-Power Bandwidth2 11 MHz typ @ 3 dB 2 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 Bits Integral Nonlinearity1,2 ±1 LSB max ±0.2 LSB typ Differential Nonlinearity1,2 +1/–0.9 LSB max Guaranteed no missed codes to 12 bits ±0.2 LSB typ Offset Error2 ±4 LSB max Mode 1 (CONVST Mode) ±6 LSB max Mode 2 (Command Mode) Offset Error Match2 ±1 LSB max Gain Error2 ±2 LSB max Gain Error Match2 ±1 LSB max ANALOG INPUT Input Voltage Range 0 to REFIN V DC Leakage Current ± 1 µA max Input Capacitance 30 pF typ REFERENCE INPUT REFIN Input Voltage Range 1.2 to VDD V min/V max DC Leakage Current ± 1 µA max Input Impedance 69 kΩ typ LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH 0.7 (VDD) V min Input Low Voltage, VINL 0.3 (VDD) V max Input Leakage Current, IIN ± 1 µA max VIN = 0 V or VDD Input Capacitance, CIN 3 10 pF max Input Hysteresis, VHYST 0.1 (VDD) V min

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AD7997/AD7998 Rev. 0 | Page 6 of 32 Parameter B Version Unit Test Conditions/Comments LOGIC INPUTS (CONVST) Input High Voltage, VINH 2.4 V min VDD = 5 V 2.0 V min VDD = 3 V Input Low Voltage, VINL 0.8 V max VDD = 5 V 0.4 V max VDD = 3 V Input Leakage Current, IIN ±1 µA max VIN = 0 V or VDD Input Capacitance, CIN3 10 pF max LOGIC OUTPUTS (OPEN-DRAIN) Output Low Voltage, VOL 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE See the Modes of Operation section Conversion Time 2 µs typ Throughput Rate Mode 1 (Reading after the Conversion) 5 kSPS typ fSCL = 100 kHz 21 kSPS typ fSCL = 400 kHz 121 kSPS typ fSCL = 3.4 MHz Mode 2 5.5 kSPS typ fSCL = 100 kHz 22 kSPS typ fSCL = 400 kHz 147 kSPS typ fSCL = 3.4 MHz , 188 kSPS typ @ 5 V POWER REQUIREMENTS VDD 2.7/5.5 V min/max IDD Digital inputs = 0 V or VDD Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 Mode 3 (I2C Inactive, TCONVERT x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V Power Dissipation Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz fSCL 1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 Power Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V 1 Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C Hs-Mode SCL frequencies. Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled. 2 See the section. Terminology 3 Guaranteed by initial characterization.

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AD7997/AD7998 Rev. 0 | Page 7 of 32 I2C TIMING SPECIFICATIONS Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line. tr and tf measured between 0.3 VDD and 0.7 VDD. High speed mode timing specifications apply to the AD7997-1/AD7998-1 only. Standard and fast mode timing specifications apply to both the AD7997-0/AD7998-0 and the AD7997-1/AD7998-1. See Figure 2. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; TA =TMIN to TMAX. Table 3. AD7997/AD7998 Limit at TMIN, TMAX Parameter Conditions Min Max Unit Description fSCL Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz High speed mode CB = 100 pF max 3.4 MHz CB = 400 pF max 1.7 MHz t1 Standard mode 4 µs tHIGH, SCL high time Fast mode 0.6 µs High speed mode CB = 100 pF max 60 ns CB = 400 pF max 120 ns t2 Standard mode 4.7 µs tLOW, SCL low time Fast mode 1.3 µs High speed mode CB = 100 pF max 160 ns CB = 400 pF max 320 ns t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns High speed mode 10 ns t41 Standard mode 0 3.45 µs tHD;DAT, data hold time Fast mode 0 0.9 µs High speed mode CB = 100 pF max 0 702 ns CB = 400 pF max 0 150 ns t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition Fast mode 0.6 µs High speed mode 160 ns t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition Fast mode 0.6 µs High speed mode 160 ns t7 Standard mode 4.7 µs tBUF, bus free time between a stop and a start condition Fast mode 1.3 µs t8 Standard mode 4 µs tSU;STO, setup time for stop condition Fast mode 0.6 µs High speed mode 160 ns t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 80 ns CB = 400 pF max 20 160 ns

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AD7997/AD7998 Rev. 0 | Page 8 of 32 AD7997/AD7998 Limit at TMIN, TMAX Parameter Conditions Min Max Unit Description t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 80 ns CB = 400 pF max 20 160 ns t11 Standard mode 1000 ns tRCL, rise time of SCL signal Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 40 ns CB = 400 pF max 20 80 ns t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an Acknowledge bit Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 80 ns CB = 400 pF max 20 160 ns t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 40 ns CB = 400 pF max 20 80 ns tSP Fast mode 0 50 ns Pulse width of suppressed spike High speed mode 0 10 ns tPOWER-UP 1 typ µs Power-up time 1 A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge. 2 For 3 V supplies, the maximum hold time with CB = 100 pF max is 100 ns max. P S S P t6 t4 t1 t3 t5 t8 t2 t11 t12 t6 SCL SDA t7 t9t10 S = START CONDITION P = STOP CONDITION 0 34 73 -0 -0 02 Figure 2. Timing Diagram for 2-Wire Serial Interface

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AD7997/AD7998 Rev. 0 | Page 9 of 32 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to GND −0.3 V to 7 V Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Reference Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150° Junction Temperature 150°C 20-Lead TSSOP θJA Thermal Impedance 143°C/W θJC Thermal Impedance 45°C/W Pb/SN Temperature, Soldering Reflow (10 s to 30 s) 240 (+0/-5)°C Pb-free Temperature, Soldering Reflow 260 (+0)°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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