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AD8251ARMZ-R7

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AD8251ARMZ-R7

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Part Number AD8251ARMZ-R7
Manufacturer Analog Devices Inc.
Description IC OPAMP INSTR 10MHZ 10MSOP
Datasheet AD8251ARMZ-R7 Datasheet
Package 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
In Stock 718 piece(s)
Unit Price $ 6.9027 *
Lead Time Can Ship Immediately
Estimated Delivery Time Oct 29 - Nov 3 (Choose Expedited Shipping)
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Part Number # AD8251ARMZ-R7 (Linear - Amplifiers - Instrumentation, OP Amps, Buffer Amps) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD8251ARMZ-R7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Linear - Amplifiers - Instrumentation, OP Amps, Buffer Amps
Datasheet AD8251ARMZ-R7Datasheet
Package10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
SeriesiCMOS?
Amplifier TypeInstrumentation
Number of Circuits1
Output Type-
Slew Rate30 V/µs
Gain Bandwidth Product-
-3db Bandwidth10MHz
Current - Input Bias5nA
Voltage - Input Offset70µV
Current - Supply4.1mA
Current - Output / Channel37mA
Voltage - Supply, Single/Dual (±)��5 V ~ 15 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
Supplier Device Package10-MSOP

AD8251ARMZ-R7 Datasheet

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10 MHz, 20 V/μs, G = 1, 2, 4, 8 iCMOS Programmable Gain Instrumentation Amplifier AD8251 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. FEATURES Small package: 10-lead MSOP Programmable gains: 1, 2, 4, 8 Digital or pin-programmable gain setting Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 98 dB (minimum), G = 8 Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.8 μV/°C (maximum), G = 8 Excellent ac performance Fast settling time: 785 ns to 0.001% (maximum) High slew rate: 20 V/μs (minimum) Low distortion: −110 dB THD at 1 kHz, 10 V swing High CMRR over frequency: 80 dB to 50 kHz (minimum) Low noise: 18 nV/√Hz, G = 8 (maximum) Low power: 4.1 mA APPLICATIONS Data acquisition Biomedical analysis Test and measurement GENERAL DESCRIPTION The AD8251 is an instrumentation amplifier with digitally programmable gains that has GΩ input impedance, low output noise, and low distortion, making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters (ADCs). It has a high bandwidth of 10 MHz, low THD of −110 dB, and fast settling time of 785 ns (maximum) to 0.001%. Offset drift and gain drift are guaranteed to 1.8 μV/°C and 10 ppm/°C, respectively, for G = 8. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 dB at G = 1 from dc to 50 kHz. The combination of precision dc performance coupled with high speed capabilities makes the AD8251 an excellent candidate for data acquisition. Furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers. The AD8251 user interface consists of a parallel port that allows users to set the gain in one of two ways (see Figure 1). A 2-bit word sent via a bus can be latched using the WR input. An alternative is to use the transparent gain mode where the state of the logic levels at the gain port determines the gain. FUNCTIONAL BLOCK DIAGRAM A1 A0DGND WR AD8251 +VS –VS REF OUT +IN LOGIC –IN 1 10 8 3 7 4562 9 06 28 7- 0 01 Figure 1. 25 –10 1k 100M 06 28 7- 0 02 FREQUENCY (Hz) G A IN ( d B ) 10k 100k 1M 10M 20 15 10 5 0 –5 G = 1 G = 2 G = 4 G = 8 Figure 2. Gain vs. Frequency Table 1. Instrumentation Amplifiers by Category General Purpose Zero Drift Mil Grade Low Power High Speed PGA AD82201 AD82311 AD620 AD6271 AD8250 AD8221 AD85531 AD621 AD6231 AD8251 AD8222 AD85551 AD524 AD82231 AD8253 AD82241 AD85561 AD526 AD8228 AD85571 AD624 1 Rail-to-rail output. The AD8251 is available in a 10-lead MSOP package and is specified over the −40°C to +85°C temperature range, making it an excellent solution for applications where size and packing density are important considerations.

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AD8251 Rev. B | Page 2 of 24 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 16 Gain Selection ............................................................................. 16 Power Supply Regulation and Bypassing ................................ 18 Input Bias Current Return Path ............................................... 18 Input Protection ......................................................................... 18 Reference Terminal .................................................................... 19 Common-Mode Input Voltage Range ..................................... 19 Layout .......................................................................................... 19 RF Interference ........................................................................... 20 Driving an ADC ......................................................................... 20 Applications..................................................................................... 21 Differential Output .................................................................... 21 Setting Gains with a Microcontroller ...................................... 21 Data Acquisition......................................................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 REVISION HISTORY 11/10—Rev. A to Rev. B Changes to Voltage Offset, Offset RTI VOS, Average TC Parameter in Table 2......................................................................... 3 Updated Outline Dimensions ....................................................... 23 5/08—Rev. 0 to Rev. A Changes to Table 1............................................................................ 1 Changes to Table 2.............................................................................3 Changes to Table 3.............................................................................6 Inserted Figure 17; Renumbered Sequentially ..............................9 Inserted Figure 29........................................................................... 11 Changes to Timing for Latched Gain Mode Section ................. 17 5/07—Revision 0: Initial Version

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AD8251 Rev. B | Page 3 of 24 SPECIFICATIONS +VS = 15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V G = 1 80 98 dB G = 2 86 104 dB G = 4 92 110 dB G = 8 98 110 dB CMRR to 50 kHz +IN = −IN = −10 V to +10 V G = 1 80 dB G = 2 84 dB G = 4 86 dB G = 8 86 dB NOISE Voltage Noise, 1 kHz, RTI G = 1 40 nV/√Hz G = 2 27 nV/√Hz G = 4 22 nV/√Hz G = 8 18 nV/√Hz 0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 2 2.5 μV p-p G = 4 1.8 μV p-p G = 8 1.2 μV p-p Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p VOLTAGE OFFSET Offset RTI VOS G = 1, 2, 4, 8 ±(70 + 200/G) ±(200 + 600/G) μV Over Temperature T = −40°C to +85°C ±(90 + 300/G) ±(260 + 900/G) μV Average TC T = −40°C to +85°C ±(0.6 + 1.5/G) ±(1.2 + 5/G) μV/°C Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±(2 + 7/G) ±(6 + 20/G) μV/V INPUT CURRENT Input Bias Current 5 30 nA Over Temperature T = −40°C to +85°C 40 nA Average TC T = −40°C to +85°C 400 pA/°C Input Offset Current 5 30 nA Over Temperature T = −40°C to +85°C 30 nA Average TC T = −40°C to +85°C 160 pA/°C DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 10 MHz G = 2 10 MHz G = 4 8 MHz G = 8 2.5 MHz Settling Time 0.01% ΔOUT = 10 V step G = 1 615 ns G = 2 460 ns G = 4 460 ns G = 8 625 ns

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AD8251 Rev. B | Page 4 of 24 Parameter Conditions Min Typ Max Unit Settling Time 0.001% ΔOUT = 10 V step G = 1 785 ns G = 2 700 ns G = 4 700 ns G = 8 770 ns Slew Rate G = 1 20 V/μs G = 2 30 V/μs G = 4 30 V/μs G = 8 30 V/μs Total Harmonic Distortion + Noise f = 1 kHz, RL = 10 kΩ, ±10 V, G = 1, 10 Hz to 22 kHz band- pass filter −110 dB GAIN Gain Range G = 1, 2, 4, 8 1 8 V/V Gain Error OUT = ±10 V G = 1 0.03 % G = 2, 4, 8 0.04 % Gain Nonlinearity OUT = −10 V to +10 V G = 1 RL = 10 kΩ, 2 kΩ, 600 Ω 9 ppm G = 2 RL = 10 kΩ, 2 kΩ, 600 Ω 12 ppm G = 4 RL = 10 kΩ, 2 kΩ, 600 Ω 12 ppm G = 8 RL = 10 kΩ, 2 kΩ, 600 Ω 15 ppm Gain vs. Temperature All gains 3 10 ppm/°C INPUT Input Impedance Differential 5.3||0.5 GΩ||pF Common Mode 1.25||2 GΩ||pF Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1.5 +VS − 1.5 V Over Temperature T = −40°C to +85°C −VS + 1.6 +VS − 1.7 V OUTPUT Output Swing −13.5 +13.5 V Over Temperature T = −40°C to +85°C −13.5 +13.5 V Short-Circuit Current 37 mA REFERENCE INPUT RIN 20 kΩ IIN +IN, −IN, REF = 0 1 μA Voltage Range −VS +VS V Gain to Output 1 ± 0.0001 V/V DIGITAL LOGIC Digital Ground Voltage, DGND Referred to GND −VS + 4.25 0 +VS − 2.7 V Digital Input Voltage Low Referred to GND DGND 2.1 V Digital Input Voltage High Referred to GND 2.8 +VS V Digital Input Current 1 μA Gain Switching Time1 325 ns tSU See Figure 3 timing diagram 20 ns tHD See Figure 3 timing diagram 10 ns t WR -LOW See Figure 3 timing diagram 20 ns t WR -HIGH See Figure 3 timing diagram 40 ns

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AD8251 Rev. B | Page 5 of 24 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range ±5 ±15 V Quiescent Current, +IS 4.1 4.5 mA Quiescent Current, −IS 3.7 4.5 mA Over Temperature T = −40°C to +85°C 4.5 mA TEMPERATURE RANGE Specified Performance −40 +85 °C 1 Add time for the output to slew and settle to calculate the total time for a gain change. TIMING DIAGRAM A0, A1 WR tSU tHD tWR-HIGH tWR-LOW 0 62 87 -0 03 Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)

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AD8251 Rev. B | Page 6 of 24 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage ±17 V Power Dissipation See Figure 4 Output Short-Circuit Current Indefinite1 Common-Mode Input Voltage +VS + 13 V to −VS − 13 V Differential Input Voltage +VS + 13 V, −VS − 13 V2 Digital Logic Inputs ±VS Storage Temperature Range −65°C to +125°C Operating Temperature Range3 −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 140°C θJA (Four-Layer JEDEC Standard Board) 112°C/W Package Glass Transition Temperature 140°C 1 Assumes the load is referenced to midsupply. 2 Current must be kept to less than 6 mA. 3 Temperature for specified performance is −40°C to +85°C. For performance to +125°C, see the Typical Performance Characteristics section. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8251 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8251. Exceeding a junction temperature of 140°C for an extended period can result in changes in silicon devices, potentially causing failure. The still air thermal properties of the package and PCB (θJA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as ( )JADAJ θPTT ×+= The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power − Load Power) ( ) L OUT L OUTS SSD R V R VV IVP 2 – 2 ⎟ ⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ ×+×= In single-supply operation with RL referenced to −VS, the worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a four-layer JEDEC standard board. 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 –40 –20 120100806040200 M A X IM U M P O W E R D IS S IP A T IO N ( W ) AMBIENT TEMPERATURE (°C) 0 62 87 -0 0 4 Figure 4. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION

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AD8251 Rev. B | Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN DGND –VS A0 A1 +IN REF +VS OUT WR AD8251 TOP VIEW (Not to Scale) 1 2 3 4 5 10 9 8 7 6 06 28 7 -0 0 5 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Inverting Input Terminal. True differential input. 2 DGND Digital Ground. 3 −VS Negative Supply Terminal. 4 A0 Gain Setting Pin (LSB). 5 A1 Gain Setting Pin (MSB). 6 WR Write Enable. 7 OUT Output Terminal. 8 +VS Positive Supply Terminal. 9 REF Reference Voltage Terminal. 10 +IN Noninverting Input Terminal. True differential input.

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AD8251 Rev. B | Page 8 of 24 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted. INPUT OFFSET CURRENT (nA) 800 400 600 200 0 500 700 300 100 3020100 0 62 87 -0 09 N U M B E R O F U N IT S –30 –10–20 CMRR (µV/V) 2700 0 120 0 62 87 -0 06 N U M B E R O F U N IT S 2400 2100 1800 1500 1200 900 600 300 –120 –90 –60 –30 0 30 60 90 Figure 9. Typical Distribution of Input Offset Current Figure 6. Typical Distribution of CMRR, G = 1 0 62 87 -0 1 0 90 0 1 100k FREQUENCY (Hz) N O IS E ( n V /√ H z) 10 100 1k 10k 80 70 60 50 40 30 20 10 G = 1 G = 2 G = 4 G = 8 INPUT OFFSET VOLTAGE, VOSI , RTI (µV) 500 300 100 400 200 0 2001000 0 62 87 -0 0 7 N U M B E R O F U N IT S –200 –100 Figure 10. Voltage Spectral Density Noise vs. Frequency Figure 7. Typical Distribution of Offset Voltage, VOSI 0 62 87 -0 1 11s/DIV2µV/DIV INPUT BIAS CURRENT (nA) 800 400 600 200 0 3020100 0 62 87 -0 08 N U M B E R O F U N IT S –30 –10–20 Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Figure 8. Typical Distribution of Input Bias Current

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AD8251 Rev. B | Page 9 of 24 0 62 87 -0 1 21s/DIV1.25µV/DIV Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 8 0 62 87 -0 1 3 18 0 1 100k FREQUENCY (Hz) N O IS E ( p A /√ H z) 10 100 1k 10k 16 14 12 10 8 6 4 2 Figure 13. Current Noise Spectral Density vs. Frequency 0 62 87 -0 1 41s/DIV140pA/DIV Figure 14. 0.1 Hz to 10 Hz Current Noise 150 130 110 90 50 70 10 10 1M 0 62 8 7- 0 16 FREQUENCY (Hz) P S R R ( d B ) 100 1k 10k 100k 30 G = 1 G = 8 G = 2 G = 4 Figure 15. Positive PSRR vs. Frequency, RTI 150 110 130 90 70 30 10 50 10 1M 0 62 8 7- 0 17 FREQUENCY (Hz) P S R R ( d B ) 100 1k 10k 100k G = 1 G = 2 G = 4 G = 8 Figure 16. Negative PSRR vs. Frequency, RTI 10 9 8 7 6 5 4 3 2 1 0 0.01 10.1 C H A N G E I N O F F S E T V O LT A G E , R T I (µ V ) 10 WARM-UP TIME (minutes) 0 62 87 -1 17 Figure 17. Change in Offset Voltage, RTI vs. Warmup Time

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