AD8642ARZ-REEL7

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Low Power, Rail-to-Rail Output, Precision JFET Amplifiers Data Sheet AD8641/AD8642/AD8643 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Low supply current: 250 μA max Very low input bias current: 1 pA max Low offset voltage: 750 μV max Single-supply operation: 5 V to 26 V Dual-supply operation: ±2.5 V to ±13 V Rail-to-rail output Unity-gain stable No phase reversal SC70 package APPLICATIONS Line-/battery-powered instruments Photodiode amplifiers Precision current sensing Medical instrumentation Industrial controls Precision filters Portable audio ATE GENERAL DESCRIPTION The AD8641/AD8642/AD8643 are low power, precision JFET input amplifiers featuring extremely low input bias current and rail-to-rail output. The ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables designers to buffer complementary metal-oxide semiconductor digital-to-analog converters (CMOS DACs), ASICs, and other wide output swing devices in single-supply systems. The outputs remain stable with capacitive loads of more than 500 pF. The AD8641/AD8642/AD8643 are suitable for applications utilizing multichannel boards that require low power to manage heat. Other applications include photodiodes, ATE reference level drivers, battery management, and industrial controls. The AD8641/AD8642/AD8643 are fully specified over the extended industrial temperature range of −40°C to +125°C. The AD8641 is available in 5-lead SC70 and 8-lead SOIC lead-free packages. The AD8642 is available in 8-lead MSOP and 8-lead SOIC lead-free packages. The AD8643 is available in 14-lead SOIC and 16-lead, 3 mm × 3 mm, LFCSP lead-free packages. PIN CONFIGURATIONS OUT 1 +IN 3 VEE 2 VCC5 –IN4 AD8641 TOP VIEW (Not to Scale) 05 07 2- 10 1 Figure 1. 5-Lead SC70 (KS-5) NIC –IN +IN VEE NIC VCC OUT NIC 05 07 2- 10 2 NIC = NO INTERNAL CONNECTION. 1 2 3 4 8 7 6 5 AD8641 TOP VIEW (Not to Scale) Figure 2. 8-Lead SOIC (R-8) OUT A 1 –IN A 2 +IN A 3 V– 4 V+8 OUT B7 –IN B6 +IN B5 AD8642 TOP VIEW (Not to Scale) 05 07 2- 10 5 Figure 3. 8-Lead SOIC (R-8) OUT A 1 –IN A 2 +IN A 3 V– 4 V+8 OUT B7 –IN B6 +IN B5 AD8642 TOP VIEW (Not to Scale) 05 07 2- 06 4 Figure 4. 8-Lead MSOP (RM-8) 05 07 2- 10 3 OUT A 1 OUT D14 –IN A 2 –IN D13 +IN A 3 +IN D12 V+ 4 V–11 +IN B 5 +IN C10 –IN B 6 –IN C9 OUT B 7 OUT C8 TOP VIEW (Not to Scale) AD8643 Figure 5. 14-Lead SOIC (R-14) 05 07 2- 10 4 +IN C V– +IN D –IN D –I N B O U T B O U T C –I N C –IN A +IN B V+ +IN A PIN 1 INDICATOR N IC O U T A O U T D N IC NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD SHOULD BE CONNECTED TO V+. 12 11 10 1 3 4 9 2 65 7 8 16 15 14 13 AD8643 TOP VIEW Figure 6. 16-Lead LFCSP (CP-16-27) (Not Drawn to Scale)

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AD8641/AD8642/AD8643 Data Sheet Rev. F | Page 2 of 15 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Pin Configurations ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Characteristics ............................................................. 3 Absolute Maximum Ratings ............................................................5 Thermal Resistance .......................................................................5 ESD Caution...................................................................................5 Typical Performance Characteristics ..............................................6 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 14 REVISION HISTORY 4/16—Rev. E to Rev. F Changed CP-16-3 to CP-16-27 .................................... Throughout Changes to Figure 2 and Figure 6 ................................................... 1 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 9/11—Rev. D to Rev. E Changes to Thermal Resistance Section ........................................ 5 7/11—Rev. C to Rev. D Changes to Figure 6 .......................................................................... 1 11/10—Rev. B to Rev. C Changes to Figure 6 .......................................................................... 1 Added Thermal Resistance Section and Table 4 .......................... 5 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 15 4/05—Rev. A to Rev. B Added AD8643 ................................................................... Universal Added 14-Lead SOIC ......................................................... Universal Added 16-Lead LFCSP ....................................................... Universal Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 3/05—Rev. 0 to Rev. A Added AD8642 ................................................................... Universal Changes to General Description ..................................................... 1 Added Figure 3 and Figure 4 ............................................................ 1 Changes to Specifications ................................................................. 3 Changes to Absolute Maximum Ratings ........................................ 5 Changes to Figure 22 ......................................................................... 8 Changes to Figure 23 ......................................................................... 9 Changes to Figure 41 ...................................................................... 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 10/04—Initial Version: Revision 0

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Data Sheet AD8641/AD8642/AD8643 Rev. F | Page 3 of 15 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 50 750 µV AD8643 LFCSP only 1 mV −40°C < TA < +85°C 1.5 mV +85°C < TA < +125°C, VCM = 1.5 V 1.6 mV Input Bias Current IB 0.25 1 pA −40°C < TA < +125°C 180 pA Input Offset Current IOS 0.5 pA −40°C < TA < +125°C 60 pA Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.5 V 74 93 dB Large Signal Voltage Gain AVO RL = 10 kΩ, VO = 0.5 to 4.5 V 80 140 V/mV Offset Voltage Drift ∆VOS/∆T −40°C < TA < +125°C 2.5 µV/°C OUTPUT CHARACTERISTICS Output Voltage High VOH 4.95 V IL = 1 mA, −40°C to +125°C 4.94 V Output Voltage Low VOL 0.05 V IL = 1 mA, −40°C to +125°C 0.01 0.05 V Output Current IOUT ±6 mA POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 5 V to 26 V 90 107 dB Supply Current/Amplifier ISY 195 250 µA −40°C < TA < +125°C 270 µA DYNAMIC PERFORMANCE Slew Rate SR 2 V/µs Gain Bandwidth Product GBP AD8641, AD8642 3 MHz AD8643 2.5 MHz Phase Margin Øm 50 Degrees NOISE PERFORMANCE Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4.0 µV p-p Voltage Noise Density eN f = 1 kHz 28.5 nV/√Hz Current Noise Density iN f = 1 kHz 0.5 fA/√Hz

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AD8641/AD8642/AD8643 Data Sheet Rev. F | Page 4 of 15 VS = ±13 V, VCM = 0 V, TA =25°C, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 70 750 µV AD8643 LFCSP only 1 mV −40°C < TA < +125°C 1.5 mV Input Bias Current IB 0.25 1 pA −40°C < TA < +125°C 260 pA Input Offset Current IOS 0.5 pA −40°C < TA < +125°C 65 pA Input Voltage Range −13 +10 V Common-Mode Rejection Ratio CMRR VCM = −13 V to +10 V 90 107 dB Large Signal Voltage Gain AVO RL = 10 kΩ, VO = −11 V to +11 V 215 290 V/mV Offset Voltage Drift ∆VOS/∆T −40°C < TA < +125°C 2.5 µV/°C OUTPUT CHARACTERISTICS Output Voltage High VOH +12.95 V IL = 1 mA, −40°C to +125°C +12.94 V Output Voltage Low VOL −12.95 V IL = 1 mA, −40°C to +125°C −12.94 V Output Current IOUT ±12 mA POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±13 V 90 107 dB Supply Current/Amplifier ISY 200 290 µA −40°C < TA < +125°C 330 µA DYNAMIC PERFORMANCE Slew Rate SR 3 V/µs Gain Bandwidth Product GBP 3.5 MHz Phase Margin Øm 60 Degrees NOISE PERFORMANCE Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4.2 µV p-p Voltage Noise Density eN f = 1 kHz 27.5 nV/√Hz Current Noise Density iN f = 1 kHz 0.5 fA/√Hz

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Data Sheet AD8641/AD8642/AD8643 Rev. F | Page 5 of 15 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 3. Parameter Rating Supply Voltage 27.3 V Input Voltage VS− to VS+ Differential Input Voltage ±Supply Voltage Output Short-Circuit Duration Indefinite Storage Temperature Range KS-5, R-8, RM-8, R-14, CP-16 Packages −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range KS-5, R-8, RM-8, R-14, CP-16 Packages −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This was measured using a standard 4-layer board. For the LFCSP, solder the exposed pad to a copper plane, which should be connected to V+. Table 4. Package Type θJA θJC Unit 5-Lead SC70 (KS) 430 149 °C/W 8-Lead SOIC (R) 121 43 °C/W 8-Lead MSOP (RM) 142 45 °C/W 14-Lead SOIC (R) 110 36 °C/W 16-Lead LFCSP (CP) 81 16 °C/W ESD CAUTION

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AD8641/AD8642/AD8643 Data Sheet Rev. F | Page 6 of 15 TYPICAL PERFORMANCE CHARACTERISTICS 0 10 20 30 40 50 60 70 FR EQ U EN C Y –0 .6 0 –0 .5 5 –0 .5 0 –0 .4 5 –0 .4 0 –0 .3 5 –0 .3 0 –0 .2 5 –0 .2 0 –0 .1 5 –0 .1 0 –0 .0 5 0 0. 05 0. 10 0. 15 0. 20 0. 25 0. 30 0. 35 0. 40 0. 45 0. 50 0. 55 0. 60 VOS (mV) 05 07 2- 00 2 80 VSY = ±13V Figure 7. Input Offset Voltage N U M B ER O F A M PL IF IE R S OFFSET VOLTAGE (µV/°C) 05 07 2- 00 30 0. 5 1. 0 1. 5 2. 0 2. 5 3. 0 3. 5 4. 0 4. 5 5. 0 5. 5 6. 0 6. 5 7. 0 7. 5 8. 0 8. 5 9. 0 9. 5 10 .0 16 14 12 10 8 6 4 2 0 VSY = ±13V Figure 8. Offset Voltage Drift 0 10 20 30 40 50 60 70 FR EQ U EN C Y –0 .6 0 –0 .5 5 –0 .5 0 –0 .4 5 – 0 .4 0 –0 .3 5 –0 .3 0 –0 .2 5 –0 .2 0 –0 .1 5 –0 .1 0 –0 .0 5 0 0. 05 0. 10 0. 15 0. 20 0. 25 0. 30 0. 35 0. 40 0. 45 0. 50 0. 55 0. 60 VOS (mV) 05 07 2- 00 4 VSY = ±2.5V Figure 9. Input Offset Voltage N U M B ER O F A M PL IF IE R S TCVOS (µV/°C) 05 07 2- 00 50 0. 5 1. 0 1. 5 2. 0 2. 5 3. 0 3. 5 4. 0 4. 5 5. 0 5. 5 6. 0 6. 5 7. 0 7. 5 8. 0 8. 5 9. 0 9. 5 10 .0 0 2 4 6 8 10 12 14 16 18 20 VSY = 5V VCM = 1.5V Figure 10. Offset Voltage Drift –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 IN PU T B IA S (p A ) –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 VCM (V) 05 07 2- 00 6 VSY = ±13V TA = 25°C Figure 11. Input Bias Current vs. VCM –0.4 –0.3 –0.2 –0.1 0 0.1 IN PU T B IA S (p A ) 0.2 0.3 0.4 –15.0 –12.5 –10.0 –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0 12.5 15.0 VCM (V) 05 07 2- 00 7 VSY = ±13V TA = 25°C 0.5 –0.5 Figure 12. Input Bias Current vs. VCM

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Data Sheet AD8641/AD8642/AD8643 Rev. F | Page 7 of 15 IN PU T B IA S C U R R EN T (p A ) 0.1 1 10 100 1000 50 750 25 100 125 150 TEMPERATURE (°C) 05 07 2- 00 8 VSY = ±13V Figure 13. Input Bias Current vs. Temperature –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 IN PU T B IA S (p A ) –5 –4 –3 –2 –1 0 1 2 3 4 5 VCM (V) 05 07 2- 00 9 VSY = +5V OR ±5V Figure 14. Input Bias Current vs. VCM V O S (µ V) –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 VCM (V) 05 07 2- 01 00 –100 0 200 600 800 1000 400 100 500 700 900 300 VSY = ±13V Figure 15. Input Offset Voltage vs. VCM –500 –400 –300 –200 –100 0 100 200 300 400 500 V O S (µ V) 1.0 1.50 0.5 2.0 2.5 VCM (V) 05 07 2- 01 1 VSY = 5V Figure 16. Input Offset Voltage vs. VCM O PE N -L O O P G A IN (V /V ) 10k 1M 100k 10M LOAD RESISTANCE (kΩ) 0.1 101 100 05 07 2- 01 2 VSY = ±13V VSY = ±2.5V Figure 17. Open-Loop Gain vs. Load Resistance A VO (V /m V) 1 100 10 1000 –50 –30 –10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) 05 07 2- 01 3 A. VSY = ±13V, VO = ±11V, RL = 10kΩ B. VSY = ±13V, VO = ±11V, RL = 2kΩ C. VSY = +5V, VO = +0.5V/+4.5V, RL = 10kΩ D. VSY = +5V, VO = +0.5V/+4.5V, RL = 2kΩ E. VSY = +5V, VO = +0.5V/+4.5V, RL = 600Ω A B C D E Figure 18. Open-Loop Gain vs. Temperature

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AD8641/AD8642/AD8643 Data Sheet Rev. F | Page 8 of 15 –600 –400 –200 –300 –500 0 –100 O FF SE T VO LT A G E (µ V) 200 100 400 300 600 500 –5 0–15 –10 5 10 15 OUTPUT VOLTAGE (V) 05 07 2- 01 4 10kΩ 1kΩ 100kΩ VSY = ±13V Figure 19. Input Error Voltage vs. Output Voltage for Resistive Loads –350 –250 –150 –200 –300 –50 –100 IN PU T VO LT A G E (µ V) 50 0 150 100 250 200 0 50 100 150 200 250 300 350 OUTPUT VOLTAGE FROM SUPPLY RAIL (mV) 05 07 2- 01 5 RL = 1kΩ POS RAIL NEG RAIL RL = 10kΩ RL = 2kΩ RL = 100kΩ RL = 100kΩ RL = 10kΩ RL = 1kΩ RL = 2kΩ VSY = ±5V Figure 20. Input Error Voltage vs. Output Voltage Within 300 mV of Supply Rails 0 100 200 300 400 500 I S Y (µ A ) 600 700 800 4 8 12 16 20 24 28 VSY (V) 0 50 72 -0 16 +25°C –55°C +125°C Figure 21. Quiescent Current vs. Supply Voltage at Different Temperatures SA TU R A TI O N V O LT A G E (m V) 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) 05 07 2- 01 7 –VSY – VOL VSY – VOH VSY = ±13V Figure 22. Output Saturation Voltage vs. Load Current SA TU R A TI O N V O LT A G E (m V) 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) 05 07 2- 01 8 VOL VSY – VOH VSY = 5V Figure 23. Output Saturation Voltage vs. Load Current –30 –135 –90 –45 0 45 90 135 180 225 270 315 –20 –10 0 10 20 30 40 50 60 70 10k 100k 1M 10M PH A SE (D eg re es ) GAIN PHASE VSY = ±13V RL = 2kΩ CL = 40pF G A IN (d B ) FREQUENCY (Hz) 05 07 2- 01 9 Figure 24. Open-Loop Gain and Phase Margin vs. Frequency

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Data Sheet AD8641/AD8642/AD8643 Rev. F | Page 9 of 15 –30 –135 –90 –45 0 45 90 135 180 225 270 315 –20 –10 0 10 20 30 40 50 60 70 10k 100k 1M 10M PH A SE (D eg re es ) GAIN PHASE G A IN (d B ) FREQUENCY (Hz) 05 07 2- 02 0 VSY = 5V RL = 2kΩ CL = 40pF Figure 25. Open-Loop Gain and Phase Margin vs. Frequency FREQUENCY (Hz) –30 –20 –10 0 10 20 30 40 50 60 70 1k 10k 100k 1M 10M G A IN (d B ) VSY = ±13V RL = 2kΩ CL = 40pF G = +100 G = +1 G = +10 05 07 2- 02 1 Figure 26. Closed-Loop Gain vs. Frequency FREQUENCY (Hz) –30 –20 –10 0 10 20 30 40 50 60 70 1k 10k 100k 1M 10M G A IN (d B ) G = +100 G = +1 G = +10 05 07 2- 02 2 VSY = 5V RL = 2kΩ CL = 40pF Figure 27. Closed-Loop Gain vs. Frequency –60 –40 –20 0 20 40 60 80 100 120 140 1k 10k 100k 1M 10M FREQUENCY (Hz) C M R R (d B ) 05 07 2- 02 3 VSY = ±13V Figure 28. CMRR vs. Frequency –60 –40 –20 0 20 40 60 80 100 120 140 1k 10k 100k 1M 10M FREQUENCY (Hz) C M R R (d B ) 05 07 2- 02 4 VSY = 5V Figure 29. CMRR vs. Frequency –60 –40 –20 0 20 40 60 80 100 120 140 1k 10k 100k 1M 10M FREQUENCY (Hz) PS R R (d B ) 05 07 2- 02 5 +PSRR –PSRR VSY = ±13V Figure 30. PSRR vs. Frequency