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AD8802ARUZ-REEL

hot AD8802ARUZ-REEL

AD8802ARUZ-REEL

For Reference Only

Part Number AD8802ARUZ-REEL
Manufacturer Analog Devices Inc.
Description IC DAC 8BIT 12CH W/SD 20TSSOP
Datasheet AD8802ARUZ-REEL Datasheet
Package 20-TSSOP (0.173", 4.40mm Width)
In Stock 8616 piece(s)
Unit Price $ 5.746 *
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AD8802ARUZ-REEL Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet AD8802ARUZ-REEL Datasheet
Package20-TSSOP (0.173", 4.40mm Width)
SeriesTrimDAC?
Number of Bits8
Number of D/A Converters12
Settling Time600ns (Typ)
Output TypeVoltage - Unbuffered
Differential OutputNo
Data InterfaceSPI
Reference TypeExternal
Voltage - Supply, Analog2.7 V ~ 5.5 V
Voltage - Supply, Digital2.7 V ~ 5.5 V
INL/DNL (LSB)±0.5, ±0.25
ArchitectureR-2R
Operating Temperature-40°C ~ 85°C
Package / Case20-TSSOP (0.173", 4.40mm Width)
Supplier Device Package20-TSSOP

AD8802ARUZ-REEL Datasheet

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FUNCTIONAL BLOCK DIAGRAM CS CLK SDI SHDN AD8802/AD8804 D7 D0 ADDR DEC EN D11 D10 D9 D8 D7 SER REG D D0 DAC REG #1 R VDD D7 D0 DAC 12 DAC REG #12 R DAC 1 8 O1 O2 O4 O5 O6 O7 O8 O9 O10 O11 O12 VREFH GND RS (AD8802 ONLY) VREFL (AD8804 ONLY) O3 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 12 Channel, 8-Bit TrimDACswith Power Shutdown AD8802/AD8804 © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 GENERAL DESCRIPTION The 12-channel AD8802/AD8804 provides independent digitally- controllable voltage outputs in a compact 20-lead package. This potentiometer divider TrimDAC® allows replacement of the mechanical trimmer function in new designs. The AD8802/ AD8804 is ideal for dc voltage adjustment applications. Easily programmed by serial interfaced microcontroller ports, the AD8802 with its midscale preset is ideal for potentiometer replacement where adjustments start at a nominal value. Appli- cations such as gain control of video amplifiers, voltage con- trolled frequencies and bandwidths in video equipment, geometric correction and automatic adjustment in CRT com- puter graphic displays are a few of the many applications ideally suited for these parts. The AD8804 provides independent con- trol of both the top and bottom end of the potentiometer divider allowing a separate zero-scale voltage setting determined by the VREFL pin. This is helpful for maximizing the resolution of devices with a limited allowable voltage control range. Internally the AD8802/AD8804 contains 12 voltage-output digital-to-analog converters, sharing a common reference- voltage input. TrimDAC is a registered trademark of Analog Devices, Inc. FEATURES Low Cost Replaces 12 Potentiometers Individually Programmable Outputs 3-Wire SPI Compatible Serial Input Power Shutdown <55 mWatts Including IDD & IREF Midscale Preset, AD8802 Separate VREFL Range Setting, AD8804 +3 V to +5 V Single Supply Operation APPLICATIONS Automatic Adjustment Trimmer Replacement Video and Audio Equipment Gain and Offset Adjustment Portable and Battery Operated Equipment Each DAC has its own DAC latch that holds its output state. These DAC latches are updated from an internal serial-to- parallel shift register that is loaded from a standard 3-wire serial input digital interface. The serial-data-input word is decoded where the first 4 bits determine the address of the DAC latches to be loaded with the last 8 bits of data. The AD8802/ AD8804 consumes only 10 µA from 5 V power supplies. In ad- dition, in shutdown mode reference input current consumption is also reduced to 10 µA while saving the DAC latch settings for use after return to normal operation. The AD8802/AD8804 is available in the 20-pin plastic DIP, the SOIC-20 surface mount package, and the 1 mm thin TSSOP-20 package.

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Parameter Symbol Conditions Min Typ1 Max Units STATIC ACCURACY Specifications apply to all DACs Resolution N 8 Bits Differential Nonlinearity Error DNL Guaranteed Monotonic –1 ±1/4 +1 LSB Integral Nonlinearity Error INL –1.5 ±1/2 +1.5 LSB Full-Scale Error GFSE –1 1/2 +1 LSB Zero Code Error VZSE –1 1/4 +1 LSB DAC Output Resistance ROUT 3 5 8 kΩ Output Resistance Match ∆R/RO 1.5 % REFERENCE INPUT Voltage Range2 VREFH 0 VDD V VREFL Pin Available on AD8804 Only 0 VDD V REFH Input Resistance RREFH Digital Inputs = 55H, VREFH = VDD 1.2 kΩ REFL Input Resistance3 RREFL Digital Inputs = 55H, VREFL = VDD 1.2 kΩ Reference Input Capacitance3 CREF0 Digital Inputs all Zeros 32 pF CREF1 Digital Inputs all Ones 32 pF DIGITAL INPUTS Logic High VIH VDD = +5 V 2.4 V Logic Low VIL VDD = +5 V 0.8 V Logic High VIH VDD = +3 V 2.1 V Logic Low VIL VDD = +3 V 0.6 V Input Current IIL VIN = 0 V or + 5 V ±1 µA Input Capacitance3 CIL 5 pF POWER SUPPLIES4 Power Supply Range VDD Range 2.7 5.5 V Supply Current (CMOS) IDD VIH = VDD or VIL = 0 V 0.01 10 µA Supply Current (TTL) IDD VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V 1 4 mA Shutdown Current IREFH SHDN = 0 0.2 10 µA Power Dissipation PDISS VIH = VDD or VIL = 0 V, VDD = +5.5 V 55 µW Power Supply Sensitivity PSRR VDD = +5 V ± 10% 0.001 0.002 %/% DYNAMIC PERFORMANCE3 VOUT Settling Time tS ±1/2 LSB Error Band 0.6 µs Crosstalk CT Between Adjacent Outputs5 50 dB SWITCHING CHARACTERISTICS3, 6 Input Clock Pulse Width tCH, tCL Clock Level High or Low 15 ns Data Setup Time tDS 5 ns Data Hold Time tDH 5 ns CS Setup Time tCSS 10 ns CS High Pulse Width tCSW 10 ns Reset Pulse Width tRS 90 ns CLK Rise to CS Rise Hold Time tCSH 20 ns CS Rise to Clock Rise Setup tCS1 10 ns NOTES 1Typicals represent average readings at +25°C. 2VREFH can be any value between GND and VDD, for the AD8804 VREFL can be any value between GND and VDD. 3Guaranteed by design and not subject to production test. 4Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD). 5Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change (f = 100 kHz). 6See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. AD8802/AD8804–SPECIFICATIONS REV. 0–2– (VDD = +3 V 6 10% or +5 V 6 10%, VREFH = +VDD, VREFL = 0 V, –408C ≤TA ≤ +858C unless otherwise noted)

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AD8802/AD8804 REV. 0 –3– ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA Thermal Resistance θJA, SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W AD8802 PIN DESCRIPTIONS Pin Name Description 1 VREF Common DAC Reference Input 2 O1 DAC Output #1, addr = 00002 3 O2 DAC Output #2, addr = 00012 4 O3 DAC Output #3, addr = 00102 5 O4 DAC Output #4, addr = 00112 6 O5 DAC Output #5, addr = 01002 7 O6 DAC Output #6, addr = 01012 8 SHDN Reference input current goes to zero. DAC latch settings maintained 9 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded into the target DAC register 10 GND Ground 11 CLK Serial Clock Input, Positive Edge Triggered 12 SDI Serial Data Input 13 O7 DAC Output #7, addr = 01102 14 O8 DAC Output #8, addr = 01112 15 O9 DAC Output #9, addr = 10002 16 O10 DAC Output #10, addr = 10012 17 O11 DAC Output #11, addr = 10102 18 O12 DAC Output #12, addr = 10112 19 RS Asynchronous Preset to Midscale Output Setting. Loads all DAC Registers with 80H 20 VDD Positive Power Supply, Specified for Operation at Both +3 V and +5 V PIN CONFIGURATIONS 14 13 12 11 17 16 15 20 19 18 9 8 1 2 3 4 7 6 5 10 O10 O11 O12 VDD O7 O8 O9 VREFL CLK SDI VREFH O1 O2 O3 O4 O5 O6 SHDN CS GND TOP VIEW (Not to Scale) AD8804 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) VREFH O11 O12 RS VDD O1 O2 O3 AD8802 O8 O9 O10O4 O5 O6 SHDN CS GND CLK SDI O7 AD8804 PIN DESCRIPTIONS Pin Name Description 1 VREFH Common High-Side DAC Reference Input 2 O1 DAC Output #1, addr = 00002 3 O2 DAC Output #2, addr = 00012 4 O3 DAC Output #3, addr = 00102 5 O4 DAC Output #4, addr = 00112 6 O5 DAC Output #5, addr = 01002 7 O6 DAC Output #6, addr = 01012 8 SHDN Reference input current goes to zero DAC latch settings maintained 9 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded input the target DAC register 10 GND Ground 11 VREFL Common Low-Side DAC Reference Input 12 CLK Serial Clock Input, Positive Edge Triggered 13 SDI Serial Data Input 14 O7 DAC Output #7, addr = 01102 15 O8 DAC Output #8, addr = 01112 16 O9 DAC Output #9, addr = 10002 17 O10 DAC Output #10, addr = 10012 18 O11 DAC Output #11, addr = 10102 19 O12 DAC Output #12, addr = 10112 20 VDD Positive power supply, specified for operation at both +3 V and +5 V ORDERING GUIDE Temperature Package Package Model FTN Range Description Option AD8802AN RS –40°C/+85°C PDIP-20 N-20 AD8802AR RS –40°C/+85°C SOL-20 R-20 AD8802ARU RS –40°C/+85°C TSSOP-20 RU-20 AD8804AN REFL –40°C/+85°C PDIP-20 N-20 AD8804AR REFL –40°C/+85°C SOL-20 R-20 AD8804ARU REFL –40°C/+85°C TSSOP-20 RU-20 WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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AD8802/AD8804–Typical Performance Characteristics REV. 0–4– CODE – Decimal IN L – L S B 1 –1 0.75 0 –0.25 –0.5 –0.75 0.5 0.25 0 25632 64 96 128 160 192 224 VDD = +5V VREFH = +5V VREFL = 0V TA = +85°C TA = +25°C TA = –40°C Figure 1. INL vs. Code CODE – Decimal IN L – L S B 1 –1 0.75 0 –0.25 –0.5 –0.75 0.5 0.25 0 25632 64 96 128 160 192 224 TA = +85°C TA = +25°C TA = –40°C VDD = +5V VREFH = +5V VREFL = 0V Figure 2. Differential Nonlinearity Error vs. Code F R E Q U E N C Y ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB 1600 320 960 640 1280 0 0 0.2 0.4 0.6 0.8 1.0 VDD = +4.5V VREF = +4.5V VREFL = 0V TA = +25°C SS = 3600 PCS Figure 3. Total Unadjusted Error Histogram CODE – Decimal 160 0 80 40 120 140 100 60 20 0 25632 64 96 128 160 192 224 I R E F C U R R E N T – µ A VDD = +5V VREFH = +2V VREFL = 0V ONE DAC CHANGING WITH CODE, OTHER DACs SET TO 00H TA = +25°C Figure 4. Input Reference Current vs. Code 10k 1k 0 100 10 –35 255–15–55 65 1251058545 TEMPERATURE – °C S H U T D O W N C U R R E N T – n A VDD = +5.5V VREF = +5.5V VDD = +2.7V VREF = +2.7V Figure 5. Shutdown Current vs. Temperature TEMPERATURE – °C S U P P L Y C U R R E N T – µ A 100k 0.001 10k 10 1 0.1 0.01 1k 100 –55 125–35 –15 5 25 45 65 85 105 VDD = +5.5V VIN = +5.5V VDD = +5.5V VIN = +2.4V Figure 6. Supply Current vs. Temperature

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AD8802/AD8804 REV. 0 –5– 100 0.0001 2.5 0.01 0.001 0.50 0.1 1.0 10 21.51 INPUT VOLTAGE – Volts 53 4.543.5 TA = +25°C ALL DIGITAL INPUTS TIED TOGETHER S U P P L Y C U R R E N T – m A VDD = +5V VDD = +3V Figure 7. Supply Current vs. Logic Input Voltage 80 60 40 20 0 100 100k10k1k10 FREQUENCY – Hz P S R R – d B VDD = +5V ALL OUTPUTS SET TO MIDSCALE (80H) Figure 8. Power Supply Rejection vs. Frequency 10 0% 100 90 0% VDD = +5V VREF = +5V TIME – 5µs/DIV 4V 0V 5V 0V OUT CS 2V 5µs 6V 2V 5V Figure 9. Large-Signal Settling Time 10 0% 100 90 OUTPUT1: OOH → FFH TIME – 0.2µs/DIV O U T P U T 2 – 1 0 m V /D IV 10mV 200ns VDD = +5V VREF = +5V f = 1MHz Figure 10. Adjacent Channel Clock Feedthrough 10 0% 100 90 OUTPUT1: 7FH → 80H VDD = +5V VREF = +5V TIME – 1µs/DIV OUT1 5mV/DIV CS 5V/DIV 5mV 1µs 5V Figure 11. Midscale Transition HOURS OF OPERATION AT 150°C 0.01 –0.01 0 –0.005 0.005 0 600100 300 500 C H A N G E I N Z E R O -S C A L E E R R O R – L S B VDD = +4.5V VREF = +4.5V SS = 176 PCS VREFL = 0V 200 400 Figure 12. Zero-Scale Error Accelerated by Burn-In

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AD8802/AD8804 REV. 0–6– HOURS OF OPERATION AT 150°C 0.04 –0.04 0 –0.02 0.02 0 600200 300 500 VDD = +4.5V VREF = +4.5V SS = 176 PCS x + 2σ C H A N G E I N F U L L -S C A L E E R R O R – L S B x x – 2σ 100 400 Figure 13. Full-Scale Error Accelerated by Burn-In HOURS OF OPERATION AT 150°C 1.0 –1.0 0 –0.5 0.5 IN P U T R E S IS T A N C E D R IF T – k Ω 0 600200 300 400 VDD = +4.5V VREF = +4.5V CODE = 55H SS = 176 PCS x + 2σ x x – 2σ 100 500 Figure 14. REF Input Resistance Accelerated by Burn-In OPERATION The AD8802/AD8804 provides twelve channels of program- mable voltage output adjustment capability. Changing the pro- grammed output voltage of each DAC is accomplished by clocking in a 12-bit serial data word into the SDI (Serial Data Input) pin. The format of this data word is four address bits, MSB first, followed by 8 data bits, MSB first. Table I provides the serial register data word format. The AD8802/AD8804 has the following address assignments for the ADDR decode which determines the location of the DAC register receiving the serial register data in Bits B7 through B0: DAC# = A3 × 8 + A2 × 4 + A1 × 2 + A0 + 1 DAC outputs can be changed one at a time in random se- quence. The fast serial-data loading of 33 MHz makes it pos- sible to load all 12 DACs in as little time as 4.6 µs (13 × 12 × 30 ns). The exact timing requirements are shown in Figure 15. Table I. Serial-Data Word Format ADDR DATA B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB MSB LSB 211 210 29 28 27 26 25 24 23 22 21 20 The AD8802 offers a midscale preset activated by the RS pin simplifying initial setting conditions at first power-up. The AD8804 has both a VREFH and a VREFL pin to establish indepen- dent positive full-scale and zero-scale settings to optimize reso- lution. Both parts offer a power shutdown SHDN which places the DAC structure in a zero power consumption state resulting in only leakage currents being consumed from the power supply and VREF inputs. In shutdown mode the DACX register settings are maintained. When returning to operational mode from power shutdown the DAC outputs return to their previous volt- age settings. A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DAC REGISTER LOAD 1 0 1 0 1 0 +5V 0V SDI CLK CS VOUT Figure 15a. Timing Diagram AX OR DX AX OR DX 1 0 1 0 1 0 +5V 0V SDI (DATA IN) CLK CS VOUT ±1/2 LSB ±1/2 LSB ERROR BAND tCSHtCL tCSS tDS tDH tCS1 DETAIL SERIAL DATA INPUT TIMING (RS = "1") tCSW tCH tS Figure 15b. Detail Timing Diagram tS tRS ±1 LSB ±1 LSB ERROR BAND 1 0 +5V 2.5V RS VOUT RESET TIMING Figure 15c. Reset Timing Diagram

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AD8802/AD8804 REV. 0 –7– PROGRAMMING THE OUTPUT VOLTAGE The output voltage range is determined by the external refer- ence connected to VREFH and VREFL pins. See Figure 16 for a simplified diagram of the equivalent DAC circuit. In the case of the AD8802 its VREFL is internally connected to GND and therefore cannot be offset. VREFH can be tied to VDD and VREFL can be tied to GND establishing a basic rail-to-rail voltage out- put programming range. Other output ranges are established by the use of different external voltage references. The general transfer equation which determines the programmed output voltage is: VO (Dx) = (Dx)/256 × (VREFH – VREFL) + VREFL Eq. 1 where Dx is the data contained in the 8-bit DACx register. MSB OX 2R R P CH N CH TO OTHER DACS R 2R 2R 2R GND VREFL LSB DAC REGISTER D6 D0 D7 VREFH ... ... ... Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit For example, when VREFH = +5 V and VREFL = 0 V, the follow- ing output voltages will be generated for the following codes: Output State D VOx (VREFH = +5 V, VREFL = 0 V) 255 4.98 V Full Scale 128 2.50 V Half Scale (Midscale Reset Value) 1 0.02 V 1 LSB 0 0.00 V Zero Scale REFERENCE INPUTS (VREFH, VREFL) The reference input pins set the output voltage range of all twelve DACs. In the case of the AD8802 only the VREFH pin is available to establish a user designed full-scale output voltage. The external reference voltage can be any value between 0 and VDD but must not exceed the VDD supply voltage. The AD8804 has access to the VREFL which establishes the zero-scale output voltage, any voltage can be applied between 0 V and VDD. VREFL can be smaller or larger in voltage than VREFH since the DAC design uses fully bidirectional switches as shown in Figure 16. The input resistance to the DAC has a code dependent variation which has a nominal worst case measured at 55H, which is ap- proximately 1.2 kΩ. When VREFH is greater than VREFL, the REFL reference must be able to sink current out of the DAC ladder, while the REFH reference is sourcing current into the DAC ladder. The DAC design minimizes reference glitch cur- rent maintaining minimum interference between DAC channels during code changes. DAC OUTPUTS (O1–O12) The twelve DAC outputs present a constant output resistance of approximately 5 kΩ independent of code setting. The distribu- tion of ROUT from DAC-to-DAC typically matches within ±1%. However device-to-device matching is process lot dependent having a ±20% variation. The change in ROUT with temperature has a 500 ppm/°C temperature coefficient. During power shut- down all twelve outputs are open-circuited. CS CLK SDI SHDN AD8802/AD8804 D7 D0 ADDR DEC EN D11 D10 D9 D8 D7 SER REG D D0 DAC REG #1 R VDD D7 D0 DAC 12DAC REG #12 R DAC 1 8 O1 O2 O4 O5 O6 O7 O8 O9 O10 O11 O12 VREFH GND RS (AD8802 ONLY) VREFL (AD8804 ONLY) O3 Figure 17. Block Diagram DIGITAL INTERFACING The AD8802/AD8804 contains a standard three-wire serial in- put control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. Fig- ure 17 block diagram shows more detail of the internal digital circuitry. When CS is taken active low, the clock can load data into the serial register on each positive clock edge, see Table II. Table II. Input Logic Control Truth Table CS CLK Register Activity 1 X No effect. 0 P Shifts Serial Register One bit loading the next bit in from the SDI pin. P 1 Clock should be high when the CS returns to the inactive state. P = Positive Edge, X = Don’t Care. The data setup and data hold times in the specification table determine the data valid time requirements. The last 12 bits of the data word entered into the serial register are held when CS returns high. At the same time CS goes high it gates the address decoder which enables one of the twelve positive-edge triggered DAC registers, see Figure 18 detail.

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AD8802/AD8804 REV. 0–8– ... DAC 12 ADDR DECODE SERIAL REGISTER CS CLK SDI DAC 2 DAC 1 Figure 18. Equivalent Control Logic The target DAC register is loaded with the last eight bits of the serial data-word completing one DAC update. Twelve separate 12-bit data words must be clocked in to change all twelve out- put settings. All digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 19. Applies to digital input pins CS, SDI, RS, SHDN, CLK LOGIC 1kΩ Figure 19. Equivalent ESD Protection Circuit Digital inputs can be driven by voltages exceeding the AD8802/ AD8804 VDD supply value. This allows 5 V logic to interface directly to the part when it is operated at 3 V. APPLICATIONS Supply Bypassing Precision analog products, such as the AD8802/AD8804, re- quire a well filtered power source. Since the AD8802/AD8804 operate from a single +3 V to +5 V supply, it seems convenient to simply tap into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which generates noise in the 20 kHz to 1 MHz range. In addition, fast logic gates can generate glitches hundred of millivolts in amplitude due to wiring resistances and inductances. If possible, the AD8802/AD8804 should be powered directly from the system power supply. This arrangement, shown in Fig- ure 20, will isolate the analog section from the logic switching transients. Even if a separate power supply trace is not available, however, generous supply bypassing will reduce supply-line in- duced errors. Local supply bypassing consisting of a 10 µF tan- talum electrolytic in parallel with a 0.1 µF ceramic capacitor is recommended (Figure 21). TTL/CMOS LOGIC CIRCUITS +5V POWER SUPPLY 10µF TANT 0.1µF + AD8802/ AD8804 Figure 20. Use Separate Traces to Reduce Power Supply Noise AD8802/ AD8804 VDD DGND 10µF 0.1µF + +5V Figure 21. Recommended Supply Bypassing for the AD8802/AD8804 Buffering the AD8802/AD8804 Output In many cases, the nominal 5 kΩ output impedance of the AD8802/AD8804 is sufficient to drive succeeding circuitry. If a lower output impedance is required, an external amplifier can be added. Several examples are shown in Figure 22. One ampli- fier of an OP291 is used as a simple buffer to reduce the output resistance of DAC A. The OP291 was chosen primarily for its rail-to-rail input and output operation, but it also offers opera- tion to less than 3 V, low offset voltage, and low supply current. The next two DACs, B and C, are configured in a summing arrangement where DAC C provides the coarse output voltage setting and DAC B can be used for fine adjustment. The inser- tion of R1 in series with DAC B attenuates its contribution to the voltage sum node at the DAC C output. VH VL VREFH VDD +5V GNDVREFL DIGITAL INTERFACING OMITTED FOR CLARITY R1 100kΩ OP291 AD8802/ AD8804 SIMPLE BUFFER 0V TO 5V SUMMER CIRCUIT WITH FINE TRIM ADJUSTMENT VH VL VH VL Figure 22. Buffering the AD8802/AD8804 Output Increasing Output Voltage Swing An external amplifier can also be used to extend the output volt- age swing beyond the power supply rails of the AD8802/AD8804. This technique permits an easy digital interface for the DAC, while expanding the output swing to take advantage of higher voltage external power supplies. For example, DAC A of Fig- ure 23 is configured to swing from –5 V to +5 V. The actual output voltage is given by: VOUT = 1+ R F RS     × D 256 × 5V( ) – 5V where D is the DAC input value (i.e., 0 to 255). This circuit can be combined with the “fine/coarse” circuit of Figure 22 if, for example, a very accurate adjustment around 0 V is desired.

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AD8802/AD8804 REV. 0 –9– A VDD VREFH GND VREFL AD8802/ AD8804 B +5V +12V –5V OP191 OP193 RF 100kΩ RS 100kΩ –5V TO +4.98V 0V TO +10V 100kΩ 100kΩ +5V AD8804 ONLY Figure 23. Increasing Output Voltage Swing DAC B of Figure 24 is in a noninverting gain of two configura- tions, which increases the available output swing to +10 V. The feedback resistors can be adjusted to provide any scaling of the output voltage, within the limits of the external op amp power supplies. Microcomputer Interfaces The AD8802/AD8804 serial data input provides an easy inter- face to a variety of single-chip microcomputers (µCs). Many µCs have a built-in serial data capability that can be used for com- municating with the DAC. In cases where no serial port is pro- vided, or it is being used for some other purpose (such as an RS-232 communications interface), the AD8802/AD8804 can easily be addressed in software. Twelve data bits are required to load a value into the AD8802/ AD8804 (4 bits for the DAC address and 8 bits for the DAC value). If more than 12 bits are transmitted before the Chip Se- lect input goes high, the extra (i.e., the most-significant) bits are ignored. This feature is valuable because most µCs only transmit data in 8-bit increments. Thus, the µC will send 16 bits to the DAC instead of 12 bits. The AD8802/AD8804 will only re- spond to the last 12 bits clocked into the SDI port, however, so the serial data interface is not affected. An 8051 µC Interface A typical interface between the AD8802/AD8804 and an 8051 µC is shown in Figure 24. This interface uses the 8051’s internal serial port. The serial port is programmed for Mode 0 opera- tion, which functions as a simple 8-bit shift register. The 8051’s Port 3.0 pin functions as the serial data output, while Port 3.1 serves as the serial clock. When data is written to the Serial Buffer Register (SBUF, at Special Function Register location 99H), the data is automati- cally converted to serial format and clocked out via Port 3.0 and Port 3.1. After 8 bits have been transmitted, the Transmit Inter- rupt flag (SCON.1) is set and the next 8 bits can be transmitted. The AD8802 and AD8804 require the Chip Select to go low at the beginning of the serial data transfer. In addition, the SCLK input must be high when the Chip Select input goes high at the end of the transfer. The 8051’s serial clock meets this require- ment, since Port 3.1 both begins and ends the serial data in the high state. +5V P3.0 P3.1 P1.3 P1.2 P1.1 SERIAL DATA SHIFT REGISTER RxD TxD SHIFT CLOCK 1.11.21.3PORT 1 SBUF 8051 µC 0.1µF 10µF O1 O12 GND AD8802 SDI SCLK RESET SHDN CS VREFHVDD Figure 24. Interfacing the 8051 µC to an AD8802/AD8804, Using the Serial Port Software for the 8051 Interface A software for the AD8802/AD8804 to 8051 interface is shown in Listing 1. The routine transters the 8-bit data stored at data memory location DAC_VALUE to the AD8802/AD8804 DAC addressed by the contents of location DAC_ADDR. The subroutine begins by setting appropriate bits in the Serial Control register to configure the serial port for Mode 0 opera- tion. Next the DAC’s Chip Select input is set low to enable the AD8802/AD8804. The DAC address is obtained from memory location DAC_ADDR, adjusted to compensate for the 8051’s serial data format, and moved to the serial buffer register. At this point, serial data transmission begins automatically. When all 8 bits have been sent, the Transmit Interrupt bit is set, and the subroutine then proceeds to send the DAC value stored at location DAC_VALUE. Finally the Chip Select input is re- turned high, causing the appropriate AD8802/AD8804 output voltage to change, and the subroutine ends. The 8051 sends data out of its shift register LSB first, while the AD8802/AD8804 require data MSB first. The subroutine there- fore includes a BYTESWAP subroutine to reformat the data. This routine transfers the MSB-first byte at location SHIFT1 to an LSB-first byte at location SHIFT2. The routine rotates the MSB of the first byte into the carry with a Rotate Left Carry in- struction, then rotates the carry into the MSB of the second byte with a Rotate Right Carry instruction. After 8 loops, SHIFT2 contains the data in the proper format. The BYTESWAP routine in Listing 1 is convenient because the DAC data can be calculated in normal LSB form. For example, producing a ramp voltage on a DAC is simply a matter of re- peatedly incrementing the DAC_VALUE location and calling the LD_8802 subroutine. If the µC’s hardware serial port is being used for other purposes, the AD8802/AD8804 DAC can be loaded by using the parallel port. A typical parallel interface is shown in Figure 25. The se- rial data is transmitted to the DAC via the 8051’s Port 1.6 out- put, while Port 1.6 acts as the serial clock. Software for the interface of Figure 25 is contained in Listing 2. The subroutine will send the value stored at location DAC_VALUE to the AD8802/AD8804 DAC addressed by location DAC_ADDR. The program begins by setting the AD8802/AD8804’s Serial Clock and Chip Select inputs high, then setting Chip Select low

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