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AD9218BSTZ-105

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AD9218BSTZ-105

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Part Number AD9218BSTZ-105
Manufacturer Analog Devices Inc.
Description IC ADC 10BIT DUAL 105MSPS 48LQFP
Datasheet AD9218BSTZ-105 Datasheet
Package 48-LQFP
In Stock 12,636 piece(s)
Unit Price $ 34.4500 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 24 - Sep 29 (Choose Expedited Shipping)
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Part Number # AD9218BSTZ-105 (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD9218BSTZ-105 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD9218BSTZ-105Datasheet
Package48-LQFP
Series-
Number of Bits10
Sampling Rate (Per Second)105M
Number of Inputs2
Input TypeDifferential, Single Ended
Data InterfaceParallel
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters2
ArchitecturePipelined
Reference TypeInternal
Voltage - Supply, Analog2.7 V ~ 3.6 V
Voltage - Supply, Digital2.7 V ~ 3.6 V
FeaturesSimultaneous Sampling
Operating Temperature-40°C ~ 85°C
Package / Case48-LQFP
Supplier Device Package48-LQFP (7x7)
Mounting Type-

AD9218BSTZ-105 Datasheet

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10-Bit, 40/65/80/105 MSPS 3 V Dual Analog-to-Digital Converter AD9218 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. FEATURES Dual 10-bit, 40 MSPS, 65 MSPS, 80 MSPS, and 105 MSPS ADC Low power: 275 mW at 105 MSPS per channel On-chip reference and track-and-hold 300 MHz analog bandwidth each channel SNR = 57 dB @ 41 MHz, Encode = 80 MSPS 1 V p-p or 2 V p-p analog input range each channel 3.0 V single-supply operation (2.7 V to 3.6 V) Power-down mode for single-channel operation Twos complement or offset binary output mode Output data alignment mode Pin compatible with the 8-bit AD9288 –75 dBc crosstalk between channels APPLICATIONS Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes I and Q communications Ultrasound equipment FUNCTIONAL BLOCK DIAGRAM 0 20 01 -0 01 AD9218 REF TIMINGENCODE A / 10 / 10 / 10 / 10 GND AINA D9A TO D0A USER SELECT NO. 1 USER SELECT NO. 2 DATA FORMAT/ GAIN D9B TO D0B AINA AINB AINB REFINA REFINB REFOUT ENCODE B TIMING T/H T/H ADC ADC OUTPUT REGISTER OUTPUT REGISTER VD VDD Figure 1. GENERAL DESCRIPTION The AD9218 is a dual 10-bit monolithic sampling analog-to- digital converter with on-chip track-and-hold circuits. The product is low cost, low power, and is small and easy to use. The AD9218 operates at a 105 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and a clock for full operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic. The clock input is TTL/CMOS compatible and the 10-bit digital outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. User-selectable options offer a combination of power-down modes, digital data formats, and digital data timing schemes. In power-down mode, the digital outputs are driven to a high impedance state. PRODUCT HIGHLIGHTS 1. Low Power. Only 275 mW power dissipation per channel at 105 MSPS. Other speed grades proportionally scaled down while maintaining high ac performance. 2. Pin Compatibility Upgrade. Allows easy migration from 8-bit to 10-bit devices. Pin compatible with the 8-bit AD9288 dual ADC. 3. Easy to Use. On-chip reference and user controls provide flexibility in system design. 4. High Performance. Maintains 54 dB SNR at 105 MSPS with a Nyquist input. 5. Channel Crosstalk. Very low at –75 dBc. 6. Fabricated on an Advanced CMOS Process. Available in a 48-lead low profile quad flat package (7 mm × 7 mm LQFP) specified over the industrial temperature range (−40°C to +85°C).

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AD9218 Rev. C | Page 2 of 28 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 4 AC Specifications.......................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams.......................................................................... 6 Absolute Maximum Ratings............................................................ 8 Explanation of Test Levels ........................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Terminology .................................................................................... 10 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 13 Theory of Operation ...................................................................... 18 Using the AD9218 ENCODE Input......................................... 18 Digital Outputs ........................................................................... 18 Analog Input ............................................................................... 18 Voltage Reference ....................................................................... 19 Timing ......................................................................................... 19 User Select Options.................................................................... 19 Application Information ........................................................... 19 AD9218/AD9288 Customer PCB BOM...................................... 20 Evaluation Board ............................................................................ 21 Power Connector........................................................................ 21 Analog Inputs ............................................................................. 21 Voltage Reference ....................................................................... 21 Clocking....................................................................................... 21 Data Outputs............................................................................... 21 Data Format/Gain ...................................................................... 21 Timing ......................................................................................... 21 Troubleshooting.......................................................................... 21 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25 REVISION HISTORY 12/06—Rev. B to Rev. C Updated Format..................................................................Universal Changes to DC Specifications......................................................... 3 1/04—Rev. A. to Rev. B Updated format...................................................................Universal Changes to General Description .................................................... 1 Changes to DC Specifications......................................................... 3 Changes to Switching Specifications.............................................. 6 Added AD9218/AD9288 Customer PCB BOM section ........... 20 Added Evaluation Board section .................................................. 21 7/03—Rev. 0 to Rev. A Updated Ordering Guide................................................................. 6 Changes to Terminology section ................................................... .8 Changes to Figure 17b.................................................................... 19 Updated Outline Dimensions ....................................................... 24

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AD9218 Rev. C | Page 3 of 28 SPECIFICATIONS DC SPECIFICATIONS VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted. Table 1. AD9218BST-40/-65 AD9218BST-80/-105 Parameter Temp Test Level Min Typ Max Min Typ Max Unit RESOLUTION 10 10 Bits ACCURACY No Missing Codes1 Full VI Guaranteed, not tested Guaranteed, not tested Offset Error2 25°C I –18 2 18 –18 2 18 LSB Gain Error2 25°C I –2 3 8 –2 3.5 8 % FS Differential Nonlinearity (DNL) 25°C I –1 ±0.3/±0.6 1/1.3 –1 ±0.5/±0.8 1.2/1.7 LSB Full VI ±0.8 ±0.6/±0.9 LSB Integral Nonlinearity (INL) 25°C I –1/–1.6 ±0.3/±1 1/1.6 –1.35/–2.7 ±0.75/±2 +1.35/2.7 LSB Full VI ±1 ±1/±2.3 LSB TEMPERATURE DRIFT Offset Error Full V 10 4 ppm/°C Gain Error2 Full V 80 100 ppm/°C Reference Full V 40 40 ppm/°C REFERENCE Internal Reference Voltage 25°C I 1.18 1.24 1.28 1.18 1.24 1.28 V (REFOUT) Input Resistance (REFINA, REFINB) Full VI 9 11 13 9 11 13 kΩ ANALOG INPUTS Differential Input Voltage Range (AIN, AIN)3 Full V 1 or 2 1 V Common-Mode Voltage3 Full V VD/3 VD/3 V Input Resistance Full VI 8 10 14 8 10 14 kΩ Input Capacitance 25°C V 3 3 pF POWER SUPPLY VD Full IV 2.7 3 3.6 2.7 3 3.6 V VDD Full IV 2.7 3 3.6 2.7 3 3.6 V Supply Currents IVD (VD = 3.0 V)4 Full VI 108/117 113/130 172/183 175/188 mA IVDD (VDD = 3.0 V)4 25°C V 7/11 13/17 mA Power Dissipation DC5 Full VI 325/350 340/390 515/550 525/565 mW IVD Power-Down Current6 Full VI 20 22 mA Power Supply Rejection Ratio 25°C I ±1 ±1 mV/V 1 No missing codes across industrial temperature range guaranteed for 40 MSPS, 65 MSPS, and 80 MSPS grades. No missing codes at room temperature guaranteed for 105 MSPS grade. 2 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) 65 grade in 2 V p-p range, 40, 80, 105 grades in 1 V p-p range. 3 (AIN –AIN) = ±0.5 V in 1 V range (full scale), (AIN – AIN) = ±1 V in 2 V range (full scale). The analog inputs self-bias to VD/3. This common-mode voltage can be overdriven externally by a low impedance source by ±300 mV (differential drive, gain = 1) or ±150 mV (differential drive, gain = 2). 4 AC power dissipation measured with rated encode and a 10.3 MHz analog input @ 0.5 dBFS, CLOAD = 5 pF. 5 DC power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = 0). 6 In power-down state, IVDD = ±10 μA typical (all grades).

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AD9218 Rev. C | Page 4 of 28 DIGITAL SPECIFICATIONS VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted. Table 2. Test AD9218BST-40/-65 AD9218BST-80/-105 Parameter Temp Level Min Typ Max Min Typ Max Unit DIGITAL INPUTS Encode Input Common Mode Full V VD/2 VD/2 V Encode 1 Voltage Full VI 2 2 V Encode 0 Voltage Full VI 0.8 0.8 V Encode Input Resistance Full VI 1.8 2.0 2.3 1.8 2.0 2.3 kΩ Logic 1 Voltage—S1, S2, DFS Full VI 2 2 V Logic 0 Voltage—S1, S2, DFS Full VI 0.8 0.8 V Logic 1 Current—S1 Full VI –50 ±0 50 –50 ±0 50 μA Logic 0 Current—S1 Full VI –400 –230 –50 –400 –230 –50 μA Logic 1 Current—S2 Full VI 50 230 400 50 230 400 μA Logic 0 Current—S2 Full VI –50 ±0 50 –50 ±0 50 μA Logic 1 Current—DFS Full VI 30 100 200 30 100 200 μA Logic 0 Current—DFS Full VI –400 –230 –50 –400 –230 –50 μA Input Capacitance—S1, S2, Encode Inputs 25°C V 2 2 pF Input Capacitance DFS 25°C V 4.5 4.5 pF DIGITAL OUTPUTS Logic 1 Voltage Full VI 2.45 2.45 V Logic 0 Voltage Full VI 0.05 0.05 V Output Coding Twos complement or offset binary Twos complement or offset binary

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AD9218 Rev. C | Page 5 of 28 AC SPECIFICATIONS VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted. Table 3. Test AD9218BST-40/-65 AD9218BST-80/-105 Parameter Temp Level Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE1 Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz 25°C I 58/55 59/57 57/53 58/55 dB fIN = Nyquist2 25°C I –/54 59/56 55/52 57/54 dB Signal-to-Noise and Distortion (SINAD) (With Harmonics) fIN = 10.3 MHz 25°C I 58/54 59/56 56/52 58/53 dB fIN = Nyquist2 25°C I –/53 59/55 55/51 57/53 dB Effective Number of Bits fIN = 10.3 MHz 25°C I 9.4/8.8 9.6/9.1 9.1/8.4 9.4/8.6 Bits fIN = Nyquist2 25°C I –/8.6 9.6/8.9 9/8.3 9.3/8.6 Bits Second Harmonic Distortion fIN = 10.3 MHz 25°C I –72/–66 –89/–77 –69/–60 –77/–68 dBc fIN = Nyquist2 25°C I –/–63 –89/–72 –65/–57 –76/–66 dBc Third Harmonic Distortion fIN = 10.3 MHz 25°C I –68/–62 –79/–68 –62/–57 –71/–63 dBc fIN = Nyquist2 25°C I –/–60 –78/–64 –63/–57 –73/–69 dBc Spurious Free Dynamic Range (SFDR) fIN = 10.3 MHz 25°C I –68/–62 –79/–67 –62/–57 –69/–62 dBc fIN = Nyquist2 25°C I –/–60 –78/–64 –63/–57 –70/–63 dBc Two-Tone Intermodulation Distortion (IMD) fIN1 = 10 MHz, fIN2 = 11 MHz at –7 dBFS 25°C V –74/–73 dBc fIN1 = 30 MHz, fIN2 = 31 MHz at –7 dBFS 25°C V –73/–73 –77/–67 dBc Analog Bandwidth, Full Power 25°C V 300 300 MHz Crosstalk 25°C V –75 –75 dBc 1 AC specifications based on an analog input voltage of –0.5 dBFS at 10.3 MHz, unless otherwise noted. AC specifications for 40, 80, 105 grades are tested in 1 V p-p range and driven differentially. AC specifications for 65 grade are tested in 2 V p-p range and driven differentially. 2 The 65, 80, and 105 grades are tested close to Nyquist for that grade: 31 MHz, 39 MHz, and 51 MHz for the 65, 80, and 105 grades, respectively.

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AD9218 Rev. C | Page 6 of 28 SWITCHING SPECIFICATIONS VDD = 3.0 V, V = 3.0 V; external reference, unless otherwise noted. D Table 4. Test AD9218BST-40/-65 AD9218BST-80/-105 Parameter Temp Level Min Typ Max Min Typ Max Unit ENCODE INPUT PARAMETERS Maximum Encode Rate Full VI 40/65 80/105 MSPS Minimum Encode Rate Full IV 20/20 20/20 MSPS Encode Pulse Width High (tEH) Full IV 7/6 5/3.8 ns Encode Pulse Width Low (tEL) Full IV 7/6 5/3.8 ns Aperture Delay (tA) 25°C V 2 2 ns Aperture Uncertainty (Jitter) 25°C V 3 3 ps rms DIGITAL OUTPUT PARAMETERS Output Valid Time (tV) Full VI 2.5 2.5 ns 1 Output Propagation Delay (tPD)1 Full VI 4.5 7 4.5 6 ns Output Rise Time (tR) 25°C V 1 1.0 ns Output Fall Time (tF) 25°C V 1.2 1.2 ns Out-of-Range Recovery Time 25°C V 5 5 ns Transient Response Time 25°C V 5 5 ns Recovery Time from Power-Down 25°C V 10 10 Cycles Pipeline Delay Full IV 5 5 Cycles 1 t and tV PD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 5 pF or a dc current of ±40 μA. Rise and fall times are measured from 10% to 90%. TIMING DIAGRAMS 02 00 1- 0 02 1/fS tA tEH tEL tPD tV SAMPLE N ENCODE A ENCODE B D9A TO D0A D9B TO D0B AINA AINB DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N SAMPLE N + 1 SAMPLE N + 5 SAMPLE N + 6 SAMPLE N + 2 SAMPLE N + 3 SAMPLE N + 4 Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing

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AD9218 Rev. C | Page 7 of 28 0 20 01 -0 0 3 1/fS tA tEH tEL tPD tV SAMPLE N ENCODE A ENCODE B D9A TO D0A D9B TO D0B AINA AINB DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1 SAMPLE N + 1 SAMPLE N + 2 SAMPLE N + 7 SAMPLE N + 8 SAMPLE N + 3 SAMPLE N + 4 SAMPLE N + 5 SAMPLE N + 6 Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing 02 00 1- 0 04 1/fS tA tEH tEL tPD tV SAMPLE N ENCODE A ENCODE B D9A TO D0A D9B TO D0B AINA AINB DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N – 11 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1 SAMPLE N + 1 SAMPLE N + 2 SAMPLE N + 7 SAMPLE N + 8 SAMPLE N + 3 SAMPLE N + 4 SAMPLE N + 5 SAMPLE N + 6 DATA N + 2 Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing

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AD9218 Rev. C | Page 8 of 28 ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Table 5. Parameter Rating I. 100% production tested. VD, V 4 V DD II. 100% production tested at 25°C and sample tested at specified temperatures. Analog Inputs –0.5 V to VD + 0.5 V Digital Inputs –0.5 V to V + 0.5 V DD REFIN Inputs –0.5 V to VD + 0.5 V III. Sample tested only. Digital Output Current 20 mA IV. Parameter is guaranteed by design and characterization testing. Operating Temperature –55°C to +125°C Storage Temperature –65°C to +150°C Maximum Junction Temperature 150°C V. Parameter is a typical value only. Maximum Case Temperature 150°C θA (measured on a 4-layer board with solid ground plane) 57°C/W VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range. 100% production tested at temperature extremes for military devices. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. User Select Modes S1 S2 Power-Down and Data Alignment Settings 0 0 Power down both Channel A and Channel B. 0 1 Power down Channel B only. 1 0 Normal operation (data align disabled). 1 1 Data align enabled (data from both channels available on rising edge of Clock A. Channel B data is delayed by a ½ clock cycle.) ESD CAUTION

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AD9218 Rev. C | Page 9 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 0 20 01 -0 0 5 GND V D E N C A V D D G N D D 9 A ( M S B ) D 8 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A V D E N C B V D D G N D (M S B ) D 9 B D 8 B D 7 B D 6 B D 5 B D 4 B D 3 B D 2 B S1 S2 GND AINA AINA DFS/GAIN AINB AINB REFINA REFINB D1A GND VDD D1B D0A GND GND D0B GND VD REFOUT VD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AD9218 TOP VIEW (Not to Scale) Figure 5. Pin Configuration Table 7. Pin Function Descriptions Pin Number Mnemonic Description GND Ground. 1, 12, 16, 27, 29, 32, 34, 45 2 AINA Analog Input for Channel A. AAIN3 Analog Input for Channel A (Complementary). 4 DFS/GAIN Data Format Select and Analog Input Gain Mode. Low = offset binary output available, 1 V p-p supported; high = twos complement output available, 1 V p-p supported; floating = offset binary output available, 2 V p-p supported; set to V = twos complement output available, 2 V p-p supported. REF 5 REFINA Reference Voltage Input for Channel A. 6 REFOUT Internal Reference Voltage. 7 REFINB Reference Voltage Input for Channel B. 8 S1 User Select No. 1. See Table 6. 9 S2 User Select No. 2. See Table 6. 10 BAIN Analog Input for Channel B (Complementary). 11 AINB Analog Input for Channel B. 13, 30, 31, 48 VD Analog Supply (3 V). 14 ENC B Clock Input for Channel B. 15, 28, 33, 46 V DD Digital Supply (2.5 V to 3.6 V). 17 to 26 D9 to D0 B B Digital Output for Channel B (D9 = MSB). B 35 to 44 D0A to D9A Digital Output for Channel A (D9A = MSB). 47 ENCA Clock Input for Channel A.

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