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AD9231BCPZ-40

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AD9231BCPZ-40

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Part Number AD9231BCPZ-40
Manufacturer Analog Devices Inc.
Description IC ADC 12BIT 40MSPS 64LFCSP
Datasheet AD9231BCPZ-40 Datasheet
Package 64-VFQFN Exposed Pad, CSP
In Stock 1,211 piece(s)
Unit Price $ 22.5168 *
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 9 - Aug 14 (Choose Expedited Shipping)
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Part Number # AD9231BCPZ-40 (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD9231BCPZ-40 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD9231BCPZ-40Datasheet
Package64-VFQFN Exposed Pad, CSP
Series-
Number of Bits12
Sampling Rate (Per Second)40M
Number of Inputs2
Input TypeDifferential, Single Ended
Data InterfaceParallel
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters2
ArchitecturePipelined
Reference TypeInternal
Voltage - Supply, Analog1.7 V ~ 1.9 V
Voltage - Supply, Digital1.7 V ~ 3.6 V
FeaturesSimultaneous Sampling
Operating Temperature-40°C ~ 85°C
Package / Case64-VFQFN Exposed Pad, CSP
Supplier Device Package64-LFCSP-VQ (9x9)
Mounting Type-

AD9231BCPZ-40 Datasheet

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12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9231 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 71.3 dBFS at 9.7 MHz input 69.0 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 83 dBc at 200 MHz input Low power 32 mW per channel at 20 MSPS 71 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.40 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR FUNCTIONAL BLOCK DIAGRAM VIN+A VIN–A VREF SENSE VCM RBIAS VIN–B VIN+B ORA D0A D11A DCOA DRVDD ORB D11B D0B DCOB SDIOGNDAVDD SCLK SPI PROGRAMMING DATA M U X O PT IO N PDWN DFSCLK+ CLK– MODE CONTROLS DCS DUTY CYCLE STABILIZER SYNC DIVIDE 1 TO 8 OEB CSB REF SELECT ADC C M O S O U TP U T B U FF ER ADC C M O S O U TP U T B U FF ER AD9231 08 12 1- 00 1 Figure 1. PRODUCT HIGHLIGHTS 1. The AD9231 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. 3. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes. 4. The AD9231 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.

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AD9231 Data Sheet Rev. B | Page 2 of 36 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Specifications .................................................................. 8 Absolute Maximum Ratings ............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 AD9231-80 .................................................................................. 12 AD9231-65 .................................................................................. 14 AD9231-40 .................................................................................. 15 AD9231-20 .................................................................................. 16 Equivalent Circuits ......................................................................... 17 Theory of Operation ...................................................................... 19 ADC Architecture ...................................................................... 19 Analog Input Considerations .................................................... 19 Voltage Reference ....................................................................... 22 Clock Input Considerations ...................................................... 23 Channel/Chip Synchronization ................................................ 25 Power Dissipation and Standby Mode .................................... 25 Digital Outputs ........................................................................... 26 Timing ......................................................................................... 26 Built-In Self-Test (BIST) and Output Test .................................. 27 Built-In Self-Test (BIST) ............................................................ 27 Output Test Modes ..................................................................... 27 Serial Port Interface (SPI) .............................................................. 28 Configuration Using the SPI ..................................................... 28 Hardware Interface ..................................................................... 29 Configuration Without the SPI ................................................ 29 SPI Accessible Features .............................................................. 29 Memory Map .................................................................................. 30 Reading the Memory Map Register Table ............................... 30 Open Locations .......................................................................... 30 Default Values ............................................................................. 30 Memory Map Register Table ..................................................... 31 Memory Map Register Descriptions ........................................ 33 Applications Information .............................................................. 34 Design Guidelines ...................................................................... 34 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35 REVISION HISTORY 9/2016—Rev. A to Rev. B Changes to Figure 3 .......................................................................... 7 6/2010—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 10/2009—Revision 0: Initial Version

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Data Sheet AD9231 Rev. B | Page 3 of 36 GENERAL DESCRIPTION The AD9231 is a monolithic, dual-channel, 1.8 V supply, 12-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital conver- ter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus. The AD9231 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

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AD9231 Data Sheet Rev. B | Page 4 of 36 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. Parameter Temp AD9231-20/AD9231-40 AD9231-65 AD9231-80 Unit Min Typ Max Min Typ Max Min Typ Max RESOLUTION Full 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full 0.05 ±0.5 0.05 ±0.5 0.05 ±0.5 % FSR Gain Error1 Full −1.5 −1.5 −1.5 % FSR Differential Nonlinearity (DNL)2 Full ±0.30 ±0.40 ±0.40 LSB 25°C ±0.12 ±0.17 ±0.2 LSB Integral Nonlinearity (INL)2 Full ±0.45 ±0.50 ±0.65 LSB 25°C ±0.15 ±0.17 ±0.2 LSB MATCHING CHARACTERISTICS Offset Error 25°C ±0.0 ±0.70 ±0.0 ±0.60 ±0.0 ±0.60 % FSR Gain Error1 25°C 0.3 0.3 0.4 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V Load Regulation Error at 1.0 mA Full 2 2 2 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.25 0.25 0.25 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance3 Full 6 6 6 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current IAVDD2 Full 35.7/49.0 37.7/52.2 69 72.4 80.0 83.4 mA IDRVDD2 (1.8 V) Full 3.0/5.1 7.4 9.1 mA IDRVDD2 (3.3 V) Full 5.9/10.1 14.9 18.3 mA POWER CONSUMPTION DC Input Full 63.5/87.1 122.9 141.8 mW Sine Wave Input2 (DRVDD = 1.8 V) Full 69.7/97.3 73.3/103.0 138.0 143.8 160.4 166.5 mW Sine Wave Input2 (DRVDD = 3.3 V) Full 83.7/121.5 173.4 204 mW Standby Power4 Full 37/37 37 37 mW Power-Down Power Full 2.2 2.2 2.2 mW 1 Measured with 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input and the CLK active.

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Data Sheet AD9231 Rev. B | Page 5 of 36 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. Parameter1 Temp AD9231-20/AD9231-40 AD9231-65 AD9231-80 Unit Min Typ Max Min Typ Max Min Typ Max SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 70.7/71.5 71.4 71.3 dBFS fIN = 30.5 MHz 25°C 70.6/71.3 71.3 71.2 dBFS Full 70.1/70.7 70.5 dBFS fIN = 70 MHz 25°C 70.5/71.0 71.0 70.9 dBFS Full 70.1 dBFS fIN = 200 MHz 25°C 69.0 69.0 69.0 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 70.6/71.4 71.3 71.2 dBFS fIN = 30.5 MHz 25°C 70.6/71.2 71.2 71.1 dBFS Full 70.1/70.6 70.0 dBFS fIN = 70 MHz 25°C 70.4/70.9 70.9 70.8 dBFS Full 70.0 dBFS fIN = 200 MHz 25°C 68 68 68 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 11.4/11.6 11.6 11.5 Bits fIN = 30.5 MHz 25°C 11.4/11.5 11.5 11.5 Bits fIN = 70 MHz 25°C 11.4/11.5 11.5 11.5 Bits fIN = 200 MHz 25°C 11.0 11.0 11.0 Bits WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −95 −95 −93 dBc fIN = 30.5 MHz 25°C −95 −95 −93 dBc Full −81 −81 dBc fIN = 70 MHz 25°C −92/−94 −94 −92 dBc Full −81 dBc fIN = 200 MHz 25°C −83 −83 −83 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 95 95 93 dBc fIN = 30.5 MHz 25°C 95 95 93 dBc Full 81 81 dBc fIN = 70 MHz 25°C 92/94 94 92 dBc Full 81 dBc fIN = 200 MHz 25°C 83 83 83 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz 25°C −98 −98 −97 dBc fIN = 30.5 MHz 25°C −97/−98 −98 −97 dBc Full −90 −90 dBc fIN = 70 MHz 25°C −97/−98 −98 −95 dBc Full −89 dBc fIN = 200 MHz 25°C −92 −92 −92 dBc TWO-TONE SFDR fIN = 28.3 MHz (−7 dBFS), 30.6 MHz (−7 dBFS) 25°C 90 90 90 dBc CROSSTALK2 Full −110 −110 −110 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

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AD9231 Data Sheet Rev. B | Page 6 of 36 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. Parameter Temp AD9231-20/AD9231-40/AD9231-65/AD9231-80 Unit Min Typ Max DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)1 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (CSB)2 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 135 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO1/DCS2) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 130 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, IOH = 50 µA Full 3.29 V High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V DRVDD = 1.8 V High Level Output Voltage, IOH = 50 µA Full 1.79 V High Level Output Voltage, IOH = 0.5 mA Full 1.75 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up.

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Data Sheet AD9231 Rev. B | Page 7 of 36 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. Parameter Temp AD9231-20/AD9231-40 AD9231-65 AD9231-80 Unit Min Typ Max Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate1 Full 3 20/40 3 65 3 80 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 50/25 15.38 12.5 ns CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 3 3 ns DCO Propagation Delay (tDCO) Full 3 3 3 ns DCO to Data Skew (tSKEW) Full 0.1 0.1 0.1 ns Pipeline Delay (Latency) Full 9 9 9 Cycles Wake-Up Time2 Full 350 350 350 µs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. tPD tSKEW tCH tDCO tCLK N – 9 N – 1 N + 1 N + 2 N + 3 N + 5 N + 4 N N – 8 N – 7 N – 6 N – 5 VIN CLK+ CLK– CH A/CH B DATA DCOA/DCOB tA 08 12 1- 00 2 Figure 2. CMOS Output Data Timing tPD tSKEW tCH tDCO tCLK CH A N – 9 CH B N – 9 CH A N – 8 CH B N – 8 CH A N – 7 CH B N – 7 CH A N – 6 CH B N – 6 CH A N – 5 N – 1 N + 1 N + 2 N + 3 N + 5 N + 4 N VIN CLK+ CLK– CH A/CH B DATA AS APPEARS ON CH A OUTPUT PINS DCOA/DCOB tA 08 12 1- 00 3 Figure 3. CMOS Interleaved Output Timing, Output as Appears on Channel A Output Pins

Page 9

AD9231 Data Sheet Rev. B | Page 8 of 36 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.24 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns SYNC CLK+ tHSYNCtSSYNC 08 12 1- 00 4 Figure 4. SYNC Input Timing Requirements

Page 10

Data Sheet AD9231 Rev. B | Page 9 of 36 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +3.9 V VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to DRVDD + 0.3 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V OEB to AGND −0.3 V to DRVDD + 0.3 V PDWN to AGND −0.3 V to DRVDD + 0.3 V D0A/D0B through D11A/D11B to AGND −0.3 V to DRVDD + 0.3 V DCOA/DCOB to AGND −0.3 V to DRVDD + 0.3 V Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature Under Bias 150°C Storage Temperature Range (Ambient) −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL CHARACTERISTICS The exposed paddle is the only ground connection for the chip. The exposed paddle must be soldered to the AGND plane of the user’s circuit board. Soldering the exposed paddle to the user’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 7. Thermal Resistance Package Type Airflow Velocity (m/sec) θJA1, 2 θJC1, 3 θJB1, 4 Unit 64-Lead LFCSP 9 mm × 9 mm (CP-64-4) 0 23 2.0 °C/W 1.0 20 12 °C/W 2.5 18 °C/W 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA. ESD CAUTION

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The helper is super handy, especially if you work with medium size PCB boards as it allows to hold the board steady in every position. It feels pretty sturdy and of good quality.

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