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AD9238BSTZ-20

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AD9238BSTZ-20

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Part Number AD9238BSTZ-20
Manufacturer Analog Devices Inc.
Description IC ADC 12BIT DUAL 20MSPS 64-LQFP
Datasheet AD9238BSTZ-20 Datasheet
Package 64-LQFP
In Stock 1,580 piece(s)
Unit Price $ 22.6800 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 3 - Jun 8 (Choose Expedited Shipping)
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Part Number # AD9238BSTZ-20 (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD9238BSTZ-20 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD9238BSTZ-20Datasheet
Package64-LQFP
Series-
Number of Bits12
Sampling Rate (Per Second)20M
Number of Inputs2
Input TypeDifferential, Single Ended
Data InterfaceParallel
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters2
ArchitecturePipelined
Reference TypeExternal, Internal
Voltage - Supply, Analog2.7 V ~ 3.6 V
Voltage - Supply, Digital2.25 V ~ 3.6 V
FeaturesSimultaneous Sampling
Operating Temperature-40°C ~ 85°C
Package / Case64-LQFP
Supplier Device Package64-LQFP (7x7)
Mounting Type-

AD9238BSTZ-20 Datasheet

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12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter AD9238 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 ©2003–2010 Analog Devices, Inc. All rights reserved. FEATURES Integrated dual 12-bit ADC Single 3 V supply operation (2.7 V to 3.6 V) SNR = 70 dB (to Nyquist, AD9238-65) SFDR = 80.5 dBc (to Nyquist, AD9238-65) Low power: 300 mW/channel at 65 MSPS Differential input with 500 MHz, 3 dB bandwidth Exceptional crosstalk immunity > 85 dB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer Output datamux option APPLICATIONS Ultrasound equipment Direct conversion or IF sampling receivers WB-CDMA, CDMA2000, WiMAX Battery-powered instruments Hand-held scopemeters Low cost, digital oscilloscopes GENERAL DESCRIPTION The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and-hold amplifiers (SHAs) and an integrated voltage reference. The AD9238 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy and to guarantee no missing codes over the full operating temperature range at up to 65 MSPS data rates. The wide bandwidth, differential SHA allows for a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for various applications, including multiplexed systems that switch full- scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate. Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available and can compensate for wide variations in the clock duty cycle, allowing the converter to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format. Out-of-range signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow. FUNCTIONAL BLOCK DIAGRAM VIN+_A VIN–_A REFT_A REFB_A VREF SENSE AGND REFT_B REFB_B VIN+_B VIN–_B OTR_A D11_A TO D0_A OEB_A MUX_SELECT CLK_A CLK_B DCS SHARED_REF PWDN_A PWDN_B DFS OTR_B D11_B TO D0_B OEB_B AVDD AGND DRVDD DRGND 12 AD9238 12 0.5V OUTPUT MUX/ BUFFERS 1212 OUTPUT MUX/ BUFFERS CLOCK DUTY CYCLE STABILIZER MODE CONTROL ADC SHA SHA 02 64 0- 00 1 ADC Figure 1. Fabricated on an advanced CMOS process, the AD9238 is available in a Pb-free, space saving, 64-lead LQFP or LFCSP and is specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. Pin-compatible with the AD9248, 14-bit 20MSPS/ 40 MSPS/65 MSPS ADC. 2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS allow flexibility between power, cost, and performance to suit an application. 3. Low power consumption: AD9238-65: 65 MSPS = 600 mW, AD9238-40: 40 MSPS = 330 mW, and AD9238-20: 20 MSPS = 180 mW. 4. Typical channel isolation of 85 dB @ fIN = 10 MHz. 5. The clock duty cycle stabilizer (AD9238-20/AD9238-40/ AD9238-65) maintains performance over a wide range of clock duty cycles. 6. Multiplexed data output option enables single-port operation from either Data Port A or Data Port B.

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AD9238 Rev. C | Page 2 of 48 TABLE OF CONTENTS Specifications ..................................................................................... 4  DC Specifications ......................................................................... 4  AC Specifications .......................................................................... 5  Digital Specifications ................................................................... 6  Switching Specifications .............................................................. 6  Absolute Maximum Ratings ............................................................ 7  Explanation of Test Levels ........................................................... 7  ESD Caution .................................................................................. 7  Pin Configurations and Function Descriptions............................ 8  Terminology .................................................................................... 10  Typical Performance Characteristics ........................................... 11  Equivalent Circuits ......................................................................... 15  Theory of Operation ...................................................................... 16  Analog Input ............................................................................... 16  Clock Input and Considerations .............................................. 17  Power Dissipation and Standby Mode ..................................... 18  Digital Outputs ........................................................................... 18  Timing .......................................................................................... 18  Data Format ................................................................................ 19  Voltage Reference ....................................................................... 19  AD9238 LQFP Evaluation Board ................................................. 21  Clock Circuitry ........................................................................... 21  Analog Inputs ............................................................................. 21  Reference Circuitry .................................................................... 21  Digital Control logic .................................................................. 21  Outputs ........................................................................................ 21  LQFP Evaluation Board Bill of Materials (BOM) .................. 23  LQFP Evaluation Board Schematics ........................................ 24  LQFP PCB Layers ....................................................................... 28  Dual ADC LFCSP PCB .................................................................. 34  Power Connector ........................................................................ 34  Analog Inputs ............................................................................. 34  Optional Operational Amplifier .............................................. 34  Clock ............................................................................................ 34  Voltage Reference ....................................................................... 34  Data Outputs ............................................................................... 34  LFCSP Evaluation Board Bill of Materials (BOM) ................ 35  LFCSP PCB Schematics ............................................................. 36  LFCSP PCB Layers ..................................................................... 39  Thermal Considerations ............................................................ 44  Outline Dimensions ....................................................................... 45  Ordering Guide .......................................................................... 46  REVISION HISTORY 11/10—Rev. B to Rev. C Changes to Absolute Maximum Ratings Section ......................... 7 Added Figure 4; Renumbered Sequentially .................................. 8 Changes to Analog Input Section ................................................. 16 Deleted Note 1 from Dual ADC LFCSP PCB Section ............... 34 Changes to Outline Dimensions ................................................... 45 4/05—Rev. A to Rev. B Changes to Format and Layout ........................................ Universal Added LFCSP ..................................................................... Universal Changes to Features and Applications ........................................... 1 Changes to General Description and Product Highlights .......... 1 Changes to Figure 1 .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Added Digital Specifications ........................................................... 6 Moved Switching Specifications to ................................................ 6 Changes to Pin Function Descriptions .......................................... 8 Changes to Terminology Section ................................................. 10 Changes to Figure 29 ...................................................................... 15 Changes to Clock Input and Considerations Section ................ 17 Changes to Figure 33 ...................................................................... 18 Changes to Data Format Section .................................................. 19 Added AD9238 LQFP Evaluation Board Section ...................... 21 Added Dual ADC LFCSP PCB Section ....................................... 34 Added Thermal Considerations Section ..................................... 44 Updated Outline Dimensions ....................................................... 45 Changes to Ordering Guide .......................................................... 46

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AD9238 Rev. C | Page 3 of 48 9/03—Rev. 0 to Rev. A Changes to DC Specifications ........................................................ 2 Changes to Switching Specifications ............................................. 3 Changes to AC Specifications ......................................................... 4 Changes to Figure 1 .......................................................................... 4 Changes to Ordering Guide ............................................................ 5 Changes to TPCs 2, 3, and 6 ........................................................... 8 Changes to Clock Input and Considerations Section ................ 13 Added Text to Data Format Section ............................................ 15 Changes to Figure 9 ........................................................................ 16 Added Evaluation Board Diagrams Section ............................... 17 Update Outline Dimensions ......................................................... 24 2/03—Revision 0: Initial Version

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AD9238 Rev. C | Page 4 of 48 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 1. Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full VI 12 12 12 Bits ACCURACY No Missing Codes Guaranteed Full VI 12 12 12 Bits Offset Error Full VI ±0.30 ±1.2 ±0.50 ±1.1 ±0.50 ±1.1 % FSR Gain Error1 Full IV ±0.30 ±2.2 ±0.50 ±2.4 ±0.50 ±2.5 % FSR Differential Nonlinearity (DNL)2 Full V ±0.35 ±0.35 ±0.35 LSB 25°C I ±0.35 ±0.9 ±0.35 ±0.8 ±0.35 ±1.0 LSB Integral Nonlinearity (INL)2 Full V ±0.45 ±0.60 ±0.70 LSB 25°C I ±0.40 ±1.4 ±0.50 ±1.4 ±0.55 ±1.75 LSB TEMPERATURE DRIFT Offset Error Full V ±4 ±4 ±6 μV/°C Gain Error Full V ±12 ±12 ±12 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 ±5 ±35 mV Load Regulation @ 1.0 mA Full V 0.8 0.8 0.8 mV Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 ±2.5 mV Load Regulation @ 0.5 mA Full V 0.1 0.1 0.1 mV INPUT REFERRED NOISE Input Span = 1 V 25°C V 0.54 0.54 0.54 LSB rms Input Span = 2.0 V 25°C V 0.27 0.27 0.27 LSB rms ANALOG INPUT Input Span = 1.0 V Full IV 1 1 1 V p-p Input Span = 2.0 V Full IV 2 2 2 V p-p Input Capacitance3 Full V 7 7 7 pF REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ POWER SUPPLIES Supply Voltages AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD Full IV 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V Supply Current IAVDD2 Full V 60 110 200 mA IDRVDD2 Full V 4 10 14 mA PSRR Full V ±0.01 ±0.01 ±0.01 % FSR POWER CONSUMPTION DC Input4 Full V 180 330 600 mW Sine Wave Input2 Full VI 190 212 360 397 640 698 mW Standby Power5 Full V 2.0 2.0 2.0 mW MATCHING CHARACTERISTICS Offset Error 25°C V ±0.1 ±0.1 ±0.1 % FSR Gain Error 25°C V ±0.05 ±0.05 ±0.05 % FSR 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 29 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).

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AD9238 Rev. C | Page 5 of 48 AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 2. Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 2.4 MHz 25°C V 70.4 70.4 70.3 dB fINPUT = 9.7 MHz Full V 70.2 dB 25°C IV 69.7 70.4 dB fINPUT = 19.6 MHz Full V 70.1 dB 25°C IV 69.7 70.3 dB fINPUT = 32.5 MHz Full V 69.3 dB 25°C IV 68.7 70.0 dB fINPUT = 100 MHz 25°C V 68.7 68.3 67.6 dB SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fINPUT = 2.4 MHz 25°C V 70.2 70.2 70.1 dB fINPUT = 9.7 MHz Full V 70.1 dB 25°C IV 69.3 70.2 dB fINPUT = 19.6 MHz Full V 69.9 dB 25°C IV 69.4 70.1 dB fINPUT = 32.5 MHz Full V 68.9 dB 25°C IV 68.1 69.1 dB fINPUT = 100 MHz 25°C V 67.9 67.9 66.6 dB EFFECTIVE NUMBER OF BITS (ENOB) fINPUT = 2.4 MHz 25°C V 11.5 11.5 11.4 Bits fINPUT = 9.7 MHz Full V 11.4 Bits 25°C IV 11.3 11.5 Bits fINPUT = 19.6 MHz Full V 11.4 Bits 25°C IV 11.3 11.4 Bits fINPUT = 32.5 MHz Full V 11.2 Bits 25°C IV 11.1 11.3 Bits fINPUT = 100 MHz 25°C V 11.1 11.1 10.9 Bits WORST HARMONIC (SECOND or THIRD) fINPUT = 9.7 MHz Full V −84.0 dBc fINPUT = 19.6 MHz Full V −85.0 dBc fINPUT = 35 MHz Full V −80.0 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = 2.4 MHz 25°C V 86.0 86.0 86.0 dBc fINPUT = 9.7 MHz Full V 84.0 dBc 25°C I 76.1 86.0 dBc fINPUT = 19.6 MHz Full V 85.0 dBc 25°C I 76.7 86.0 dBc fINPUT = 32.5 MHz Full V 80.0 dBc 25°C I 72.5 80.5 dBc fINPUT = 100 MHz 25°C V 75.0 dBc CROSSTALK Full V −85.0 −85.0 −85.0 dB

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AD9238 Rev. C | Page 6 of 48 DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 3. Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS High Level Input Voltage Full IV 2.0 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 0.8 V High Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA Low Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA Input Capacitance Full IV 2 2 2 pF LOGIC OUTPUTS1 High Level Output Voltage Full IV DRVDD − 0.05 DRVDD − 0.05 DRVDD − 0.05 V Low Level Output Voltage Full IV 0.05 0.05 0.05 V 1 Output voltage levels measured with capacitive load only on each output. SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 4. Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 20 40 65 MSPS Minimum Conversion Rate Full V 1 1 1 MSPS CLK Period Full V 50.0 25.0 15.4 ns CLK Pulse-Width High1 Full V 15.0 8.8 6.2 ns CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns DATA OUTPUT PARAMETER Output Delay2 (tPD) Full VI 2 3.5 6 2 3.5 6 2 3.5 6 ns Pipeline Delay (Latency) Full V 7 7 7 Cycles Aperture Delay (tA) Full V 1.0 1.0 1.0 ns Aperture Uncertainty (tJ) Full V 0.5 0.5 0.5 ps rms Wake-Up Time3 Full V 2.5 2.5 2.5 ms OUT-OF-RANGE RECOVERY TIME Full V 2 2 2 Cycles 1 The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24). 2 Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 ANALOG INPUT CLOCK DATA OUT N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N MIN 2.0ns, MAX 6.0ns tPD = 02 64 0- 00 2 Figure 2. Timing Diagram

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AD9238 Rev. C | Page 7 of 48 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Table 5. Parameter Rating ELECTRICAL AVDD to AGND −0.3 V to +3.9 V DRVDD to DRGND −0.3 V to +3.9 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +3.9 V Digital Outputs to DRGND −0.3 V to DRVDD + 0.3 V OEB, DFS, CLK, DCS, MUX_SELECT, SHARED_REF to AGND −0.3 V to AVDD + 0.3 V VINA, VINB to AGND −0.3 V to AVDD + 0.3 V VREF to AGND −0.3 V to AVDD + 0.3 V SENSE to AGND −0.3 V to AVDD + 0.3 V REFB, REFT to AGND −0.3 V to AVDD + 0.3 V PDWN to AGND −0.3 V to AVDD + 0.3 V ENVIRONMENTAL1 Operating Temperature −40°C to +85°C Junction Temperature 150°C Lead Temperature (10 sec) 300°C Storage Temperature −65°C to +150°C 1 Typical thermal impedances: 64-lead LQFP, θJA = 54°C/W; 64-lead LFCSP, θJA = 26.4°C/W with heat slug soldered to ground plane. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. EXPLANATION OF TEST LEVELS I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. ESD CAUTION

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AD9238 Rev. C | Page 8 of 48 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 55 54 53 52 51 50 4959 58 57 56 PIN 1 IDENTIFIER 64-LEAD LQFP TOP VIEW (Not to Scale) D4_A D3_A D2_A D1_A D0_A (LSB) DNC DNC DRGND OTR_B D11_B (MSB) D10_B D9_B D8_B D7_B D6_B AD9238 AGND AVDD REFT_A REFB_A VREF SENSE REFB_B AGND VIN–_B VIN+_B VIN+_A VIN–_A AVDD REFT_B C L K _ A S H A R E D _ R E F M U X _S E L E C T O E B _A D 1 1 _ A ( M S B ) D 1 0 _ A D 9 _ A D 8 _ A D R G N D D 7 _ A D 6 _ A D 5 _ A C L K _ B D C S D F S P D W N _B O E B _B D N C D 0 _ B (L S B ) D 1 _ B D 2 _ B D R G N D D 3 _ B D 4 _ B D 5 _ B D N C AGND AGND A V D D D R V D D DRVDD A V D D P D W N _A O T R _A D R V D D DNC = DO NOT CONNECT 02 6 4 0 -0 0 3 Figure 3. 64-Lead LQFP Pin Configuration 64-LEAD LFCSP TOP VIEW (Not to Scale) D4_A D3_A D2_A D1_A D0_A (LSB) DNC DNC DRGND OTR_B D11_B (MSB) D10_B D9_B D8_B D7_B D6_B AD9238 AGND AVDD REFT_A REFB_A VREF SENSE REFB_B AGND VIN–_B VIN+_B VIN+_A VIN–_A AVDD REFT_B C L K _A S H A R E D _R E F M U X _S E L E C T O E B _A D 11 _A ( M S B ) D 10 _A D 9_ A D 8_ A D R G N D D 7_ A D 6_ A D 5_ A C L K _B D C S D F S P D W N _B O E B _B D N C D 0_ B ( L S B ) D 1_ B D 2_ B D R G N D D 3_ B D 4_ B D 5_ B D N C AGND AGND A V D D D R V D D DRVDD A V D D P D W N _A O T R _A D R V D D PIN 1 INDICATOR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NOTES 1. THERE IS AN EXPOSED PAD THAT MUST CONNECT TO AGND. 2. DNC = DO NOT CONNECT. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 02 64 0- 1 03 Figure 4. 64-Lead LFCSP Pin Configuration

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AD9238 Rev. C | Page 9 of 48 Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN–_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Enable Duty Cycle Stabilizer (DCS) Mode (Tie High to Enable). 20 DFS Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement). 21 PDWN_B Power-Down Function Selection for Channel B: Logic 0 enables Channel B. Logic 1 powers down Channel B. (Outputs static, not High-Z.) 22 OEB_B Output Enable Bit for Channel B: Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z. 23, 24, 42, 43 DNC Do Not Connect Pins. Should be left floating. 25 to 27, 30 to 38 D0_B (LSB) to D11_B (MSB) Channel B Data Output Bits. 28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF. 39 OTR_B Out-of-Range Indicator for Channel B. 44 to 51, 54 to 57 D0_A (LSB) to D11_A (MSB) Channel A Data Output Bits. 58 OTR_A Out-of-Range Indicator for Channel A. 59 OEB_A Output Enable Bit for Channel A: Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z. 60 PDWN_A Power-Down Function Selection for Channel A: Logic 0 enables Channel A. Logic 1 powers down Channel A. (Outputs static, not High-Z.) 61 MUX_SELECT Data Multiplexed Mode. (See Data Format section for how to enable; high setting disables output data multiplexed mode). 62 SHARED_REF Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode). 63 CLK_A Clock Input Pin for Channel A. EP For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND.

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John*****astro

May 24, 2020

Well packed in anti-static bags. Repaired my amp perfectly - thank you!

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May 21, 2020

You're my good supplier. I appreciate Heisener Electronics on many levels.

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May 18, 2020

I am satisfied with Heisener company

Brie*****Pratt

May 14, 2020

All OK, fast delivery, good quality. Product works as it should, Nice Seller.

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May 7, 2020

Great dealing with you Guys. Thanks for a very prompt delivery.

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April 30, 2020

Great deal, immediate response and very quick delivery!

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April 25, 2020

The items I want are often in stock and available in small quantities.

Sadi*****tton

April 19, 2020

Went well this time Now have the IC and very pleased.

Mala*****astry

April 11, 2020

Competitively priced set of diodes, tested as described. Quality is about what you would expect for no- or off-brand.

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April 10, 2020

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ISL6151CB-T ISL6151CB-T Renesas Electronics America, IC CONTROLLER HOT PLUG 8-SOIC, 8-SOIC (0.154", 3.90mm Width), - View
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AD9238BSTZ-20

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