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AD9513BCPZ

hot AD9513BCPZ

AD9513BCPZ

For Reference Only

Part Number AD9513BCPZ
Manufacturer Analog Devices Inc.
Description IC CLK BUFFER 1:3 800MHZ 32LFCSP
Datasheet AD9513BCPZ Datasheet
Package 32-VFQFN Exposed Pad, CSP
In Stock 49722 piece(s)
Unit Price $ 12.05 *
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AD9513BCPZ

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AD9513BCPZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Buffers, Drivers
Datasheet AD9513BCPZ Datasheet
Package32-VFQFN Exposed Pad, CSP
Series-
TypeFanout Buffer (Distribution), Divider
Number of Circuits1
Ratio - Input:Output1:3
Differential - Input:OutputYes/Yes
InputClock
OutputCMOS, LVDS
Frequency - Max800MHz
Voltage - Supply3.135 V ~ 3.465 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case32-VFQFN Exposed Pad, CSP
Supplier Device Package32-LFCSP-VQ (5x5)

AD9513BCPZ Datasheet

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800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs Data Sheet AD9513 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust Three 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 300 fs rms Time delays up to 11.6 ns Device configured with 4-level logic pins Space-saving, 32-lead LFCSP APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE FUNCTIONAL BLOCK DIAGRAM 05 59 5- 00 1 CLK CLKB SYNCB RSET VS GND AD9513 VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 SETUP LOGIC OUT0 OUT0B /1. . . /32 LVDS/CMOS OUT1 OUT1B /1. . . /32 LVDS/CMOS OUT2 OUT2B /1. . . /32 LVDS/CMOS ∆t Figure 1. GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independent clock outputs that can be set to either LVDS or CMOS levels. These outputs operate to 800 MHz in LVDS mode and to 250 MHz in CMOS mode. Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment. One of the outputs features a delay element with three selectable full-scale delay values (1.8 ns, 6.0 ns, and 11.6 ns), each with 16 steps of fine adjustment. The AD9513 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ VS. The VREF pin provides a level of ⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels. The AD9513 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9513 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.

Page 3

AD9513 Data Sheet Rev. B | Page 2 of 28 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Clock Input .................................................................................... 3 Clock Outputs ............................................................................... 3 Timing Characteristics ................................................................ 4 Clock Output Phase Noise .......................................................... 6 Clock Output Additive Time Jitter ............................................. 8 SYNCB, VREF, and Setup Pins ................................................... 9 Power .............................................................................................. 9 Timing Diagrams ............................................................................ 10 Absolute Maximum Ratings .......................................................... 11 Thermal Characteristics1 ........................................................... 11 Pin Configuration and Function Descriptions ........................... 12 Terminology .................................................................................... 13 Typical Performance Characteristics ........................................... 14 Functional Description .................................................................. 17 Overall .......................................................................................... 17 CLK, CLKB—Differential Clock Input ................................... 17 Synchronization .......................................................................... 17 Power-On SYNC .................................................................... 17 SYNCB ..................................................................................... 17 RSET Resistor ............................................................................. 18 VREF ............................................................................................ 18 Setup Configuration................................................................... 18 Divider Phase Offset .................................................................. 20 Delay Block ................................................................................. 21 Outputs ........................................................................................ 21 Power Supply ............................................................................... 22 Exposed Metal Paddle ........................................................... 22 Power Management.................................................................... 22 Applications Information .............................................................. 23 Using the AD9513 Outputs for ADC Clock Applications .... 23 LVDS Clock Distribution .......................................................... 23 CMOS Clock Distribution ........................................................ 23 Setup Pins (S0 to S10) ................................................................ 24 Power and Grounding Considerations and Power Supply Rejection ...................................................................................... 24 Phase Noise and Jitter Measurement Setups........................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26 REVISION HISTORY 10/2017—Rev. A to Rev. B Changed CP-32-7 to CP-32-2 ...................................... Throughout Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 1/2017—Rev. 0 to Rev. A Changes to Figure 5 and Table 9 ................................................... 12 Deleted Figure 6; Renumbered Sequentially ............................... 12 Change to Table 14 ......................................................................... 19 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 9/2005—Revision 0: Initial Version

Page 4

Data Sheet AD9513 Rev. B | Page 3 of 28 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; TA = 25°C, RSET = 4.12 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. CLOCK INPUT Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUT (CLK) Input Frequency 0 1.6 GHz Input Sensitivity1 150 mV p-p Input Common-Mode Voltage, VCM 1.5 1.6 1.7 V Self-biased; enables ac coupling Input Common-Mode Range, VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLKB ac-bypassed to RF ground Input Resistance 4.0 4.8 5.6 kΩ Self-biased Input Capacitance 2 pF 1A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications. CLOCK OUTPUTS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments LVDS CLOCK OUTPUT Termination = 100 Ω differential Differential Output Frequency 0 800 MHz Differential Output Voltage (VOD) 250 350 450 mV Delta VOD 30 mV Output Offset Voltage (VOS) 1.125 1.23 1.375 V Delta VOS 25 mV Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND CMOS CLOCK OUTPUT Single-ended measurements; termination open Single-Ended Complementary output on (OUT1B) Output Frequency 0 250 MHz With 5 pF load Output Voltage High (VOH) VS − 0.1 V @ 1 mA load Output Voltage Low (VOL) 0.1 V @ 1 mA load

Page 5

AD9513 Data Sheet Rev. B | Page 4 of 28 TIMING CHARACTERISTICS CLK input slew rate = 1 V/ns or greater. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments LVDS Termination = 100 Ω differential Output Rise Time, tRL 200 350 ps 20% to 80%, measured differentially Output Fall Time, tFL 210 350 ps 80% to 20%, measured differentially PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT Delay off on OUT2 OUT0, OUT1, OUT2 Divide = 1 1.03 1.29 1.62 ns Divide = 2 − 32 1.09 1.35 1.68 ns Variation with Temperature 0.9 ps/°C OUT2 Divide = 1 1.07 1.35 1.69 ns Divide = 2 − 32 1.13 1.41 1.75 ns Variation with Temperature 0.9 ps/°C OUTPUT SKEW, LVDS OUTPUTS Delay off on OUT2 OUT0 to OUT1 on Same Part, tSKV 1 −135 −20 +125 ps OUT0 to OUT2 on Same Part, tSKV1 −205 −65 +90 ps All LVDS OUTs Across Multiple Parts, tSKV_AB 2 375 ps Same LVDS OUTs Across Multiple Parts, tSKV_AB2 300 ps CMOS B outputs are inverted; termination = open Output Rise Time, tRC 650 865 ps 20% to 80%; CLOAD = 3 pF Output Fall Time, tFC 650 990 ps 80% to 20%; CLOAD = 3 pF PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT Delay off on OUT2 OUT0, OUT1 Divide = 1 1.14 1.46 1.89 ns Divide = 2 − 32 1.19 1.51 1.94 ns Variation with Temperature 1 ps/°C OUT2 Divide = 1 1.20 1.53 1.97 ns Divide = 2 − 32 1.24 1.57 2.01 ns Variation with Temperature 1 ps/°C OUTPUT SKEW, CMOS OUTPUTS Delay off on OUT2 All CMOS OUTs on Same Part, tSKC1 −230 +135 ps All CMOS OUTs Across Multiple Parts, tSKC_AB2 415 ps Same CMOS OUTs Across Multiple Parts, tSKC_AB2 330 ps LVDS-TO-CMOS OUT Everything the same; different logic type Output Skew, tSKV_C 510 ps LVDS to CMOS on same part DELAY ADJUST (OUT2; LVDS AND CMOS) S0 = 1/3 Zero-Scale Delay Time3 0.35 ns Zero-Scale Variation with Temperature 0.20 ps/°C Full-Scale Time Delay3 1.8 ns Full-Scale Variation with Temperature −0.38 ps/°C S0 = 2/3 Zero-Scale Delay Time3 0.48 ns Zero-Scale Variation with Temperature 0.31 ps/°C Full-Scale Time Delay3 6.0 ns Full-Scale Variation with Temperature −1.3 ps/°C

Page 6

Data Sheet AD9513 Rev. B | Page 5 of 28 Parameter Min Typ Max Unit Test Conditions/Comments S0 = 1 Zero-Scale Delay Time3 0.59 ns Zero-Scale Variation with Temperature 0.47 ps/°C Full-Scale Time Delay3 11.6 ns Full-Scale Variation with Temperature −5 ps/°C Linearity, DNL 0.2 LSB Linearity, INL 0.2 LSB 1 This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. 2 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. 3 Incremental delay; does not include propagation delay.

Page 7

AD9513 Data Sheet Rev. B | Page 6 of 28 CLOCK OUTPUT PHASE NOISE Table 4. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 At 10 Hz Offset −100 dBc/Hz At 100 Hz Offset −110 dBc/Hz At 1 kHz Offset −118 dBc/Hz At 10 kHz Offset −129 dBc/Hz At 100 kHz Offset −135 dBc/Hz At 1 MHz Offset −140 dBc/Hz >10 MHz Offset −148 dBc/Hz CLK = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 At 10 Hz Offset −112 dBc/Hz At 100 Hz Offset −122 dBc/Hz At 1 kHz Offset −132 dBc/Hz At 10 kHz Offset −142 dBc/Hz At 100 kHz Offset −148 dBc/Hz At 1 MHz Offset −152 dBc/Hz >10 MHz Offset −155 dBc/Hz CLK = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 At 10 Hz Offset −108 dBc/Hz At 100 Hz Offset −118 dBc/Hz At 1 kHz Offset −128 dBc/Hz At 10 kHz Offset −138 dBc/Hz At 100 kHz Offset −145 dBc/Hz At 1 MHz Offset −148 dBc/Hz >10 MHz Offset −154 dBc/Hz CLK = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 At 10 Hz Offset −118 dBc/Hz At 100 Hz Offset −129 dBc/Hz At 1 kHz Offset −136 dBc/Hz At 10 kHz Offset −147 dBc/Hz At 100 kHz Offset −153 dBc/Hz At 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz CLK = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 At 10 Hz Offset −108 dBc/Hz At 100 Hz Offset −118 dBc/Hz At 1 kHz Offset −128 dBc/Hz At 10 kHz Offset −138 dBc/Hz At 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −155 dBc/Hz

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Data Sheet AD9513 Rev. B | Page 7 of 28 Parameter Min Typ Max Unit Test Conditions/Comments CLK = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 At 10 Hz Offset −118 dBc/Hz At 100 Hz Offset −127 dBc/Hz At 1 kHz Offset −137 dBc/Hz At 10 kHz Offset −147 dBc/Hz At 100 kHz Offset −154 dBc/Hz At 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz CLK-TO-CMOS ADDITIVE PHASE NOISE CLK = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 At 10 Hz Offset −110 dBc/Hz At 100 Hz Offset −121 dBc/Hz At 1 kHz Offset −130 dBc/Hz At 10 kHz Offset −140 dBc/Hz At 100 kHz Offset −145 dBc/Hz At 1 MHz Offset −149 dBc/Hz >10 MHz Offset −156 dBc/Hz CLK = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 At 10 Hz Offset −125 dBc/Hz At 100 Hz Offset −132 dBc/Hz At 1 kHz Offset −143 dBc/Hz At 10 kHz Offset −152 dBc/Hz At 100 kHz Offset −158 dBc/Hz At 1 MHz Offset −160 dBc/Hz >10 MHz Offset −162 dBc/Hz CLK = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1 At 10 Hz Offset −122 dBc/Hz At 100 Hz Offset −132 dBc/Hz At 1 kHz Offset −140 dBc/Hz At 10 kHz Offset −150 dBc/Hz At 100 kHz Offset −155 dBc/Hz At 1 MHz Offset −158 dBc/Hz >10 MHz Offset −160 dBc/Hz CLK = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2 At 10 Hz Offset −128 dBc/Hz At 100 Hz Offset −136 dBc/Hz At 1 kHz Offset −146 dBc/Hz At 10 kHz Offset −155 dBc/Hz At 100 kHz Offset −161 dBc/Hz >1 MHz Offset −162 dBc/Hz

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AD9513 Data Sheet Rev. B | Page 8 of 28 CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT ADDITIVE TIME JITTER Calculated from SNR of ADC method CLK= 400 MHz 300 fs rms LVDS (OUT0) = 100 MHz Divide Ratio = 4 LVDS (OUT1, OUT2) = 100 MHz Interferer CLK = 400 MHz 300 fs rms LVDS (OUT0) = 100 MHz Divide Ratio = 4 LVDS (OUT1, OUT2) = 50 MHz Interferer CLK = 400 MHz 305 fs rms LVDS (OUT1) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT2) = 100 MHz Interferer CLK = 400 MHz 310 fs rms LVDS (OUT1) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT2) = 50 MHz Interferer CLK = 400 MHz 310 fs rms LVDS (OUT2) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT1) = 100 MHz Interferer CLK = 400 MHz 315 fs rms LVDS (OUT2) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT1) = 50 MHz Interferer CLK = 400 MHz 345 fs rms LVDS (OUT2) = 100 MHz Divide Ratio = 4 CMOS (OUT0, OUT1) = 50 MHz Interferer CMOS OUTPUT ADDITIVE TIME JITTER Calculated from SNR of ADC method CLK = 400 MHz 300 fs rms CMOS (OUT0) = 100 MHz Divide Ratio = 4 LVDS (OUT2) = 100 MHz Interferer CLK = 400 MHz 300 fs rms CMOS (OUT0) = 100 MHz Divide Ratio = 4 CMOS (OUT1, OUT2) = 50 MHz Interferer CLK = 400 MHz 335 fs rms CMOS (OUT1) = 100 MHz Divide Ratio = 4 CMOS (OUT0, OUT2) = 50 MHz Interferer CLK = 400 MHz 355 fs rms CMOS (OUT2) = 100 MHz Divide Ratio = 4 CMOS (OUT0, OUT1) = 50 MHz Interferer CLK = 400 MHz 340 fs rms CMOS (OUT2) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT1) = 50 MHz Interferer

Page 10

Data Sheet AD9513 Rev. B | Page 9 of 28 Parameter Min Typ Max Unit Test Conditions/Comments DELAY BLOCK ADDITIVE TIME JITTER1 100 MHz output; incremental additive jitter1 Delay FS = 1.8 ns Fine Adj. 00000 0.71 ps rms Delay FS = 1.8 ns Fine Adj. 11111 1.2 ps rms Delay FS = 6.0 ns Fine Adj. 00000 1.3 ps rms Delay FS = 6.0 ns Fine Adj. 11111 2.7 ps rms Delay FS = 11.6 ns Fine Adj. 00000 2.0 ps rms Delay FS = 11.6 ns Fine Adj. 11111 2.8 ps rms 1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method. SYNCB, VREF, AND SETUP PINS Table 6. Parameter Min Typ Max Unit Test Conditions/Comments SYNCB Logic High 2.7 V Logic Low 0.40 V Capacitance 2 pF VREF Output Voltage 0.62·VS 0.76·VS V Minimum − maximum from 0 mA to 1 mA load S0 TO S10 Levels 0 0.1·VS V 1/3 0.2·VS 0.45·VS V 2/3 0.55·VS 0.8·VS V 1 0.9·VS V POWER Table 7. Parameter Min Typ Max Unit Test Conditions/Comments POWER-ON SYNCHRONIZATION1 35 ms See the Power-On SYNC section. VS Transit Time from 2.2 V to 3.1 V POWER DISSIPATION 175 325 575 mW All three outputs on. LVDS (divide = 2). No clock. Does not include power dissipated in external resistors. 240 460 615 mW All three outputs on. CMOS (divide = 2); 62.5 MHz out (5 pF load). 320 605 840 mW All three outputs on. CMOS (divide = 2); 125 MHz out (5 pF load). POWER DELTA Divider (Divide = 2 to Divide = 1) 15 30 45 mW For each divider. No clock. LVDS Output 20 50 85 mW No clock. CMOS Output (Static) 30 40 50 mW No clock. CMOS Output (@ 62.5 MHz) 65 110 155 mW Single-ended. At 62.5 MHz out with 5 pF load. CMOS Output (@ 125 MHz) 70 145 220 mW Single-ended. At 125 MHz out with 5 pF load. Delay Block 30 45 65 mW Off to 1.8 ns fs, delay word = 60; output clocking at 62.5 MHz. 1 This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs are not synchronized.

AD9513BCPZ Reviews

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Gerar*****ymond

November 22, 2019

These are the most popular variety of components of different types!

Paul *****maniam

November 7, 2019

Didn’t need so many but it was cheap. I did have to solder extra wire on each end to make fit better but exactly you need of your looking for this particular mod.

Romi*****ilva

September 25, 2019

fast delivery and good product, very happy

Averi*****eland

June 24, 2019

Purchasing from Heisener means the real part is obtained no worried for product quality.

Eth*****Pai

May 9, 2019

Went well this time Now have the IC and very pleased.

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May 2, 2019

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Joh***** Lad

April 29, 2019

Great Seller, Great Item, the quality is great, Highly Recommended.

Summ*****amesh

April 1, 2019

Great capacitors. very fast post very good communication.

Land*****llen

March 19, 2019

Received Quickly. Excellent Communication. Capacitors Look Excellent

Heze***** Khare

January 24, 2019

Excellent website experience for search any product I want, problem solvers. You guys I can trust and reply on.

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