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AD976BN

hot AD976BN

AD976BN

For Reference Only

Part Number AD976BN
Manufacturer Analog Devices Inc.
Description IC ADC 16BIT 100KSPS 28-DIP
Datasheet AD976BN Datasheet
Package 28-DIP (0.600", 15.24mm)
In Stock 244 piece(s)
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AD976BN Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD976BN Datasheet
Package28-DIP (0.600", 15.24mm)
Series-
Number of Bits16
Sampling Rate (Per Second)100k
Number of Inputs1
Input TypeSingle Ended
Data InterfaceParallel
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeExternal, Internal
Voltage - Supply, Analog5V
Voltage - Supply, Digital5V
Operating Temperature-40°C ~ 85°C
Package / Case28-DIP (0.600", 15.24mm)
Supplier Device Package28-PDIP

AD976BN Datasheet

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REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD976/AD976A One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters FUNCTIONAL BLOCK DIAGRAM REF VANA 4kV R D15 D0 DGND BYTE R/C CS BUSY VDIG VIN AGND2 CAP AGND1 2.5V REFERENCE 4R CONTROL LOGIC & INTERNAL CALIBRATION CIRCUITRY CLOCK PARALLEL INTERFACE SWITCHED CAP ADC AD976/AD976A 4R 3 R = 6kV AD976 R = 3kV AD976A FEATURES Fast 16-Bit ADC 200 kSPS Throughput – AD976A 100 kSPS Throughput – AD976 Single 5 V Supply Operation Input Range: 610 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages GENERAL DESCRIPTION The AD976/AD976A is a high speed, low power 16-bit A/D converter that operates from a single 5 V supply. The part con- tains a successive approximation, switched capacitor ADC, an internal 2.5 V reference and a high speed parallel interface. The ADC is factory calibrated to minimize all linearity errors. The analog full-scale input is the standard industrial range of ±10 V. The AD976/AD976A is comprehensively tested for ac param- eters such as SNR and THD, as well as the more traditional parameters of offset, gain and linearity. The AD976/AD976A is fabricated on Analog Devices’ propri- etary BiCMOS process, which has high performance bipolar devices along with CMOS transistors. The AD976/AD976A is available in skinny 28-lead DIP, SSOP and SOIC packages. PRODUCT HIGHLIGHTS 1. Fast Throughput. The AD976/AD976A is a high speed (100 kSPS/200 kSPS throughput rates respectively), 16-bit ADC based on a switched capacitor architecture. 2. Single-Supply Operation. The AD976/AD976A operates from a single 5 V supply and dissipates only 100 mW max. 3. Comprehensive DC and AC Specifications. The AD976/AD976A is factory calibrated and fully tested for SNR and THD as well as the traditional specifications of offset, gain and linearity. 4. Complete A/D Solution. The AD976/AD976A offers a highly integrated solution containing an accurate ADC, reference and on-chip clock.

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AD976/AD976A –2– REV. C AD976A–SPECIFICATIONS AD976AA AD976AB AD976AC Parameter Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 16 16 16 Bits ANALOG INPUT Voltage Range ± 10 ± 10 ± 10 V Impedance 13 13 13 kΩ Capacitance 22 22 22 pF THROUGHPUT SPEED Complete Cycle 5 5 5 µs Throughput Rate 200 200 200 kHz DC ACCURACY Integral Linearity Error ± 3 ± 2 ± 3 LSB1 Differential Linearity Error –2 +3 –1 +1.75 ± 2 LSB No Missing Codes 15 16 15 Bit Transition Noise2 1.0 1.0 1.0 LSB Full-Scale Error3, 4 ± 0.5 ± 0.25 ± 0.5 % Full-Scale Error Drift ± 7 ± 7 ± 7 ppm/°C Full-Scale Error, Ext. REF = 2.5 V ± 0.5 ± 0.25 ± 0.5 % Full-Scale Error Drift, Ext. REF = 2.5 V ± 2 ± 2 ± 2 ppm/°C Bipolar Zero Error4 ± 10 ± 10 ± 15 mV Bipolar Zero Error Drift ± 2 ± 2 ± 2 ppm/°C Power Supply Sensitivity VANA = VDIG = VD = 5 V ± 5% ± 8 ± 8 ± 8 LSB AC ACCURACY Spurious Free Dynamic Range5 90 96 90 dB6 Total Harmonic Distortion5 –90 –96 –90 dB Signal to (Noise + Distortion)5 83 85 83 dB –60 dB Input 27 28 27 dB Signal to Noise5 83 85 83 dB Full-Power Bandwidth7 1 1 1 MHz Input Bandwidth 2.7 2.7 2.7 MHz SAMPLING DYNAMICS Aperture Delay 40 40 40 ns Transient Response Full-Scale Step 1 1 1 µs Overvoltage Recovery8 150 150 150 ns REFERENCE Internal Reference Voltage 2.48 2.5 2.52 2.48 2.5 2.52 2.48 2.5 2.52 V Internal Reference Source Current 1 1 1 µA External Reference Voltage Range for Specified Linearity 2.3 2.5 2.7 2.3 2.5 2.7 2.3 2.5 2.7 V External Reference Current Drain Ext. REF = 2.5 V 100 100 100 µA DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 –0.3 +0.8 –0.3 +0.8 V VIH +2.0 VDIG + 0.3 +2.0 VDIG + 0.3 +2.0 VDIG + 0.3 V IIL ± 10 ± 10 ± 10 µA IIH ± 10 ± 10 ± 10 µA NOTES 1LSB means least significant bit. With a ± 10 V input, one LSB is 305 µV. 2Typical rms noise at worst case transitions and temperatures. 3Measured with fixed resistors as shown in Figure 5 (AD976) and Figure 6 (AD976A). Adjustable to zero as shown in Figure 7. 4Full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage and includes the effect of offset error. The full-scale error is the worst case of either the –full-scale or +full-scale code transition voltage errors. 5fIN = 20 kHz (AD976) and fIN = 45 kHz (AD976A), 0.5 dB down, unless otherwise noted. 6All specifications in dB are referred to a full scale ±10 V input. 7Full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of accuracy. 8Recovers to specified performance after a 2 × FS input overvoltage. Specifications subject to change without notice. (–408C to +858C, FS = 200 kHz, Ref = Internal Reference, VDIG = VANA = +5 V unless otherwise noted)

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–3–REV. C AD976/AD976A AD976–SPECIFICATIONS AD976A AD976B AD976C Parameter Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 16 16 16 Bits ANALOG INPUT Voltage Range ± 10 ± 10 ± 10 V Impedance 23 23 23 kΩ Capacitance 22 22 22 pF THROUGHPUT SPEED Complete Cycle 10 10 10 µs Throughput Rate 100 100 100 kHz DC ACCURACY Integral Linearity Error ± 3 ± 2 ± 3 LSB1 Differential Linearity Error –2 +3 –1 +1.75 ± 2 LSB No Missing Codes 15 16 15 Bit Transition Noise2 1.0 1.0 1.0 LSB Full-Scale Error3, 4 ± 0.5 ± 0.25 ± 0.5 % Full-Scale Error Drift ± 7 ± 7 ± 7 ppm/°C Full-Scale Error, Ext. REF = 2.5 V ± 0.5 ± 0.25 ± 0.5 % Full-Scale Error Drift, Ext. REF = 2.5 V ± 2 ± 2 ± 2 ppm/°C Bipolar Zero Error4 ± 10 ± 10 ± 15 mV Bipolar Zero Error Drift ± 2 ± 2 ± 2 ppm/°C Power Supply Sensitivity VANA = VDIG = VD = 5 V ± 5% ± 8 ± 8 ± 8 LSB AC ACCURACY Spurious Free Dynamic Range5 90 96 90 dB6 Total Harmonic Distortion5 –90 –96 –90 dB Signal to (Noise + Distortion)5 83 85 83 dB –60 dB Input 27 28 27 dB Signal to Noise5 83 85 83 dB Full-Power Bandwidth7 700 700 700 kHz Input Bandwidth 1.5 1.5 1.5 MHz SAMPLING DYNAMICS Aperture Delay 40 40 40 ns Transient Response Full-Scale Step 2 2 2 µs Overvoltage Recovery8 150 150 150 ns REFERENCE Internal Reference Voltage 2.48 2.5 2.52 2.48 2.5 2.52 2.48 2.5 2.52 V Internal Reference Source Current 1 1 1 µA External Reference Voltage Range for Specified Linearity 2.3 2.5 2.7 2.3 2.5 2.7 2.3 2.5 2.7 V External Reference Current Drain Ext. REF = 2.5 V 100 100 100 µA DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 –0.3 +0.8 –0.3 +0.8 V VIH +2.0 VDIG + 0.3 +2.0 VDIG + 0.3 +2.0 VDIG + 0.3 V IIL ± 10 ± 10 ± 10 µA IIH ± 10 ± 10 ± 10 µA NOTES 1LSB means least significant bit. With a ± 10 V input, one LSB is 305 µV. 2Typical rms noise at worst case transitions and temperatures. 3Measured with fixed resistors as shown in Figure 5 (AD976) and Figure 6 (AD976A). Adjustable to zero as shown in Figure 7. 4Full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage and includes the effect of offset error. The full-scale error is the worst case of either the –full-scale or +full-scale code transition voltage errors. 5fIN = 20 kHz (AD976) and fIN = 45 kHz (AD976A), 0.5 dB down, unless otherwise noted. 6All specifications in dB are referred to a full scale ± 10 V input. 7Full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of accuracy. 8Recovers to specified performance after a 2 × FS input overvoltage. Specifications subject to change without notice. (–408C to +858C, FS = 100 kHz, Ref = Internal Reference, VDIG = VANA = +5 V unless otherwise noted)

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AD976/AD976A –4– REV. C All Grades Parameter Conditions Min Typ Max Units DIGITAL OUTPUTS Data Format Parallel 16 Bits Data Coding Binary Twos Complement VOL ISINK = 1.6 mA +0.4 V VOH ISOURCE = 500 µA +4 V Leakage Current High-Z State, ±5 µA VOUT = 0 V to VDIG Output Capacitance High-Z State 15 pF DIGITAL TIMING Bus Access Time 83 ns Bus Relinquish Time 83 ns POWER SUPPLIES Specified Performance VDIG 4.75 5 5.25 V VANA 4.75 5 5.25 V IDIG 3.0 mA IANA 11 mA Power Dissipation 100 mW TEMPERATURE RANGE Specified Performance –40 +85 °C Specifications subject to change without notice. TIMING SPECIFICATIONS (AD976A: FS = 200 kHz; AD976: FS = 100 kHz; –408C to +858C, VDIG = VANA = +5 V unless otherwise noted) Symbol Min Typ Max Units Convert Pulsewidth t1 50 ns Data Valid Delay after R/C Low (AD976A/AD976) t2 4.0/8.0 µs BUSY Delay from R/C Low t3 83 ns BUSY Low (AD976A/AD976) t4 4.0/8.0 µs BUSY Delay after End of Conversion (AD976A/AD976) t5 180/360 ns Aperture Delay t6 40 ns Conversion Time (AD976A/AD976) t7 3.8/7.6 4.0/8.0 µs Acquisition Time t8 1.0/2.0 µs Bus Relinquish Time t9 10 35 83 ns BUSY Delay after Data Valid (AD976A/AD976) t10 50 180/360 ns Previous Data Valid after R/C Low (AD976A/AD976) t11 3.7/7.4 µs Throughput Time (AD976A/AD976) t7 + t8 5/10 µs R/C to CS Setup Time t12 10 ns Time Between Conversions (AD976A/AD976) t13 5/10 µs Bus Access and Byte Delay t14 10 83 ns Specifications subject to change without notice.

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AD976/AD976A –5–REV. C ABSOLUTE MAXIMUM RATINGS1 Analog Inputs VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V CAP . . . . . . . . . . . . . . . . +VANA + 0.3 V to AGND2 – 0.3 V REF . . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2 Ground Voltage Differences DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . . ±0.3 V Supply Voltages VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VDIG to VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V VDIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital Inputs . . . . . . . . . . . . . . . . . . . –0.3 V to VDIG + 0.3 V Internal Power Dissipation2 PDIP (N), SOIC (R), SSOP (RS) . . . . . . . . . . . . . 700 mW Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature Range (N, R, RS) . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air: 28-Lead PDIP: θJA = 74°C/W; θJC = 24°C/W, 28-Lead SOIC: θJA = 72°C/W; θJC = 23°C/W, 28-Lead SSOP: θJA = 109°C/W; θJC = 39°C/W. ORDERING GUIDE Temperature Max Min Throughput Package Package Model Range INL S/(N+D) Rate Descriptions Options AD976AN –40°C to +85°C ±3.0 LSB 83 dB 100 kSPS 28-Lead, 300 mil Plastic DIP N-28B AD976BN –40°C to +85°C ±2.0 LSB 85 dB 100 kSPS 28-Lead, 300 mil Plastic DIP N-28B AD976CN –40°C to +85°C 83 dB 100 kSPS 28-Lead, 300 mil Plastic DIP N-28B AD976AAN –40°C to +85°C ±3.0 LSB 83 dB 200 kSPS 28-Lead, 300 mil Plastic DIP N-28B AD976ABN –40°C to +85°C ±2.0 LSB 85 dB 200 kSPS 28-Lead, 300 mil Plastic DIP N-28B AD976ACN –40°C to +85°C 83 dB 200 kSPS 28-Lead, 300 mil Plastic DIP N-28B AD976AR –40°C to +85°C ±3.0 LSB 83 dB 100 kSPS 28-Lead Small Outline Package R-28 AD976BR –40°C to +85°C ±2.0 LSB 85 dB 100 kSPS 28-Lead Small Outline Package R-28 AD976CR –40°C to +85°C 83 dB 100 kSPS 28-Lead Small Outline Package R-28 AD976AAR –40°C to +85°C ±3.0 LSB 83 dB 200 kSPS 28-Lead Small Outline Package R-28 AD976ABR –40°C to +85°C ±2.0 LSB 85 dB 200 kSPS 28-Lead Small Outline Package R-28 AD976ACR –40°C to +85°C 83 dB 200 kSPS 28-Lead Small Outline Package R-28 AD976ARS –40°C to +85°C ±3.0 LSB 83 dB 100 kSPS 28-Lead Shrink Small Outline Package RS-28 AD976BRS –40°C to +85°C ±2.0 LSB 85 dB 100 kSPS 28-Lead Shrink Small Outline Package RS-28 AD976CRS –40°C to +85°C 83 dB 100 kSPS 28-Lead Shrink Small Outline Package RS-28 AD976AARS –40°C to +85°C ±3.0 LSB 83 dB 200 kSPS 28-Lead Shrink Small Outline Package RS-28 AD976ABRS –40°C to +85°C ±2.0 LSB 85 dB 200 kSPS 28-Lead Shrink Small Outline Package RS-28 AD976ACRS –40°C to +85°C 83 dB 200 kSPS 28-Lead Shrink Small Outline Package RS-28 PIN CONFIGURATION DIP, SOIC and SSOP Packages 14 13 12 11 10 9 8 2 3 4 7 6 5 1 TOP VIEW (Not to Scale) 17 16 15 19 18 20 28 27 26 25 24 23 22 21 AD976 AD976A VIN CS BUSY VANA VDIG AGND1 REF CAP D0 (LSB) BYTE R/CAGND2 D15 (MSB) D14 D13 D12 D11 D3 D2 D1 D10 D9 D8 DGND D4 D7 D6 D5 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD976/AD976A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 1.6mA IOL TO OUTPUT PIN CL 100pF 500mA IOH +2.1V Figure 1. Load Circuit for Digital Interface Timing WARNING! ESD SENSITIVE DEVICE

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AD976/AD976A –6– REV. C PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 VIN Analog Input. Connect a 200 Ω resistor between VIN and the analog signal source. The full-scale input range is ±10 V. 2 AGND1 Analog Ground. Used as the ground reference point for the REF pin. 3 REF Reference Input/Output. The internal +2.5 V reference is available at this pin. Alternatively, an external reference can be used to override the internal reference. In either case, connect a 2.2 µF tantalum capacitor between REF and AGND1. 4 CAP Reference Buffer Output. Connect a 2.2 µF tantalum capacitor between CAP and AGND2. 5 AGND2 Analog Ground. 6 D15 (MSB) Data Bit 15. Most significant bit of conversion result. High impedance state when CS is HIGH or when R/C is LOW. 7–13 D14–D8 Data Bits 14–8. High impedance state when CS is HIGH or when R/C is LOW. 14 DGND Digital Ground. 15–21 D7–D1 Data Bits 7–1. High impedance state when CS is HIGH or when R/C is LOW. 22 D0 (LSB) Data Bit 0. Least significant bit of conversion result. High impedance state when CS is HIGH or when R/C is LOW. 23 BYTE Byte Select. With BYTE LOW, data will be output as indicated above; Pin 6 (D15) is the MSB, Pin 22 (D0) is the LSB. With BYTE HIGH, the top and bottom 8 bits of data will be switched; D15–D8 are output on Pins 15–22 and D7–D0 are output on Pins 6–13. 24 R/C Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion; a rising edge enables the output data bits. 25 CS Chip Select Input. Internally OR’d with R/C. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH, a falling edge on CS will enable the output data bits. When CS is HIGH, the output data bits will be in the Hi-impedance state. 26 BUSY Busy Output. Goes LOW when a conversion is started and remains LOW until the conversion is completed and the data is latched into the output register. With CS tied LOW and R/C HIGH, output data will be valid when BUSY rises. The rising edge of BUSY can be used to latch the out- put data. 27 VANA Analog Power Supply. Nominally +5 V. 28 VDIG Digital Power Supply. Nominally +5 V. DEFINITION OF SPECIFICATIONS INTEGRAL NONLINEARITY ERROR (INL) Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” to “positive full scale.” The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. DIFFERENTIAL NONLINEARITY ERROR (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. 6 FULL-SCALE ERROR The last + transition (from 011. . .10 to 011. . .11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (9.9995422 V for a ±10 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level. BIPOLAR ZERO ERROR Bipolar zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. INPUT BANDWIDTH The input bandwidth is that frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full- scale input. FULL-POWER BANDWIDTH Full-power bandwidth is defined as the full-scale input fre- quency at which signal to (Noise + Distortion) degrades to 60 dB, as 10 bits of accuracy. APERTURE DELAY Aperture delay is a measure of the Sample-and-Hold Amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for a conversion.

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AD976/AD976A –7–REV. C APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. TRANSIENT RESPONSE The time required for the AD976/AD976A to achieve its rated accuracy after a full-scale step function is applied to its input. OVERVOLTAGE RECOVERY The time required for the ADC to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value. Signal-to-(Noise Plus Distortion Ratio) (S/[N+D]) S/(N+D) is the measured signal-to-noise plus distortion ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise plus distortion is the rms sum of all of the nonfundamental signals and harmonics to half the sampling rate excluding dc. The S/(N+D) is dependent upon the number of quantization levels. The more levels, the lower the quantization noise. The theoretical S/(N+D) for a sine wave input signal can be calculated using the following: S/(N+D) = (6.02N + 1.76) dB (1) where N is the number of bits. Thus, for an ideal 16 bit converter, S/(N+D) = 98 dB. The output spectrum from the ADC is evaluated by applying a low noise, low distortion sine wave signal to the VIN pin and sampling at a 200 kHz throughput rate. By generating a Fast Fourier Transform (FFT) plot, the S/(N+D) data can then be obtained. Figure 10 shows a typical 2048-point FFT plot with an input signal of 45 kHz and a sampling rate of 200 kHz. The S/(N+D) obtained from this graph is 86.23 dB. Since the measured S/(N+D) is less than the theoretical value, it is possible to get a measure of performance expressed in effective number of bits (ENOB). ENOB = ((S/(N+D) – 1.76) / 6.02) Thus for an input signal of 45 kHz, the typical ENOB is 14. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the harmonics to the rms value of the fundamental. For the AD976/AD976A, THD is defined as: THD dB V V V V V V ( ) = + + + +20 2 2 3 2 4 2 5 2 6 2 1 log where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through sixth harmonics. The THD is also derived from the FFT plot of the ADC output spectrum shown in Figure 10 and is seen there as –105.33 dB. Spurious Free Dynamic Range (SPFD) The spurious free dynamic range is defined as the difference, in dB, between the peak spurious or harmonic component in the ADC output spectrum (up to FS/2 and excluding dc) and the rms value of the fundamental. Normally, the value of this specification will be determined by the largest harmonic in the spectrum. The typical SPFD for the AD976/AD976A is –100 dB and can be seen in Figure 10. FUNCTIONAL DESCRIPTION The AD976/AD976A is a high speed, low power, 16-bit sam- pling, analog-to-digital converter that can operate from a single +5 volt power supply. The AD976/AD976A uses laser trimmed scaling input resistors to provide an industry standard ±10 volt input range. With a 100/200 kSPS throughput rate and a paral- lel interface, the AD976/AD976A is capable of connecting di- rectly to digital signal processors and microcontrollers. The AD976/AD976A employs a successive-approximation technique to determine the value of the analog input voltage. Instead of using the traditional laser-trimmed resistor-ladder approach, however, this device uses a capacitor array charge distribution technique. Binary weighted capacitors subdivide the input sample to perform the actual analog-to-digital conversion. The capacitor array eliminates variation in the linearity of the device due to temperature-induced mismatches of resistor val- ues. As a result of having an on-chip capacitor array, there is no need for additional external circuitry to perform the sample/hold function. Initial errors in capacitor matching are eliminated at the time of manufacturing. Calibration coefficients are calculated that cor- rect for capacitor mismatches and are stored in on-chip thin-film resistors that act as ROM. As a conversion is occurring, the appro- priate calibration coefficients are read out of ROM. The accumu- lated coefficients are then used to adjust and improve conversion accuracy. Any initial offset error is also trimmed out during factory calibration. With the addition of an onboard reference the AD976/AD976A provides a complete 16-bit A/D solution.

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AD976/AD976A –8– REV. C DATA VALID t6 t3 t1 t10t9 CONVERT CONVERTACQUIREMODE DATA BUS NOT VALID HI-Z DATA VALID BUSY R/C t7 t8 t11 t13 ACQUIRE t2 t4 PREVIOUS DATA VALID t5 PREVIOUS DATA VALID t14 HI-Z Figure 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low) MODE BUSY R/C DATA BUS CS t6 t12 t1 CONVERT ACQUIRE HI-Z DATA VALID t7 ACQUIRE t9 t12 t12 t12 t1 t3 t4 t14 HI-Z Figure 3. Using CS to Control Conversion and Read Timing CONVERSION CONTROL The AD976/AD976A is controlled by two signals: R/C and CS, as shown in Figures 2 and 3. To initiate a conversion and place the sample/hold circuit into the hold state, both the R/C and CS signals must be brought low for no less than 50 ns. Once the conversion process begins, the BUSY signal will go Low until the conversion is complete. At the end of a conversion, BUSY will return High, and the resulting valid data will be available on the data bus. On the first conversion after the AD976/AD976A is powered up, the DATA output will be indeterminate. The AD976/AD976A exhibits two modes of conversion. In the mode demonstrated in Figure 2, conversion timing is controlled by a negative-going R/C signal, at least 50 ns wide. In this mode the CS pin is always tied low, and the only limit placed on how long the R/C signal can remain low is the desired sampling rate. Less than 83 ns after the initiation of a conversion, the BUSY signal will be brought low and remain low until the conversion is complete and the output shift registers have been updated with the new Binary Twos Complement data. Figure 3 demonstrates the AD976/AD976A conversion timing, using CS to control both the conversion process and the reading of output data. To operate in this mode, the R/C signal should be brought low no less than 10 ns before the falling edge of a CS pulse (50 ns wide) is applied to the ADC. Once these two pulses are applied, BUSY will go low and remain low until a conver- sion is complete. After a maximum of 4 µs (AD976A only), BUSY will again return high, and parallel data will be valid on the ADC outputs. To achieve the maximum 100 kHz/200 kHz throughput rate of the part, the negative going R/C and CS control signals should be applied every 5 µs (AD976A). It should also be noted that although all R/C and CS commands will be ignored once a conversion has begun, these inputs can be asserted during a conversion; i.e., a read during conversion can be performed. Voltage transients on these inputs could feed through to the analog circuitry and affect conversion results.

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AD976/AD976A –9–REV. C R/C CS BYTE PINS 6–13 PINS 15–22 HI-Z HIGH BYTE LOW BYTE HI-Z HI-Z HIGH BYTELOW BYTE HI-Z t14 t12 t12 t14 t9 Figure 4. Using CS and BYTE to Control Data Bus Read Timing Regardless of the method for controlling conversions, output data from conversion “n–1” will be valid during the BUSY Low time for roughly 3.7 µs (AD976A only), and output data from conversion “n” will be valid at the end of a conversion, 50 ns (t10) before BUSY returns High. It is recommended, however, that data is read only after BUSY goes high since this timing is much more clearly defined and provides optimal performance. Figure 4 demonstrates the functionality of the BYTE pin and shows how the data will be valid in Binary Twos Complement format only when R/C is asserted High and CS is Low. The BYTE pin enables the output data on the bus to be read as a full parallel output or as two 8-bit bytes on Pins 6–13 and Pins 15–22. ANALOG INPUTS Figure 5 shows the analog input section for the AD976 when operating with an internal reference. The analog input range is nominally a bipolar –10 V to +10 V. Since the AD976/AD976A can be operated with an internal or external reference, the full- scale analog input range can be best represented as ±4 VREF. The nominal input impedance is 23 kΩ /13 kΩ with a 22 pF input capacitance. The analog input section also has a ±25 V overvoltage protection. Since the AD976/AD976A has two analog grounds it is important to ensure that the analog input is referenced to the AGND1 pin, the low current ground. This will minimize any problems associated with a resistive ground drop. It is also important to ensure that the analog input of the AD976/AD976A is driven by a low impedance source. With its primarily resistive analog input circuitry, the ADC can be driven by a wide selection of general purpose amplifiers. To best match the low distortion requirements of the AD976/ AD976A, care should be taken in the selection of the drive circuitry op amp. Figure 6 shows the analog input section for the AD976A when operating with an internal reference only. Figure 9 shows the analog input section for both the AD976 and the AD976A when operating with an external reference. VIN AGND1 REF CAP AGND2 610V INPUT R2 33.2kV C2 2.2mF AD976 R1 200V C1 2.2mF Figure 5. ±10 V Input Connection for the AD976 (Internal Reference) C1 2.2mF R2 66.4kV VANA VIN AGND1 REF CAP AGND2 610V INPUT C2 2.2mF AD976A R1 200V +5V Figure 6. ±10 V Input Connection for the AD976A (Internal Reference) Only

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