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AD9822JRSZ

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AD9822JRSZ

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Part Number AD9822JRSZ
Manufacturer Analog Devices Inc.
Description IC CCD SIGNAL PROC 14BIT 28SSOP
Datasheet AD9822JRSZ Datasheet
Package 28-SSOP (0.209", 5.30mm Width)
In Stock 46,552 piece(s)
Unit Price $ 9.3100 *
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 6 - Aug 11 (Choose Expedited Shipping)
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Part Number # AD9822JRSZ (Interface - Sensor and Detector Interfaces) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD9822JRSZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - Sensor and Detector Interfaces
Datasheet AD9822JRSZDatasheet
Package28-SSOP (0.209", 5.30mm Width)
Series-
TypeCCD Signal Processor, 14-Bit
Input TypeLogic
Output TypeLogic
Interface3-Wire Serial
Current - Supply73mA
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mount
Package / Case28-SSOP (0.209", 5.30mm Width)
Supplier Device Package28-SSOP

AD9822JRSZ Datasheet

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Complete 14-Bit CCD/CIS Signal Processor AD9822 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. FEATURES 14-bit 15 MSPS ADC No missing codes guaranteed 3-channel operation up to 15 MSPS 1-channel operation up to 12.5 MSPS Correlated double sampling 1–6× programmable gain ±350 mV programmable offset Input clamp circuitry Internal voltage reference Multiplexed byte-wide output (8 + 6 format) 3-wire serial digital interface 3 V/5 V digital I/O compatibility 28-Lead SOIC or SSOP Low power CMOS: 385 mW (typ) Power-down mode: <1 mW APPLICATIONS Flatbed document scanners Film scanners Digital color copiers Multifunction peripherals GENERAL DESCRIPTION The AD9822 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, correlated double sampler (CDS), offset DAC, and programmable gain amplifier (PGA) multiplexed to a high performance 14-bit ADC. The CDS amplifiers may be disabled for use with sensors such as contact image sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 14-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface and provide adjustment of the gain, offset, and operating mode. The AD9822 operates from a single 5 V power supply, consumes 385 mW of power typically, and is packaged in a 28-lead SOIC or SSOP. FUNCTIONAL BLOCK DIAGRAM 14 8 BAND GAP REFERENCE CONFIGURATION REGISTER MUX REGISTER 6 9 GAIN REGISTERS OFFSET REGISTERS DIGITAL CONTROL INTERFACE INPUT CLAMP BIAS AD9822 DRVDD DRVSSAVDD AVSSCAPT CAPBAVDD AVSS CML OEB DOUT ADCCLKCDSCLK2CDSCLK1 OFFSET VINB VING VINR 9-BIT DAC 00 62 3- 00 1 SCLK SLOAD SDATA 9-BIT DAC 9-BIT DAC CDS PGA PGA PGA CDS CDS 3:1 MUX 14-BIT ADC 14:8 MUX BLUE GREEN RED BLUE GREEN RED Figure 1.

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AD9822 Rev. B | Page 2 of 20 TABLE OF CONTENTS Specifications..................................................................................... 3 Analog Specifications................................................................... 3 Digital Specifications ................................................................... 4 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Functional Description .................................................................. 12 3-Channel CDS Mode................................................................ 12 3-Channel SHA Mode................................................................ 12 1-Channel CDS Mode ............................................................... 12 1-Channel SHA Mode ............................................................... 12 Internal Register Descriptions.................................................. 13 Circuit Operation ........................................................................... 15 Analog Inputs—CDS Mode ...................................................... 15 External Input Coupling Capacitors........................................ 15 Analog Inputs—SHA Mode...................................................... 16 Programmable Gain AmplifierS (PGA) .................................. 16 Applications..................................................................................... 17 Circuit and Layout Recommendations ................................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18 REVISION HISTORY 2/05—Rev. A to Rev. B Changes to Format .............................................................Universal Changes to Ordering Guide .......................................................... 18 Updated Outline Dimensions ....................................................... 18 12/99—Rev. 0 to Rev. A

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AD9822 Rev. B | Page 3 of 20 SPECIFICATIONS ANALOG SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA gain = 1, unless otherwise noted. Table 1. Parameter Min Typ Max Unit MAXIMUM CONVERSION RATE 3-Channel Mode with CDS 15 MSPS 1-Channel Mode with CDS 12.5 MSPS ACCURACY (ENTIRE SIGNAL PATH) ADC Resolution 14 Bits Integral Nonlinearity (INL) −17.0/+3.5 LSB INL @ 6 MHz −10.5/+1.5 LSB Differential Nonlinearity (DNL) −0.65/+0.75 LSB DNL @ 6 MHz −1.0 −0.6/+0.65 +1.1 LSB No Missing Codes 14 Bits No Missing Codes @ 6 MHz 14 Bits Offset Error −240 −19 +200 mV Gain Error −1.4 +3.5 +6.9 % FSR ANALOG INPUTS Input Signal Range1 2.0 V p-p Allowable Reset Transient1 1.0 V Input Limits2 AVSS − 0.3 AVDD + 0.3 V Input Capacitance 10 pF Input Bias Current 10 nA AMPLIFIERS PGA Gain at Minimum 1 V/V PGA Gain at Maximum 5.7 V/V PGA Gain Resolution2 64 Steps PGA Gain Monotonicity Guaranteed Programmable Offset at Minimum −350 mV Programmable Offset at Maximum +350 mV Programmable Offset Resolution 512 Steps Programmable Offset Monotonicity Guaranteed NOISE AND CROSSTALK Total Output Noise @ PGA Minimum 1.5 LSB rms Total Output Noise @ PGA Maximum 6.0 LSB rms Channel-to-Channel Crosstalk @ 6 MHz <1 LSB POWER SUPPLY REJECTION AVDD = 5 V ± 0.25 V 0.063 0.9 % FSR DIFFERENTIAL VREF (@ 25°C) CAPT to CAPB (2 V ADC Full-Scale Range) 0.94 1.0 1.06 V TEMPERATURE RANGE Operating 0 +70 °C Storage −65 +150 °C POWER SUPPLIES AVDD 4.75 5.0 5.25 V DRVDD 3.0 5.0 5.25 V OPERATING CURRENT AVDD 73 mA DRVDD 4 mA Power-Down Mode Current 150 µA

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AD9822 Rev. B | Page 4 of 20 Parameter Min Typ Max Unit POWER DISSIPATION 3-Channel Mode 385 450 mW 3-Channel Mode @ 6 MHz 335 410 mW 1-Channel Mode 300 mW 1-Channel Mode @ 6 MHz 250 mW 1 Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp. 1V TYP RESET TRANSIENT 4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE) 2V p-p MAX INPUT SIGNAL RANGE 00 62 3- 00 2 2 The PGA gain is approximately linear-in-dB and follows the equation: [ ] ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − + = 63 63 7.41 7.5 G Gain where G is the register value. See Figure . 15 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, CL = 10 pF, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage VIH 2.0 V Low Level Input Voltage VIL 0.8 V High Level Input Current IIH 10 µA Low Level Input Current IIL 10 µA Input Capacitance CIN 10 pF LOGIC OUTPUTS High Level Output Voltage VOH 4.5 V Low Level Output Voltage VOL 0.1 V High Level Output Current IOH 50 µA Low Level Output Current IOL 50 µA

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AD9822 Rev. B | Page 5 of 20 TIMING SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V. Table 3. Parameter Symbol Min Typ Max Unit CLOCK PARAMETERS 3-Channel Pixel Rate tPRA 67 ns 1-Channel Pixel Rate tPRB 80 ns ADCCLK Pulse Width tADCLK 30 ns CDSCLK1 Pulse Width tC1 10 ns CDSCLK2 Pulse Width tC2 10 ns CDSCLK1 Falling to CDSCLK2 Rising tC1C2 0 ns ADCCLK Falling to CDSCLK2 Rising tADC2 0 ns CDSCLK2 Rising to ADCCLK Rising tC2ADR 0 ns CDSCLK2 Falling to ADCCLK Falling tC2ADF 30 40 ns CDSCLK2 Falling to CDSCLK1 Rising tC2C1 30 40 ns ADCCLK Falling to CDSCLK1 Rising tADC1 0 ns Aperture Delay for CDS Clocks tAD 2 ns SERIAL INTERFACE Maximum SCLK Frequency fSCLK 10 MHz SLOAD to SCLK Setup Time tLS 10 ns SCLK to SLOAD Hold Time tLH 10 ns SDATA to SCLK Rising Setup Time tDS 10 ns SCLK Rising to SDATA Hold Time tDH 10 ns SCLK Falling to SDATA Valid tRDV 10 ns DATA OUTPUT Output Delay tOD 8 ns Three-State to Data Valid tDV 10 ns Output Enable High to Three-State tHZ 10 ns Latency (Pipeline Delay) 3 (Fixed) Cycles

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AD9822 Rev. B | Page 6 of 20 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter With Respect To Min Max Unit VIN, CAPT, CAPB AVSS −0.3 AVDD + 0.3 V Digital Inputs AVSS −0.3 AVDD + 0.3 V AVDD AVSS −0.5 +6.5 V DRVDD DRVSS −0.5 +6.5 V AVSS DRVSS −0.3 +0.3 V Digital Outputs DRVSS −0.3 DRVDD + 0.3 V Junction Temperature 150 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS 28-Lead 300 Mil SOIC θJA = 71.4°C/W θJC = 23°C/W 28-Lead 5.3 mm SSOP θJA = 109°C/W θJC = 39°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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AD9822 Rev. B | Page 7 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 00 62 3- 00 3 CDSCLK1 CDSCLK2 ADCCLK OEB AVDD28 AVSS27 VINR26 OFFSET25 DRVDD DRVSS (MSB) D7 VING24 CML23 VINB22 D6 CAPT21 D5 CAPB20 D4 10 AVSS19 D3 11 AVDD18 D2 12 SLOAD17 D1 13 SCLK16 (LSB) D0 14 SDATA15 1 2 3 4 5 6 7 8 9 AD9822 TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 CDSCLK1 DI CDS Reference Level Sampling Clock. 2 CDSCLK2 DI CDS Data Level Sampling Clock. 3 ADCCLK DI ADC Sampling Clock. 4 OEB DI Output Enable, Active Low. 5 DRVDD P Digital Output Driver Supply. 6 DRVSS P Digital Output Driver Ground. 7 D7 (MSB) DO Data Output MSB. ADC DB13 High Byte, ADC DB5 Low Byte. 8 D6 DO Data Output. ADC DB12 High Byte, ADC DB4 Low Byte. 9 D5 DO Data Output. ADC DB11 High Byte, ADC DB3 Low Byte. 10 D4 DO Data Output. ADC DB10 High Byte, ADC DB2 Low Byte. 11 D3 DO Data Output. ADC DB9 High Byte, ADC DB1 Low Byte. 12 D2 DO Data Output. ADC DB8 High Byte, ADC DB0 Low Byte. 13 D1 DO Data Output. ADC DB7 High Byte, Don’t Care Low Byte. 14 D0 (LSB) DO Data Output LSB. ADC DB6 High Byte, Don’t Care Low Byte. 15 SDATA DI/DO Serial Interface Data Input/Output. 16 SCLK DI Serial Interface Clock Input. 17 SLOAD DI Serial Interface Load Pulse. 18 AVDD P 5 V Analog Supply. 19 AVSS P Analog Ground. 20 CAPB AO ADC Bottom Reference Voltage Decoupling. 21 CAPT AO ADC Top Reference Voltage Decoupling. 22 VINB AI Analog Input, Blue Channel. 23 CML AO Internal Bias Level Decoupling. 24 VING AI Analog Input, Green Channel. 25 OFFSET AO Clamp Bias Level Decoupling. 26 VINR AI Analog Input, Red Channel. 27 AVSS P Analog Ground. 28 AVDD P 5 V Analog Supply. 1 Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

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AD9822 Rev. B | Page 8 of 20 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. The point used as zero scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1 ½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value; therefore, every code must have a finite width. No missing codes guaranteed to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges. Offset Error The first ADC code transition should occur at a level ½ LSB above the nominal zero-scale voltage. The offset error is the deviation of the actual first code transition level from the ideal level. Gain Error The last code transition should occur for an analog value 1 ½ LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions. Input Referred Noise The rms output noise is measured using histogram techniques. The ADC output codes’ standard deviation is calculated in LSB and converted to an equivalent voltage, using the relationship 1 LSB = 4 V/16384 = 244 mV. The noise is then referred to the input of the AD9822 by dividing by the PGA gain. Channel-to-Channel Crosstalk In an ideal 3-channel system, the signal in one channel will not influence the signal level of another channel. The channel-to- channel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. In the AD9822, one channel is grounded and the other two channels are exercised with full-scale input signals. The change in the output codes from the first channel is measured and compared with the result when all three channels are grounded. The difference is the channel-to-channel crosstalk, stated in LSB. Aperture Delay The time delay that occurs from when a sampling edge is applied to the AD9822 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low; therefore, the aperture delay is measured from each clock’s falling edge to the instant the actual internal sample is taken. Power Supply Rejection It specifies the maximum full-scale change that occurs from the initial value when the supplies are varied over the specified limits.

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AD9822 Rev. B | Page 9 of 20 PIXEL N (R, G, B) PIXEL (N + 1) tAD tC2 tC2ADF tADC2 tC2ADR tADCLK tADCLK tOD ANALOG INPUTS CDSCLK2 ADCCLK OUTPUT DATA D<7:0> R (N– 2) G (N– 2) G (N– 2) B (N– 2) B (N– 2) R (N– 1) R (N– 1) G (N– 1) G (N– 1) B (N– 1) B (N– 1) R (N) R (N) G (N) G (N) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE tADC1 tAD tC1 CDSCLK1 PIXEL (N + 2) 00 62 3- 00 4 tC2C1 tC1C2 tPRA Figure 3. 3-Channel CDS Mode Timing tAD PIXEL N tAD ANALOG INPUTS tOD CDSCLK2 ADCCLK OUTPUT DATA D<7:0> tC2 PIXEL (N – 4) PIXEL (N – 4) PIXEL (N – 3) PIXEL (N – 3) PIXEL (N – 2) PIXEL (N – 2) tC1C2 tC1 CDSCLK1 tADC1 HIGH BYTE LOW BYTE LOW BYTEHIGH BYTE LOW BYTEHIGH BYTE PIXEL (N + 1) PIXEL (N + 2) tC2ADR 00 62 3- 00 5 tC2C1 tPRB tC2ADF tADCLK tADCLK Figure 4. 1-Channel CDS Mode Timing

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Alon*****Prabhu

July 15, 2020

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July 12, 2020

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July 8, 2020

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July 2, 2020

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June 25, 2020

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June 23, 2020

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June 15, 2020

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June 12, 2020

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Heat*****lkins

June 12, 2020

This seems to be a good set. I'll update more when I've tested these and can review their working quality.

Mar*****Reyes

May 30, 2020

Very good contact, well packed, hope to buy from you again.

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