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AD9854ASTZ

hot AD9854ASTZ

AD9854ASTZ

For Reference Only

Part Number AD9854ASTZ
Manufacturer Analog Devices Inc.
Description IC DDS QUADRATURE CMOS 80-LQFP
Datasheet AD9854ASTZ Datasheet
Package 80-LQFP
In Stock 759 piece(s)
Unit Price $ 41.11 *
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AD9854ASTZ

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AD9854ASTZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - Direct Digital Synthesis (DDS)
Datasheet AD9854ASTZ Datasheet
Package80-LQFP
Series-
Resolution (Bits)12 b
Master fclk300MHz
Tuning Word Width (Bits)48 b
Voltage - Supply3.14 V ~ 3.47 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case80-LQFP
Supplier Device Package80-LQFP (14x14)

AD9854ASTZ Datasheet

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CMOS 300 MSPS Quadrature Complete DDS AD9854 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved. FEATURES 300 MHz internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit digital-to-analog converters (DACs) Ultrahigh speed comparator, 3 ps rms jitter Excellent dynamic performance 80 dB SFDR at 100 MHz (±1 MHz) AOUT 4× to 20× programmable reference clock multiplier Dual 48-bit programmable frequency registers Dual 14-bit programmable phase offset registers 12-bit programmable amplitude modulation and on/off output shaped keying function Single-pin FSK and BPSK data interfaces PSK capability via input/output interface Linear or nonlinear FM chirp functions with single-pin frequency hold function Frequency-ramped FSK <25 ps rms total jitter in clock generator mode Automatic bidirectional frequency sweeping Sin(x)/x correction Simplified control interfaces 10 MHz serial 2- or 3-wire SPI compatible 100 MHz parallel 8-bit programming 3.3 V single supply Multiple power-down functions Single-ended or differential input reference clock Small, 80-lead LQFP or TQFP with exposed pad APPLICATIONS Agile, quadrature LO frequency synthesis Programmable clock generators FM chirp source for radar and scanning systems Test and measurement equipment Commercial and amateur RF exciters FUNCTIONAL BLOCK DIAGRAM DIGITAL MULTIPLIERS SYSTEM CLOCK DAC RSET INV SINC FILTER F R E Q U E N C Y A C C U M U L A T O R A C C 1 I/O PORT BUFFERS COMPARATOR PROGRAMMING REGISTERS DIFF/SINGLE SELECT REFERENCE CLOCK IN FSK/BPSK/HOLD DATA IN BIDIRECTIONAL INTERNAL/EXTERNAL I/O UPDATE CLOCK READ WRITE SERIAL/ PARALLEL SELECT 6-BIT ADDRESS OR SERIAL PROGRAMMING LINES 8-BIT PARALLEL LOAD MASTER RESET +VS GND CLOCK OUT ANALOG IN OSK ANALOG OUT ANALOG OUT P H A S E -T O - A M P L IT U D E C O N V E R T E R PROGRAMMABLE AMPLITUDE AND RATE CONTROL D Q CK ÷2 INT EXT SYSTEM CLOCK REF CLK BUFFER SYSTEM CLOCK MUX DELTA FREQUENCY RATE TIMER SYSTEM CLOCK DELTA FREQUENCY WORD FREQUENCY TUNING WORD 1 FREQUENCY TUNING WORD 2 FIRST 14-BIT PHASE/OFFSET WORD SECOND 14-BIT PHASE/OFFSET WORD 12-BIT DC CONTROL MUX SYSTEM CLOCK P H A S E A C C U M U L A T O R A C C 2 DDS CORE 12-BIT I DAC 12-BIT Q DAC OR CONTROL DAC I Q 12 MUX MUX M U X M U X SYSTEM CLOCK SYSTEM CLOCK 48 48 48 14 14 BUS 1212 14 17174848 48 AD9854 MODE SELECT 2 3 D E M U X M U X M U X 12 INV SINC FILTER 12 1212 12 I AND Q 12-BIT AM MODULATION 0 0 6 3 6 -0 0 1 4× TO 20× REF CLK MULTIPLIER INTERNAL PROGRAMMABLE UPDATE CLOCK Figure 1.

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AD9854 Rev. E | Page 2 of 52 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 Explanation of Test Levels ........................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 12 Typical Applications ....................................................................... 16 Theory of Operation ...................................................................... 19 Modes of Operation ................................................................... 19 Using the AD9854 .......................................................................... 29 Internal and External Update Clock ........................................ 29 On/Off Output Shaped Keying (OSK) .................................... 29 I and Q DACs.............................................................................. 30 Control DAC ............................................................................... 30 Inverse Sinc Function ................................................................ 31 REFCLK Multiplier .................................................................... 31 Programming the AD9854............................................................ 32 MASTER RESET ........................................................................ 32 Parallel I/O Operation ............................................................... 34 Serial Port I/O Operation.......................................................... 34 General Operation of the Serial Interface ................................... 36 Instruction Byte .......................................................................... 37 Serial Interface Port Pin Descriptions ..................................... 37 Notes on Serial Port Operation ................................................ 37 MSB/LSB Transfers......................................................................... 38 Control Register Description.................................................... 38 Power Dissipation and Thermal Considerations ....................... 40 Thermal Impedance................................................................... 40 Junction Temperature Considerations .................................... 40 Evaluation of Operating Conditions........................................ 41 Thermally Enhanced Package Mounting Guidelines ................ 41 Evaluation Board ............................................................................ 42 Evaluation Board Instructions.................................................. 42 General Operating Instructions ............................................... 42 Using the Provided Software .................................................... 44 Support ........................................................................................ 44 Outline Dimensions ....................................................................... 52 Ordering Guide .......................................................................... 52

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AD9854 Rev. E | Page 3 of 52 REVISION HISTORY 7/07—Rev. D to Rev. E Changed AD9854ASQ to AD9854ASVZ ....................... Universal Changed AD9854AST to AD9854ASTZ......................... Universal Changes to General Description .....................................................4 Changes to Table 1 Endnotes...........................................................7 Changes to Absolute Maximum Ratings Section..........................8 Changes to Power Dissipation Section.........................................40 Changes to Thermally Enhanced Package Mounting Guidelines Section......................................................................41 Changes to Figure 64 ......................................................................47 Changes to Outline Dimensions ...................................................52 Changes to Ordering Guide...........................................................52 11/06—Rev. C to Rev. D Changes to General Description Section .......................................4 Changes to Endnotes in the Power Supply Parameter .................7 Changes to Absolute Maximum Ratings Section..........................8 Added Endnotes to Table 2 ..............................................................8 Changes to Figure 50 ......................................................................29 Changes to Power Dissipation Section.........................................39 Changes to Figure 68 ......................................................................45 Updated Outline Dimensions........................................................51 Changes to Ordering Guide...........................................................51 9/04—Rev. B to Rev. C Updated Format.................................................................. Universal Changes to Table 1 ............................................................................4 Changes to Footnote 2 ......................................................................7 Changes to Explanation of Test Levels Section .............................8 Changes to Theory of Operation Section ....................................17 Changes to Single Tone (Mode 000) Section...............................17 Changes to Ramped FSK (Mode 010) Section............................18 Changes to Basic FM Chirp Programming Steps Section .........23 Changes to Figure 50 ......................................................................27 Changes to Evaluation Board Operating Instructions Section.40 Changes to Filtered IOUT1 and the Filtered IOUT2 Section ...41 Changes to Using the Provided Software Section.......................42 Changes to Figure 68 ......................................................................45 Changes to Figure 69 ......................................................................46 Updated Outline Dimensions........................................................50 Changes to Ordering Guide...........................................................50 3/02—Rev. A to Rev. B Updated Format ................................................................. Universal Renumbered Figures and Tables ...................................... Universal Changes to General Description Section.......................................1 Changes to Functional Block Diagram ..........................................1 Changes to Specifications Section ..................................................4 Changes to Absolute Maximum Ratings Section .........................7 Changes to Pin Function Descriptions ..........................................8 Changes to Figure 3 ........................................................................10 Deleted two Typical Performance Characteristics Graphs........11 Changes to Inverse SINC Function Section ................................28 Changes to Differential REFCLK Enable Section.......................28 Changes to Figure 52 ......................................................................30 Changes to Parallel I/O Operation Section .................................32 Changes to General Operation of the Serial Interface Section .33 Changes to Figure 57 ......................................................................34 Replaced Operating Instructions Section....................................40 Changes to Figure 68 ......................................................................44 Changes to Figure 69 ......................................................................45 Changes to Customer Evaluation Board Table............................46

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AD9854 Rev. E | Page 4 of 52 GENERAL DESCRIPTION The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with two internal high speed, high performance quadrature DACs to form a digitally programmable I and Q synthesizer function. When referenced to an accurate clock source, the AD9854 generates highly stable, frequency-phase, amplitude-programmable sine and cosine outputs that can be used as an agile LO in communications, radar, and many other applications. The innovative high speed DDS core of the AD9854 provides 48-bit frequency resolution (1 μHz tuning resolution with 300 MHz SYSCLK). Maintaining 17 bits ensures excellent SFDR. The circuit architecture of the AD9854 allows the generation of simultaneous quadrature output signals at frequencies up to 150 MHz, which can be digitally tuned at a rate of up to 100 million new frequencies per second. The sine wave output (externally filtered) can be converted to a square wave by the internal comparator for agile clock generator applications. The device provides two 14-bit phase registers and a single pin for BPSK operation. For higher-order PSK operation, the I/O interface can be used for phase changes. The 12-bit I and Q DACs, coupled with the innovative DDS architecture, provide excellent wideband and narrow-band output SFDR. The Q DAC can also be configured as a user-programmable control DAC if the quadrature function is not desired. When configured with the comparator, the 12-bit control DAC facilitates static duty cycle control in high speed clock generator applications. Two 12-bit digital multipliers permit programmable amplitude modulation, on/off output shaped keying, and precise amplitude control of the quadrature output. Chirp functionality is also included to facilitate wide bandwidth frequency sweeping applications. The programmable 4× to 20× REFCLK multiplier circuit of the AD9854 internally generates the 300 MHz system clock from an external lower frequency reference clock. This saves the user the expense and difficulty of implementing a 300 MHz system clock source. Direct 300 MHz clocking is also accommodated with either single- ended or differential inputs. Single-pin conventional FSK and the enhanced spectral qualities of ramped FSK are supported. The AD9854 uses advanced 0.35 μm CMOS technology to provide a high level of functionality on a single 3.3 V supply. The AD9854 is pin-for-pin compatible with the AD9852 single- tone synthesizer. It is specified to operate over the extended industrial temperature range of −40°C to +85°C.

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AD9854 Rev. E | Page 5 of 52 SPECIFICATIONS VS = 3.3 V ± 5%, RSET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASVZ, external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9854ASTZ, unless otherwise noted. Table 1. AD9854ASVZ AD9854ASTZ Parameter Temp Test Level Min Typ Max Min Typ Max Unit REFERENCE CLOCK INPUT CHARACTERISTICS1 Internal System Clock Frequency Range REFCLK Multiplier Enabled Full VI 20 300 20 200 MHz REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz External Reference Clock Frequency Range REFCLK Multiplier Enabled Full VI 5 75 5 50 MHz REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz Duty Cycle 25°C IV 45 50 55 45 50 55 % Input Capacitance 25°C IV 3 3 pF Input Impedance 25°C IV 100 100 kΩ Differential Mode Common-Mode Voltage Range Minimum Signal Amplitude2 25°C IV 400 400 mV p-p Common-Mode Range 25°C IV 1.6 1.75 1.9 1.6 1.75 1.9 V VIH (Single-Ended Mode) 25°C IV 2.3 2.3 V VIL (Single-Ended Mode) 25°C IV 1 1 V DAC STATIC OUTPUT CHARACTERISTICS Output Update Speed Full I 300 200 MSPS Resolution 25°C IV 12 12 Bits I and Q Full-Scale Output Current 25°C IV 5 10 20 5 10 20 mA I and Q DAC DC Gain Imbalance3 25°C I −0.5 +0.15 +0.5 −0.5 +0.15 +0.5 dB Gain Error 25°C I −6 +2.25 −6 +2.25 % FS Output Offset 25°C I 2 2 μA Differential Nonlinearity 25°C I 0.3 1.25 0.3 1.25 LSB Integral Nonlinearity 25°C I 0.6 1.66 0.6 1.66 LSB Output Impedance 25°C IV 100 100 kΩ Voltage Compliance Range 25°C I −0.5 +1.0 −0.5 +1.0 V DAC DYNAMIC OUTPUT CHARACTERISTICS I and Q DAC Quadrature Phase Error 25°C IV 0.2 1 0.2 1 Degrees DAC Wideband SFDR 1 MHz to 20 MHz AOUT 25°C V 58 58 dBc 20 MHz to 40 MHz AOUT 25°C V 56 56 dBc 40 MHz to 60 MHz AOUT 25°C V 52 52 dBc 60 MHz to 80 MHz AOUT 25°C V 48 48 dBc 80 MHz to 100 MHz AOUT 25°C V 48 48 dBc 100 MHz to 120 MHz AOUT 25°C V 48 48 dBc DAC Narrow-Band SFDR 10 MHz AOUT (±1 MHz) 25°C V 83 83 dBc 10 MHz AOUT (±250 kHz) 25°C V 83 83 dBc 10 MHz AOUT (±50 kHz) 25°C V 91 91 dBc 41 MHz AOUT (±1 MHz) 25°C V 82 82 dBc 41 MHz AOUT (±250 kHz) 25°C V 84 84 dBc 41 MHz AOUT (±50 kHz) 25°C V 89 89 dBc 119 MHz AOUT (±1 MHz) 25°C V 71 71 dBc 119 MHz AOUT (±250 kHz) 25°C V 77 77 dBc 119 MHz AOUT (±50 kHz) 25°C V 83 83 dBc

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AD9854 Rev. E | Page 6 of 52 AD9854ASVZ AD9854ASTZ Parameter Temp Test Level Min Typ Max Min Typ Max Unit Residual Phase Noise (AOUT = 5 MHz, External Clock = 30 MHz REFCLK Multiplier Engaged at 10×) 1 kHz Offset 25°C V 140 140 dBc/Hz 10 kHz Offset 25°C V 138 138 dBc/Hz 100 kHz Offset 25°C V 142 142 dBc/Hz (AOUT = 5 MHz, External Clock = 300 MHz, REFCLK Multiplier Bypassed) 1 kHz Offset 25°C V 142 142 dBc/Hz 10 kHz Offset 25°C V 148 148 dBc/Hz 100 kHz Offset 25°C V 152 152 dBc/Hz PIPELINE DELAYS4, 5 , 6 DDS Core (Phase Accumulator and Phase-to-Amp Converter) 25°C IV 33 33 SYSCLK cycles Frequency Accumulator 25°C IV 26 26 SYSCLK cycles Inverse Sinc Filter 25°C IV 16 16 SYSCLK cycles Digital Multiplier 25°C IV 9 9 SYSCLK cycles DAC 25°C IV 1 1 SYSCLK cycles I/O Update Clock (Internal Mode) 25°C IV 2 2 SYSCLK cycles I/O Update Clock (External Mode) 25°C IV 3 3 SYSCLK cycles MASTER RESET DURATION 25°C IV 10 10 SYSCLK cycles COMPARATOR INPUT CHARACTERISTICS Input Capacitance 25°C V 3 3 pF Input Resistance 25°C IV 500 500 kΩ Input Current 25°C I ±1 ±5 ±1 ±5 μA Hysteresis 25°C IV 10 20 10 20 mV p-p COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage, High-Z Load Full VI 3.1 3.1 V Logic 0 Voltage, High-Z Load Full VI 0.16 0.16 V Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I 9 11 9 11 dBm Propagation Delay 25°C IV 3 3 ns Output Duty Cycle Error7 25°C I −10 ±1 +10 −10 ±1 +10 % Rise/Fall Times, 5 pF Load 25°C V 2 2 ns Toggle Rate, High-Z Load 25°C IV 300 350 300 350 MHz Toggle Rate, 50 Ω Load 25°C IV 375 400 375 400 MHz Output Cycle-to-Cycle Jitter8 IV 4.0 4.0 ps rms COMPARATOR NARROW-BAND SFDR9 10 MHz (±1 MHz) 25°C V 84 84 dBc 10 MHz (±250 MHz) 25°C V 84 84 dBc 10 MHz (±50 MHz) 25°C V 92 92 dBc 41 MHz (±1 MHz) 25°C V 76 76 dBc 41 MHz (±250 MHz) 25°C V 82 82 dBc 41 MHz (±50 MHz) 25°C V 89 89 dBc 119 MHz (±1 MHz) 25°C V 73 dBc 119 MHz (±250 MHz) 25°C V 73 dBc 119 MHz (±50 MHz) 25°C V 83 dBc CLOCK GENERATOR OUTPUT JITTER9 5 MHz AOUT 25°C V 23 23 ps rms 40 MHz AOUT 25°C V 12 12 ps rms 100 MHz AOUT 25°C V 7 7 ps rms

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AD9854 Rev. E | Page 7 of 52 AD9854ASVZ AD9854ASTZ Parameter Temp Test Level Min Typ Max Min Typ Max Unit PARALLEL I/O TIMING CHARACTERISTICS tASU (Address Setup Time to WR Signal Active) Full IV 8.0 7.5 8.0 7.5 ns tADHW (Address Hold Time to WR Signal Inactive) Full IV 0 0 ns tDSU (Data Setup Time to WR Signal Inactive) Full IV 3.0 1.6 3.0 1.6 ns tDHD (Data Hold Time to WR Signal Inactive) Full IV 0 0 ns tWRLOW (WR Signal Minimum Low Time) Full IV 2.5 1.8 2.5 1.8 ns tWRHIGH (WR Signal Minimum High Time) Full IV 7 7 ns tWR (Minimum WR Time) Full IV 10.5 10.5 ns tADV (Address to Data Valid Time) Full V 15 15 15 15 ns tADHR (Address Hold Time to RD Signal Inactive) Full IV 5 5 ns tRDLOV (RD Low to Output Valid) Full IV 15 15 ns tRDHOZ (RD High to Data Three-State) Full IV 10 10 ns SERIAL I/O TIMING CHARACTERISTICS tPRE (CS Setup Time) Full IV 30 30 ns tSCLK (Period of Serial Data Clock) Full IV 100 100 ns tDSU (Serial Data Setup Time) Full IV 30 30 ns tSCLKPWH (Serial Data Clock Pulse Width High) Full IV 40 40 ns tSCLKPWL (Serial Data Clock Pulse Width Low) Full IV 40 40 ns tDHLD (Serial Data Hold Time) Full IV 0 0 ns tDV (Data Valid Time) Full V 30 30 ns CMOS LOGIC INPUTS10 Logic 1 Voltage 25°C I 2.2 2.2 V Logic 0 Voltage 25°C I 0.8 0.8 V Logic 1 Current 25°C IV ±5 ±12 μA Logic 0 Current 25°C IV ±5 ±12 μA Input Capacitance 25°C V 3 3 pF POWER SUPPLY11, 15 VS Current11, 12, 15 25°C I 1050 1210 755 865 mA VS Current11, 13, 15 25°C I 710 816 515 585 mA VS Current14 25°C I 600 685 435 495 mA PDISS11, 12, 15 25°C I 3.475 4.190 2.490 3.000 W PDISS11, 13, 15 25°C I 2.345 2.825 1.700 2.025 W PDISS14 25°C I 1.975 2.375 1.435 1.715 W PDISS Power-Down Mode 25°C I 1 50 1 50 mW 1 The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine wave centered at one-half the applied VDD or a 3 V TTL-level pulse input. 2 An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins. 3 The I and Q gain imbalance is digitally adjustable to less than 0.01 dB. 4 Pipeline delays of each individual block are fixed; however, if the first eight MSBs of a tuning word are 0s, the delay appears longer. This is due to insufficient phase accumulation per system clock period to produce enough LSB amplitude to the DAC. 5 If a feature such as the inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount. 6 The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks. 7 Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold. 8 Represents the comparator’s inherent cycle-to-cycle jitter contribution. The input signal is a 1 V, 40 MHz square wave, and the measurement device is a Wavecrest DTS-2075. 9 Comparator input originates from the analog output section via the external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 Ω. 10 Avoid overdriving digital inputs. (Refer to the equivalent circuits in Figure 3.) 11 If all device functions are enabled, it is not recommended to simultaneously operate the device at the maximum ambient temperature of 85°C and at the maximum internal clock frequency. This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal Considerations section for derating and thermal management information. 12 All functions engaged. 13 All functions except inverse sinc engaged. 14 All functions except inverse sinc and digital multipliers engaged. 15 In most cases, disabling the inverse sinc filter reduces power consumption by approximately 30%.

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AD9854 Rev. E | Page 8 of 52 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Maximum Junction Temperature 150°C VS 4 V Digital Inputs −0.7 V to +VS Digital Output Current 5 mA Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Maximum Clock Frequency (ASVZ) 300 MHz Maximum Clock Frequency (ASTZ) 200 MHz Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The heat sink of the AD9854ASVZ 80-lead TQFP package must be soldered to the PCB. Table 3. Thermal Characteristic TQFP LQFP θJA (0 m/sec airflow)1, 2, 3 16.2°C/W 38°C/W θJMA (1.0 m/sec airflow)2, 3, 4, 5 13.7°C/W θJMA (2.5 m/sec airflow)2, 3, 4, 5 12.8°C/W ΨJT1, 2 0.3°C/W θJC6, 7 2.0°C/W 1 Per JEDEC JESD51-2 (heat sink soldered to PCB). 2 2S2P JEDEC test board. 3 Values of θJA are provided for package comparison and PCB design considerations. 4 Per JEDEC JESD51-6 (heat sink soldered to PCB). 5 Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the more metal that is directly in contact with the package leads from metal traces through holes, ground, and power planes, the more θJA is reduced. 6 Per MIL-Std 883, Method 1012.1. 7 Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. To determine the junction temperature on the application PCB use the following equation: TJ = Tcase + (ΨJT × PD) where: TJ is the junction temperature expressed in degrees Celsius. Tcase is the case temperature expressed in degrees Celsius, as measured by the user at the top center of the package. ΨJT = 0.3°C/W. PD is the power dissipation (PD); see the Power Dissipation and Thermal Considerations section for the method to calculate PD. EXPLANATION OF TEST LEVELS Table 3. Test Level Description I 100% production tested. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI Devices are 100% production tested at 25°C and guaranteed by design and characterization testing for industrial operating temperature range. ESD CAUTION

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AD9854 Rev. E | Page 9 of 52 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 71 70 69 6875 74 73 72 21 22 23 24 25 26 27 28 29 30 31 32 33 1 2 3 4 5 6 7 8 9 10 11 13 12 60 59 58 57 56 55 54 53 52 51 50 49 48 NC = NO CONNECT AD9854 TOP VIEW (Not to Scale) W R /S C L K R D /C S D V D D D V D D D V D D D G N D D G N D D G N D F S K /B P S K /H O L D O S K A V D D A V D D A G N D D V D D D V D D D G N D D G N D D G N D D G N D D V D D D V D D D G N D M A S T E R R E S E T S /P S E L E C T R E F C L K R E F C L K D7 D6 D5 D4 D3 D2 D1 D0 DVDD DVDD DGND DGND NC AVDD AGND NC NC DAC RSET DACBP AVDD AGND IOUT2 IOUT2 AVDD IOUT1 IOUT1 PIN 1 INDICATOR 14 15 16 17 18 20 19 47 46 45 44 43 42 41 A5 A4 A3 A2/IO RESET A1/SDO A0/SDIO I/O UD CLK AGND AGND AGND AVDD VINN VINP AGND 64 63 62 6167 66 65 34 35 36 37 38 39 40 A G N D N C V O U T A V D D A V D D A G N D A G N D A G N D A G N D A V D D D IF F C L K E N A B L E N C A G N D P L L F IL T E R 00 63 6- 0 02 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 to 8 D7 to D0 8-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode. 9, 10, 23, 24, 25, 73, 74, 79, 80 DVDD Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND and DGND. 11, 12, 26, 27, 28, 72, 75 to 78 DGND Connections for the Digital Circuitry Ground Return. Same potential as AGND. 13, 35, 57, 58, 63 NC No Internal Connection. 14 to 16 A5 to A3 Parallel Address Inputs for Program Registers (Part of 6-Bit Parallel Address Inputs for Program Register, A5:A0). Used only in parallel programming mode. 17 A2/IO RESET Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program Register, A5:A0)/IO Reset. A2 is used only in parallel programming mode. IO RESET is used when the serial programming mode is selected, allowing an IO RESET of the serial communication bus that is unresponsive due to improper programming protocol. Resetting the serial bus in this manner does not affect previous programming, nor does it invoke the default programming values listed in Table 8. Active high. 18 A1/SDO Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program Register, A5:A0)/Unidirectional Serial Data Output. A1 is used only in parallel programming mode. SDO is used in 3-wire serial communication mode when the serial programming mode is selected. 19 A0/SDIO Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program Register, A5:A0)/Bidirectional Serial Data I/O. A0 is used only in parallel programming mode. SDIO is used in 2-wire serial communication mode.

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hotAD9854ASTZ ADG841YKSZ-REEL7 Analog Devices Inc., IC SWITCH SPST SC70-6, 6-TSSOP, SC-88, SOT-363, - View
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hotAD9854ASTZ AD9739BBCZRL Analog Devices Inc., IC DAC 14BIT 2.5GSPS RF 160BGA, 160-LFBGA, CSPBGA, - View
hotAD9854ASTZ AD9742ARZRL Analog Devices Inc., IC DAC 12BIT 210MSPS 28-SOIC, 28-SOIC (0.295", 7.50mm Width), - View
hotAD9854ASTZ AD9776ABSVZ Analog Devices Inc., IC DAC 12BIT 1.0GSPS 100TQFP, 100-TQFP Exposed Pad, - View
hotAD9854ASTZ AD9231BCPZ-40 Analog Devices Inc., IC ADC 12BIT 40MSPS 64LFCSP, 64-VFQFN Exposed Pad, CSP, - View
hotAD9854ASTZ AD9225ARZRL Analog Devices Inc., IC ADC 12BIT 25MSPS 28SOIC, 28-SOIC (0.295", 7.50mm Width), - View
hotAD9854ASTZ AD9288BSTZRL-40 Analog Devices Inc., IC ADC 8BIT DUAL 40MSPS 48LQFP, 48-LQFP, - View

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