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AD9883AKSTZ-110

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AD9883AKSTZ-110

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Part Number AD9883AKSTZ-110
Manufacturer Analog Devices Inc.
Description IC FLAT PANEL INTERFACE 80-LQFP
Datasheet AD9883AKSTZ-110 Datasheet
Package 80-LQFP
In Stock 8,684 piece(s)
Unit Price $ 9.1600 *
Lead Time Can Ship Immediately
Estimated Delivery Time Nov 2 - Nov 7 (Choose Expedited Shipping)
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Part Number # AD9883AKSTZ-110 (Interface - Specialized) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD9883AKSTZ-110 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - Specialized
Datasheet AD9883AKSTZ-110Datasheet
Package80-LQFP
Series-
ApplicationsDisplays, Monitors, TV
InterfaceAnalog
Voltage - Supply3 V ~ 3.6 V
Package / Case80-LQFP
Supplier Device Package80-LQFP (14x14)
Mounting TypeSurface Mount

AD9883AKSTZ-110 Datasheet

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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. a AD9883A One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays FUNCTIONAL BLOCK DIAGRAM RAIN ROUTA GAIN GOUTA BAIN BOUTA MIDSCV SYNC PROCESSING AND CLOCK GENERATION HSYNC COAST CLAMP FILT DTACK HSOUT VSOUT SOGOUT REF REF BYPASS SERIAL REGISTER AND POWER MANAGEMENT SCL SDA A0 AD9883A CLAMP 8 A/D CLAMP 8 A/D CLAMP 8 A/D FEATURES Industrial Temperature Range Operation 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V Power Supply Full Sync Processing Sync Detect for Hot Plugging Midscale Clamping Power-Down Mode Low Power: 500 mW Typical 4:2:2 Output Format Mode APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV GENERAL DESCRIPTION The AD9883A is a complete 8-bit, 140 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 × 1024 at 75 Hz). The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and Hsync and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9883A’s on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync, and clock output phase relationships are maintained. The AD9883A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface. Fabricated in an advanced CMOS process, the AD9883A is pro- vided in a space-saving 80-lead LQFP surface-mount plastic package and is specified over the –40°C to +85°C temperature range.

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REV. B–2– AD9883A–SPECIFICATIONS Test AD9883AKST-110 AD9883AKST-140 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity 25°C I ±0.5 +1.25/–1.0 ±0.5 +1.35/–1.0 LSB Full VI +1.35/–1.0 +1.45/–1.0 LSB Integral Nonlinearity 25°C I ±0.5 ±1.85 ±0.5 ±2.0 LSB Full VI ±2.0 ±2.3 LSB No Missing Codes Full VI Guaranteed Guaranteed ANALOG INPUT Input Voltage Range Minimum Full VI 0.5 0.5 V p-p Maximum Full VI 1.0 1.0 V p-p Gain Tempco 25°C V 100 100 ppm/°C Input Bias Current 25°C IV 1 1 µA Full IV 1 1 µA Input Offset Voltage Full VI 7 50 7 70 mV Input Full-Scale Matching Full VI 1.5 6.0 1.5 8.0 % FS Offset Adjustment Range Full VI 46 49 52 46 49 52 % FS REFERENCE OUTPUT Output Voltage Full VI 1.20 1.25 1.32 1.20 1.25 1.32 V Temperature Coefficient Full V ±50 ±50 ppm/°C SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 110 140 MSPS Minimum Conversion Rate Full IV 10 10 MSPS Data to Clock Skew Full IV –0.5 +2.0 –0.5 +2.0 ns tBUFF Full VI 4.7 4.7 µs tSTAH Full VI 4.0 4.0 µs tDHO Full VI 0 0 µs tDAL Full VI 4.7 4.7 µs tDAH Full VI 4.0 4.0 µs tDSU Full VI 250 250 ns tSTASU Full VI 4.7 4.7 µs tSTOSU Full VI 4.0 4.0 µs HSYNC Input Frequency Full IV 15 110 15 110 kHz Maximum PLL Clock Rate Full VI 110 140 MHz Minimum PLL Clock Rate Full IV 12 12 MHz PLL Jitter 25°C IV 400 7001 400 7001 ps p-p Full IV 10001 10001 ps p-p Sampling Phase Tempco Full IV 15 15 ps/°C DIGITAL INPUTS Input Voltage, High (VIH) Full VI 2.5 2.5 V Input Voltage, Low (VIL) Full VI 0.8 0.8 V Input Voltage, High (VIH) Full V –1.0 –1.0 µA Input Voltage, Low (VIL) Full V +1.0 +1.0 µA Input Capacitance 25°C V 3 3 pF Analog Interface (VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)

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REV. B –3– AD9883A Test AD9883AKST-110 AD9883AKST-140 Parameter Temp Level Min Typ Max Min Typ Max Unit DIGITAL OUTPUTS Output Voltage, High (VOH) Full VI VD – 0.1 VD – 0.1 V Output Voltage, Low (VOL) Full VI 0.1 0.1 V Duty Cycle DATACK Full IV 45 50 55 45 50 55 % Output Coding Binary Binary POWER SUPPLY VD Supply Voltage Full IV 3.0 3.3 3.6 3.15 3.3 3.6 V VDD Supply Voltage Full IV 2.2 3.3 3.6 2.2 3.3 3.6 V PVD Supply Voltage Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V ID Supply Current (VD) 25°C V 132 180 mA IDD Supply Current (VDD) 2 25°C V 19 26 mA IPVD Supply Current (PVD) 25°C V 8 11 mA Total Power Dissipation Full VI 525 650 650 800 mW Power-Down Supply Current Full VI 5 10 5 10 mA Power-Down Dissipation Full VI 16.5 33 16.5 33 mW DYNAMIC PERFORMANCE Analog Bandwidth, Full Power 25°C V 300 300 MHz Transient Response 25°C V 2 2 ns Overvoltage Recovery Time 25°C V 1.5 1.5 ns Signal-to-Noise Ratio (SNR) 25°C V 44 43 dB (Without Harmonics) Full V 43 42 dB fIN = 40.7 MHz Crosstalk Full V 55 55 dBc THERMAL CHARACTERISTICS θJC Junction-to-Case Thermal Resistance V 16 16 °C/W θJA Junction-to-Ambient Thermal Resistance V 35 35 °C/W NOTES 1VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693. 2DATACK Load = 15 pF, Data Load = 5 pF. Specifications subject to change without notice.

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REV. B AD9883A –4– Test AD9883ABST–110 AD9883ABST–140 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity 25°C I ±0.5 +1.25/–1.0 ±0.5 +1.5/–1.0 LSB Full VI +1.5/–1.0 +1.81/–1.0 LSB Integral Nonlinearity 25°C I ±0.5 ±1.85 ±0.5 ±1.85 LSB Full VI ±3.2 ±3.2 LSB ANALOG INPUT Input Voltage Range Minimum Full VI 0.5 0.5 V p-p Maximum Full VI 1.0 1.0 V p-p Gain Tempco 25°C V 100 100 ppm/°C Input Bias Current 25°C IV 1 1 µA Full IV 2 2 µA Input Offset Voltage Full VI 7 75 7 75 mV Input Full-Scale Matching Full VI 1.5 8.0 1.5 10.0 % FS Offset Adjustment Range Full VI 46 49 52 46 49 52 % FS REFERENCE OUTPUT Output Voltage Full VI 1.19 1.25 1.33 1.19 1.25 1.33 V Temperature Coefficient Full V ±100 ±100 ppm/°C SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 110 140 MSPS Minimum Conversion Rate Full IV 10 10 MSPS Data to Clock Skew Full IV –0.5 +2.0 –0.5 +2.0 ns tBUFF Full VI 4.7 4.7 µs tSTAH Full VI 4.0 4.0 µs tDHO Full VI 0 0 µs tDAL Full VI 4.7 4.7 µs tDAH Full VI 4.0 4.0 µs tDSU Full VI 250 250 µs tSTASU Full VI 4.7 4.7 µs tSTOSU Full VI 4.0 4.0 µs HSYNC Input Frequency Full IV 15 110 15 110 kHz Maximum PLL Clock Rate Full VI 110 140 MHz Minimum PLL Clock Rate Full IV 12 12 MHz PLL Jitter 25°C IV 400 7001 400 7001 ps p-p Full IV 11001 11001 ps p-p Sampling Phase Tempco Full IV 15 15 ps/°C DIGITAL INPUTS Input Voltage, High (VIH) Full VI 2.5 2.5 V Input Voltage, Low (VIL) Full VI 0.8 0.8 V Input Current, High (IIH) Full V –1.0 –1.0 µA Input Current, Low (IIL) Full V 1.0 1.0 µA Input Capacitance +25°C V 3 3 pF DIGITAL OUTPUTS Output Voltage, High (VOH) Full VI VD – 0.1 VD – 0.1 V Output Voltage, Low (VOL) Full VI 0.1 0.1 V Duty Cycle, DATACK Full IV 45 50 55 45 50 55 % Output Coding Binary Binary Analog Interface (VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)

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REV. B AD9883A –5– Test AD9883ABST–110 AD9883ABST–140 Parameter Temp Level Min Typ Max Min Typ Max Unit POWER SUPPLY VD Supply Voltage Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V VDD Supply Voltage Full IV 2.2 3.3 3.6 2.2 3.3 3.6 V PVD Supply Voltage Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V ID Supply Current (VD) 25°C V 132 163 mA IDD Supply Current (VDD) 2 25°C V 19 24 mA IPVD Supply Current (PVD) 25°C V 8 10 mA Total Power Dissipation Full VI 525 700 650 850 mW Power-Down Supply Current Full VI 5 15 5 15 mA Power-Down Dissipation Full VI 16.5 33 16.5 33 mW DYNAMIC PERFORMANCE Analog Bandwidth, Full Power 25°C V 300 300 MHz Transient Response 25°C V 2 2 ns Overvoltage Recovery Time 25°C V 1.5 1.5 ns Signal-to-Noise Ratio (SNR) 25°C V 44 43 dB (Without Harmonics) Full V 43 42 dB fIN = 40.7 MHz Crosstalk Full V 55 55 dBc THERMAL CHARACTERISTICS θJC Junction-to-Case 16 16 Thermal Resistance V °C/W θJA Junction-to-Ambient 35 35 Thermal Resistance V °C/W NOTES 1VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693. 2DATACK Load = 15 pF, Data Load = 5 pF. Specifications subject to change without notice.

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REV. B AD9883A –6– ABSOLUTE MAXIMUM RATINGS* VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25°C; guaranteed by design and characterization testing. ORDERING GUIDE Temperature Package Package Model Range Description Option AD9883AKST-140 0°C to 70°C LQFP ST-80 AD9883AKST-110 0°C to 70°C LQFP ST-80 AD9883AKSTZ-110* 0°C to 70°C LQFP ST-80 AD9883AKSTZ-140* 0°C to 70°C LQFP ST-80 AD9883ABST-110 –40°C to +85°C LQFP ST-80 AD9883ABST-140 –40°C to +85°C LQFP ST-80 AD9883ABST-RL110 –40°C to +85°C LQFP ST-80 AD9883ABST-RL140 –40°C to +85°C LQFP ST-80 AD9883A/PCB 25°C Evaluation Board *Lead-free product CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9883A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

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REV. B –7– AD9883A PIN CONFIGURATION GND GREEN <7> GREEN <6> GREEN <5> GREEN <4> GREEN <3> GREEN <2> GREEN <1> GREEN <0> GND VDD BLUE <7> BLUE <6> BLUE <5> BLUE <4> BLUE <3> BLUE <2> BLUE <1> BLUE <0> GND GND GND GND GND GND GND VD VD VD VD VD VD REF BYPASS SDA SCL A0 RAIN GAIN BAIN SOGIN 80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AD9883A 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 G N D V D D V D D R E D < 0 > R E D < 1 > R E D < 2 > R E D < 3 > R E D < 4 > R E D < 5 > R E D < 6 > R E D < 7 > V D D G N D D A T A C K H S O U T S O G O U T G N D V D G N D V S O U T G N D V D D V D D G N D G N D P V D P V D G N D M ID S C V C L A M P V D G N D C O A S T H S Y N C V S Y N C G N D F IL T P V D P V D G N D Table I. Complete Pinout List Pin Type Mnemonic Function Value Pin No. Inputs RAIN Analog Input for Converter R 0.0 V to 1.0 V 54 GAIN Analog Input for Converter G 0.0 V to 1.0 V 48 BAIN Analog Input for Converter B 0.0 V to 1.0 V 43 HSYNC Horizontal SYNC Input 3.3 V CMOS 30 VSYNC Vertical SYNC Input 3.3 V CMOS 31 SOGIN Input for Sync-on-Green 0.0 V to 1.0 V 49 CLAMP Clamp Input (External CLAMP Signal) 3.3 V CMOS 38 COAST PLL COAST Signal Input 3.3 V CMOS 29 Outputs Red [7:0] Outputs of Converter Red, Bit 7 is the MSB 3.3 V CMOS 70–77 Green [7:0] Outputs of Converter Green, Bit 7 is the MSB 3.3 V CMOS 2–9 Blue [7:0] Outputs of Converter Blue, Bit 7 is the MSB 3.3 V CMOS 12–19 DATACK Data Output Clock 3.3 V CMOS 67 HSOUT HSYNC Output (Phase-Aligned with DATACK) 3.3 V CMOS 66 VSOUT VSYNC Output (Phase-Aligned with DATACK) 3.3 V CMOS 64 SOGOUT Sync-on-Green Slicer Output 3.3 V CMOS 65 References REF BYPASS Internal Reference Bypass 1.25 V 58 MIDSCV Internal Midscale Voltage Bypass 37 FILT Connection for External Filter Components for Internal PLL 33 Power Supply VD Analog Power Supply 3.3 V 39, 42, 45, 46, 51, 52, 59, 62 VDD Output Power Supply 3.3 V 11, 22, 23, 69, 78, 79 PVD PLL Power Supply 3.3 V 26, 27, 34, 35 GND Ground 0 V 1, 10, 20, 21, 24, 25, 28, 32, 36, 40, 41, 44, 47, 50, 53, 60, 61, 63, 68, 80 Control SDA Serial Port Data I/O 3.3 V CMOS 57 SCL Serial Port Data Clock (100 kHz Maximum) 3.3 V CMOS 56 A0 Serial Port Address Input 1 3.3 V CMOS 55

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REV. B AD9883A –8– PIN FUNCTION DESCRIPTIONS Pin Name Function OUTPUTS HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be pro- grammed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to horizontal sync can always be determined. VSOUT Vertical Sync Output A reconstructed and phase-aligned version of the video Vsync. The polarity of this output can be controlled via a serial bus bit. The placement and duration in all modes is set by the graphics transmitter. SOGOUT Sync-On-Green Slicer Output This pin outputs either the signal from the Sync-on-Green slicer comparator or an unprocessed but delayed version of the Hsync input. See the Sync Processing Block Diagram (Figure 12) to view how this pin is connected. (Note: Besides slicing off SOG, the output from this pin gets no other additional processing on the AD9883A. Vsync separation is performed via the sync separator.) SERIAL PORT (2-Wire) SDA Serial Port Data I/O SCL Serial Port Data Clock A0 Serial Port Address Input 1 For a full description of the 2-wire serial register and how it works, refer to the 2-Wire Serial Control Port section. DATA OUTPUTS RED Data Output, Red Channel GREEN Data Output, Green Channel BLUE Data Output, Blue Channel The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained. For exact timing information, refer to Figures 7, 8, and 9. DATA CLOCK OUTPUT DATACK Data Output Clock This is the main clock output signal used to strobe the output data and HSOUT into external logic. It is produced by the internal clock generator and is synchronous with the internal pixel sampling clock. When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The Data, DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained. INPUTS RAIN Analog Input for Red Channel GAIN Analog Input for Green Channel BAIN Analog Input for Blue Channel High impedance inputs that accept the Red, Green, and Blue channel graphics signals, respectively. (The three channels are identical, and can be used for any colors, but colors are assigned for convenient reference.) They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation. HSYNC Horizontal Sync Input This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by serial register 0EH Bit 6 (Hsync Polarity). Only the leading edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the falling edge of Hsync is used. When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V. VSYNC Vertical Sync Input This is the input for vertical sync. SOGIN Sync-on-Green Input This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal. The default voltage threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync information that must be separated before passing the horizontal sync signal to Hsync.) When not used, this input should be left unconnected. For more details on this function and how it should be configured, refer to the Sync-on-Green section.

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REV. B AD9883A –9– DESIGN GUIDE General Description The AD9883A is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel monitors or projectors. The circuit is ideal for providing a computer interface for HDTV monitors or as the front end to high performance video scan converters. Implemented in a high performance CMOS process, the interface can capture signals with pixel rates up to 110 MHz. The AD9883A includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. All controls are programmable via a 2-wire serial interface. Full integration of these sensitive analog functions makes system design straightforward and less sensitive to the physical and electrical environment. With a typical power dissipation of only 500 mW and an operating temperature range of 0°C to 70°C, the device requires no special environmental considerations. Digital Inputs All digital inputs on the AD9883A operate to 3.3 V CMOS levels. However, all digital inputs are 5 V tolerant. Applying 5 V to them will not cause any damage. Input Signal Handling The AD9883A has three high impedance analog input pins for the Red, Green, and Blue channels. They will accommodate signals ranging from 0.5 V to 1.0 V p-p. Signals are typically brought onto the interface board via a DVI-I connector, a 15-pin D connector, or via BNC connectors. The AD9883A should be located as close as practical to the input connector. Signals should be routed via matched-impedance traces (normally 75 Ω) to the IC input pins. PIN FUNCTION DESCRIPTIONS (continued) Pin Name Function CLAMP External Clamp Input This logic input may be used to define the time during which the input signal is clamped to ground. It should be exer- cised when the reference dc level is known to be present on the analog input channels, typically during the back porch of the graphics signal. The CLAMP pin is enabled by setting control bit Clamp Function to 1, (register 0FH, Bit 7, default is 0). When disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the Hsync input. The logic sense of this pin is controlled by Clamp Polarity register 0FH, Bit 6. When not used, this pin must be grounded and Clamp Function programmed to 0. COAST Clock Generator Coast Input (Optional) This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal sync pulses during the vertical interval. The COAST signal is generally not required for PC-generated signals. The logic sense of this pin is controlled by Coast Polarity (register 0FH, Bit 3). When not used, this pin may be grounded and Coast Polarity programmed to 1, or tied HIGH (to VD through a 10 kΩ resistor) and Coast Polarity programmed to 0. Coast Polarity defaults to 1 at power-up. REF BYPASS Internal Reference BYPASS Bypass for the internal 1.25 V band gap reference. It should be connected to ground through a 0.1 µF capacitor. The absolute accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most AD9883A applications. If higher accuracy is required, an external reference may be employed instead. MIDSCV Midscale Voltage Reference BYPASS Bypass for the internal midscale voltage reference. It should be connected to ground through a 0.1 µF capacitor. The exact voltage varies with the gain setting of the Blue channel. FILT External Filter Connection For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics on this node. POWER SUPPLY VD Main Power Supply These pins supply power to the main elements of the circuit. They should be filtered and as quiet as possible. VDD Digital Output Power Supply A large number of output pins (up to 25) switching at high speed (up to 110 MHz) generates a lot of power supply transients (noise). These supply pins are identified separately from the VD pins so special care can be taken to minimize output noise transferred into the sensitive analog circuitry. If the AD9883A is interfacing with lower voltage logic, VDD may be connected to a lower supply voltage (as low as 2.5 V) for compatibility. PVD Clock Generator Power Supply The most sensitive portion of the AD9883A is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins. GND Ground The ground return for all circuitry on-chip. It is recommended that the AD9883A be assembled on a single solid ground plane, with careful attention given to ground current paths.

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