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ADADC80-12

hot ADADC80-12

ADADC80-12

For Reference Only

Part Number ADADC80-12
Manufacturer Analog Devices Inc.
Description IC ADC 12-BIT INTEGRATED 32-CDIP
Datasheet ADADC80-12 Datasheet
Package 32-CDIP (0.910", 23.12mm)
In Stock 3308 piece(s)
Unit Price $ 308.81 *
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ADADC80-12

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ADADC80-12 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet ADADC80-12 Datasheet
Package32-CDIP (0.910", 23.12mm)
Series-
Number of Bits12
Number of Inputs2
Input TypeSingle Ended
Data InterfaceParallel
ConfigurationADC
Number of A/D Converters1
ArchitectureSAR
Reference TypeInternal
Voltage - Supply, Analog��15V
Voltage - Supply, Digital5V
Operating Temperature-25°C ~ 85°C
Package / Case32-CDIP (0.910", 23.12mm)
Supplier Device Package32-CDIP Side Brazed

ADADC80-12 Datasheet

Page 1

Page 2

12-Bit Successive-Approximation Integrated Circuit ADC ADADC80 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved. FEATURES True 12-bit operation: maximum nonlinearity ±0.012% Low gain temperature coefficient (TC): ±30 ppm/°C maximum Low power: 800 mW Fast conversion time: 25 μs Precision 6.3 V reference for external application Short-cycle capability Parallel data output Monolithic DAC with scaling resistors for stability Low chip count, high reliability Industry-standard pin configuration “Z” models for ±12 V supplies FUNCTIONAL BLOCK DIAGRAM 1 32 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 (LSB)BIT 1 (MSB) BIT 1 (MSB) DIGITAL GND 10V SPAN IN 20V SPAN IN ANALOG GND GAIN ADJUST NC 5V DIGITAL SUPPLY COMPARATOR IN BIPOLAR OFFSET OUT NC –15V OR –12V STATUS REF OUT (6.3V) CLOCK OUT SHORT CYCLE CLOCK INHIBIT 15V OR 12V EXTERNAL CLOCK IN CONVERT START ADADC80 12-BIT SAR 12-BIT DAC CLOCK AND CONTROL CIRCUITS REFERENCE COMP NC = NO CONNECT 01 2 02 -0 0 1 Figure 1. PRODUCT DESCRIPTION The ADADC801 is a complete 12-bit successive-approximation analog-to-digital converter (ADC) that includes an internal clock, reference, and comparator. Its hybrid IC design uses MSI digital and linear monolithic chips in conjunction with a 12-bit monolithic digital-to-analog converter (DAC) to provide modular performance and versatility with IC size, price, and reliability. Important performance characteristics of the ADADC80 include a maximum linearity error of ±0.012% at 25°C, maximum gain TC of 30 ppm/°C, typical power dissipation of 800 mW, and maximum conversion time of 25 μs. Monotonic operation of the feedback DAC guarantees no missing codes over the temperature range of −25°C to +85°C. The design of the ADADC80 includes scaling resistors that provide an analog signal range of ±2.5 V, ±5.0 V, ±10 V, 0 V to +5.0 V, or 0 V to +10.0 V. The 6.3 V precision reference can be used for external applications. All digital signals are fully DTL and TTL compatible; output data is in parallel form. The ADADC80 is available in grades specified for use over the −25°C to +85°C temperature range and is available in a 32-lead ceramic DIP. 1 The serial output function is no longer supported on this product after Date Code 9616. PRODUCT HIGHLIGHTS 1. The ADADC80 is a complete 12-bit ADC. No external components are required to perform a conversion. 2. A monolithic 12-bit feedback DAC is used for reduced chip count and higher reliability. 3. The internal buried Zener reference is laser trimmed to 6.3 V. The reference voltage is available externally and can supply up to 1.5 mA beyond the current required for the reference and bipolar offset. 4. The scaling resistors are included on the monolithic DAC for exceptional thermal tracking. 5. The ADADC80 directly replaces other devices of this type, providing significant increases in performance. 6. The fast conversion rate of the ADADC80 makes it an excellent choice for applications requiring high system throughput rates. 7. The short cycle and external clock options are provided for applications requiring faster conversion speed or lower resolution.

Page 3

ADADC80 Rev. E | Page 2 of 16 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 Product Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 8 Timing ............................................................................................8 Digital Output Data ......................................................................9 Input Scaling ..................................................................................9 Offset Adjustment ...................................................................... 10 Gain Adjustment ........................................................................ 10 Calibration ................................................................................... 11 Grounding ................................................................................... 12 Control Modes ............................................................................ 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 REVISION HISTORY 2/08—Rev. D to Rev. E Updated Format .................................................................. Universal Pin 7 Changed to NC ......................................................... Universal Changes to Specifications Section .................................................. 3 Added Absolute Maximum Ratings Section ................................. 5 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 8/03—Rev. C to Rev. D Changes to Specifications ................................................................. 2 4/03—Rev. B to Rev. C Changes to General Description ..................................................... 1 9/02—Rev. A to Rev. B Changes to Figure 1 ........................................................................... 6 Updated Outline Dimensions ....................................................... 11

Page 4

ADADC80 Rev. E | Page 3 of 16 SPECIFICATIONS Typical @ 25°C, ±15 V, and +5 V, unless otherwise noted. Table 1. Parameter Min Typ Max Unit RESOLUTION 12 Bits ANALOG INPUTS Voltage Ranges Bipolar ±2.5 or ±5 or ±10 V Unipolar 0 to +5 or 0 to +10 V Impedance (Direct Input) 0 to +5, ±2.5 V 2.5 kΩ 0 to +10, ±5 V 5 kΩ ±10 V 10 kΩ DIGITAL INPUTS1 Positive Pulse During Conversion (CONVERT START) 100 ns Logic Loading 1 TTL load External Clock (EXTERNAL CLOCK IN) 1 TTL load TRANSFER CHARACTERISTICS ERROR Gain Error2 ±0.1 % of FSR3 Offset2 Bipolar ±0.1 % of FSR Unipolar ±0.05 % of FSR Linearity Error4 ±0.012 % of FSR Inherent Quantization Error ±½ LSB Differential Linearity Error ±½ LSB No Missing Codes Temperature Range −25 +85 °C Power Supply Sensitivity ±15 V ±0.0030 % of FSR/% VS +5 V ±0.0015 % of FSR/% VS DRIFT Specification Temperature Range5 −25 +85 °C Gain ±30 ppm/°C Offset Bipolar ±15 ppm of FSR/°C Unipolar ±3 ppm of FSR/°C Linearity ±3 ppm of FSR/°C Monotonicity Guaranteed CONVERSION SPEED6 17 22 25 μs DIGITAL OUTPUTS (ALL CODES COMPLEMENTARY) Parallel, BIT 1 (MSB) to BIT 12 (LSB) Output Codes7 Bipolar COB, CTC Unipolar CSB Output Drive 2 TTL loads Status (STATUS) Logic 1 during conversion Status Output Drive 2 TTL loads Internal Clock (CLOCK OUT) Clock Output Drive 2 TTL loads Frequency8 575 kHz

Page 5

ADADC80 Rev. E | Page 4 of 16 Parameter Min Typ Max Unit INTERNAL REFERENCE VOLTAGE +6.3 V ±10 ± mV Maximum External Current (With No Degradation of Specifications) 1.5 mA Temperature Coefficient of Drift5 ±10 ±20 ppm/°C POWER REQUIREMENTS Rated Voltages ±15, +5 V Range for Rated Accuracy5 +5 V +4.75 +5.25 V ±15 V ±14.0 ±16.0 V “Z” Models5, 9 +5 V +4.75 +5.25 V ±15 V ±11.4 ±16.0 V Supply Drain +15 V +10 mA −15 V −20 mA +5 V +70 mA TEMPERATURE RANGE Specification −25 +85 °C Operating (Derated Specifications) −55 +100 °C Storage −55 +125 °C 1 DTL/TTL compatible, that is, Logic 0 = 0.8 V maximum and Logic 1 = 2.0 V minimum for digital inputs, Logic 0 = 0.4 V maximum and Logic 1 = 2.4 V minimum for digital outputs. 2 Adjustable to zero with external trimpots. 3 FSR means full-scale range, that is, unit connected for ±10 V range has +20 V FSR. 4 Error shown is the same as ±½ LSB maximum for resolution of analog-to-digital converter. 5 Guaranteed by design. Not production tested. 6 Conversion time with internal clock. 7 See Table 4. Complementary offset binary is COB, complementary straight binary is CSB, and complementary twos complement is CTC. 8 For conversion speeds specified. 9 For “Z” models, order ADADC80-Z-12.

Page 6

ADADC80 Rev. E | Page 5 of 16 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage ±18 V Logic Supply Voltage 7 V Analog Ground to Digital Ground ±0.3 V Analog Inputs (Pin 13, Pin 14) ±VS Digital Input −0.3 V to VDD + 0.3 V Junction Temperature 175°C Storage Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Page 7

ADADC80 Rev. E | Page 6 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC = NO CONNECT 32 31 30 29 28 27 26 25 24 23 22 21 20 19 15 16 18 17 BIT 5 BIT 4 BIT 3 NC BIT 1 (MSB) BIT 2 BIT 6 BIT 8 BIT 9 BIT 10 NC BIT 12 (LSB) BIT 11 BIT 1 (MSB) 5V DIGITAL SUPPLY DIGITAL GND 20V SPAN IN BIPOLAR OFFSET OUT COMPARATOR IN –15V OR –12V REF OUT (6.3V) CLOCK OUT EXTERNAL CLOCK IN 10V SPAN IN CLOCK INHIBIT GAIN ADJUST 15V OR 12V ANALOG GND CONVERT START SHORT CYCLE STATUS BIT 7 ADADC80 TOP VIEW (Not to Scale) 0 12 0 2- 00 2 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Function 1 to 6 BIT 6 to BIT 1 (MSB) Digital Outputs. 7 NC No Connection. 8 BIT 1 (MSB) MSB Inverted Digital Output. 9 5V DIGITAL SUPPLY Digital Positive Supply (Nominally ±0.25 V). 10 DIGITAL GND Digital Ground. 11 COMPARATOR IN Offset Adjust. 12 BIPOLAR OFFSET OUT Bipolar Offset Output. 13 10V SPAN IN Analog Input 10 V Signal Range. 14 20V SPAN IN Analog Input 20 V Signal Range. 15 ANALOG GND Analog Ground. 16 GAIN ADJUST Gain Adjust. 17 15V OR 12V Analog Positive Supply (Nominally ±1.0 V for +15 V or ±0.6 V for +12 V). 18 CONVERT START Enables Conversion. 19 EXTERNAL CLOCK IN External Clock Input. 20 CLOCK INHIBIT Clock Inhibit. 21 SHORT CYCLE Shortens Conversion Cycle to Desired Resolution. 22 STATUS Logic High, ADC Converting/Logic Low, ADC Data Valid. 23 CLOCK OUT Internal Clock Output. 24 REF OUT (6.3V) 6.3 V Reference Output. 25 −15V OR −12V Analog Negative Supply (Nominally ±1.0 V for −15 V or ±0.6 V for −12 V). 26 NC No Connection. 27 to 32 BIT 12 (LSB) to BIT 7 Digital Outputs.

Page 8

ADADC80 Rev. E | Page 7 of 16 01 20 2- 00 3 TYPICAL PERFORMANCE CHARACTERISTICS 1.00 0.50 0.75 0.25L IN E A R IT Y E R R O R ( L S B ) 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 CONVERSION TIME (µs) 10-BIT8-BIT 12-BIT Figure 3. Linearity Error vs. Conversion Time (Normalized) 01 20 2- 00 5–0.3 –25 0 25 70 85 TEMPERATURE (°C) 0.2 0.3 0.1 0 –0.1 –0.2 G A IN D R IF T E R R O R ( % O F F S R ) Figure 4. Gain Drift Error vs. Temperature 01 20 2 -0 0 4 0.75 1.00 0.50 0.25 0 D IF F E R E N T IA L L IN E A R IT Y E R R O R ( L S B ) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 CONVERSION TIME (µs) 8-BIT 10-BIT 12-BIT Figure 5. Differential Linearity Error vs. Conversion Time (Normalized) 0 1TEMPERATURE (°C) 2 02 -0 06 0.06 0.08 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 R E F E R E N C E D R IF T E R R O R ( % ) –55 –25 0 25 85 100 TYPICAL Figure 6. Reference Drift, Error vs. Temperature

Page 9

ADADC80 Rev. E | Page 8 of 16 01 20 2- 00 7 THEORY OF OPERATION Upon receipt of a CONVERT START command, the ADADC80 converts the voltage at its analog input into an equivalent 12-bit binary number. This conversion is accomplished as follows: 1. The 12-bit successive-approximation register (SAR) has its 12-bit outputs connected both to the device bit output pins and to the corresponding bit inputs of the feedback DAC. 2. The analog input is successively compared to the feedback DAC output, one bit at a time (MSB first, LSB last). 3. The decision to keep or reject each bit is then made at the completion of each bit comparison period, depending on the state of the comparator at that time. TIMING The timing diagram is shown in Figure 7. Receipt of a CONVERT START signal sets the STATUS flag, indicating that a conversion is in progress. This, in turn, removes the inhibit applied to the gated clock, permitting it to run through 13 cycles. All changes to the SAR parallel bit and to the STATUS bit are initialized on the leading edge, and the gated clock inhibit signal is removed on the trailing edge of the CONVERT START signal. At time t0, BIT 1 is reset and BIT 2 to BIT 12 are set unconditionally. At t1, the BIT 1 decision is made (keep) and BIT 2 is unconditionally reset. At t2, the BIT 2 decision is made (keep) and BIT 3 is reset unconditionally. This sequence continues until the BIT 12 (LSB) decision (keep) is made at t12. After a 40 ns delay period, the STATUS flag is reset, indicating that the conversion is complete and the parallel output data is valid. Resetting the STATUS flag restores the gated clock inhibit signal, forcing the clock output to the Logic 0 state. Parallel data bits become valid on the positive-going clock edge (see Figure 7). Incorporation of this 40 ns delay guarantees that the parallel data is valid at the Logic l to Logic 0 transition of the STATUS flag, permitting a parallel data transfer to be initiated by the trailing edge of the STATUS signal. MAXIMUM THROUGHPUT TIME CONVERT START1 INTERNAL CLOCK STATUS3 MSB BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 0 1 0 1 1 1 1 0 t0 t2t1 t4t3 t6t5 t8t7 t10t9 t12 t11 CONVERSION TIME2 BIT 9 BIT 10 BIT 11 LSB 0 1 1 0 * * * * * * * * * * NOTES 1THE CONVERT START PULSE WIDTH IS 100ns MINIMUM AND MUST REMAIN LOW DURING A CONVERSION. 1THE CONVERSION IS INITIATED BY THE RISING EDGE OF THE CONVERT COMMAND. 225µs FOR 12 BITS AND 21µs FOR 10 BITS (MAXIMUM). 3t1 SHOWS THE MSB DECISION AND t11 SHOWS THE LSB DECISION 40ns PRIOR TO THE STATUS GOING LOW. *BIT DECISIONS. Figure 7. Timing Diagram (Binary Code 011001110110)

Page 10

ADADC80 Rev. E | Page 9 of 16 DIGITAL OUTPUT DATA Parallel data from TTL storage registers is in negative true form. Parallel data output coding is complementary binary for unipolar ranges and either complementary offset binary or complementary twos complement binary for bipolar ranges, depending on whether BIT 1 (Pin 6) or its logical inverse BIT 1 (MSB) (Pin 8) is used as the MSB. Parallel data becomes valid approximately 40 ns before the STATUS flag returns to Logic 0, permitting parallel data transfer to be clocked on the 1 to 0 transition of the STATUS flag. Parallel data outputs change state on positive-going clock edges. There are 13 negative-going clock edges in the complete 12-bit conversion cycle, as shown in Figure 7. The first edge shifts an invalid bit into the register, which is shifted out on the 13th negative-going clock edge. SHORT CYCLE Input The SHORT CYCLE input (Pin 21) permits the timing cycle shown in Figure 7 to be terminated after any number of desired bits has been converted, allowing somewhat shorter conversion times in applications not requiring full 12-bit resolution. When 10-bit resolution is desired, Pin 21 is connected to the BIT 11 output (Pin 28). The conversion cycle then terminates, and the STATUS flag resets after the BIT 10 decision (t10 + 40 ns in timing diagram of Figure 7). Short cycle pin connections and associated maximum 12-, 10-, and 8-bit conversion times are summarized in Table 4. When 12-bit resolution is required, SHORT CYCLE (Pin 21) is connected to 5V DIGITAL SUPPLY (Pin 9). INPUT SCALING The ADADC80 input should be scaled as close to the maximum input signal range as possible to use the maximum signal resolution of the ADC. Connect the input signal as shown in Table 5. See Figure 8 for circuit details. BIPOLAR OFFSET OUT ANALOG GND R2 5kΩ R1 5kΩ 0 12 02 -0 08 FROM DAC TO SAR COMPARATOR 6.3kΩ VREF COMPARATOR IN 20V SPAN IN 10V SPAN IN 13 14 11 12 15 Figure 8. Input Scaling Circuit Table 4. Short Cycle Connections Connect SHORT CYCLE (Pin 21) to Resolution (Bits) (% FSR) Maximum Conversion Time (μs) STATUS Flag Reset 5V DIGITAL SUPPLY (Pin 9) 12 0.024 25 t12 + 40 ns BIT 11 (Pin 28) 10 0.100 21 t10 + 40 ns BIT 9 (Pin 30) 8 0.390 17 t8 + 40 ns Table 5. Input Scaling Connections Input Signal Range Output Code Connect BIPOLAR OFFSET OUT (Pin 12) to Connect 20V SPAN IN (Pin 14) to Connect Input Signal to ±10 V COB or CTC COMPARATOR IN (Pin 11) Input Signal 20V SPAN IN (Pin 14) ±5 V COB or CTC COMPARATOR IN (Pin 11) Open 10V SPAN IN (Pin 13) ±2.5 V COB or CTC COMPARATOR IN (Pin 11) COMPARATOR IN (Pin 11) 10V SPAN IN (Pin 13) 0 V to +5 V CSB ANALOG GND (Pin 15) COMPARATOR IN (Pin 11) 10V SPAN IN (Pin 13) 0 V to +10 V CSB ANALOG GND (Pin 15) Open 10V SPAN IN (Pin 13)

ADADC80-12 Reviews

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Marc*****rant

January 6, 2020

2nd time buying these - quite good. Very fast shipping

Arel*****drade

December 31, 2020

There are cheaper ones out there but this one really take the guessing game out.

Kin*****ssac

November 25, 2019

I had no problems with this product. Would I recommend it. Yes.

Cann*****iles

November 21, 2019

Wish there were some documentation but I guess if you're buying you kinda should know.

Izaia*****dward

November 17, 2019

Great deal, immediate response and very quick delivery!

Feli*****hacko

November 9, 2019

A well designed product that fit my custom PCB's perfectly. Easy to use. Sturdy construction. Highly recommend to all PCB builders.

Juel*****nson

July 15, 2019

DELIVERY AND COMMUNICATION EXTRA SELLER TOP 5 STARS on my list

Domin*****ncock

June 13, 2019

Thanks a lot! Ease of ordering and I love when they upgrade my shipping for free. What a nice thing to do.

Mik*****ain

June 3, 2019

Very pleased with the parts from this company. First class service. Thanks!

Alice*****andez

May 6, 2019

Great Seller, Great Item, the quality is great, Highly Recommended.

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