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ADAU1381BCBZ-RL7

hotADAU1381BCBZ-RL7

ADAU1381BCBZ-RL7

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Part Number ADAU1381BCBZ-RL7
Manufacturer Analog Devices Inc.
Description IC AUDIO CODEC STEREO LN 30WLCSP
Datasheet ADAU1381BCBZ-RL7 Datasheet
Package 30-UFBGA, WLCSP
In Stock 2,400 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Nov 27 - Dec 2 (Choose Expedited Shipping)
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Part Number # ADAU1381BCBZ-RL7 (Interface - CODECs) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADAU1381BCBZ-RL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - CODECs
Datasheet ADAU1381BCBZ-RL7Datasheet
Package30-UFBGA, WLCSP
Series-
TypeStereo Audio
Data InterfaceSPI
Resolution (Bits)24 b
Number of ADCs / DACs2 / 2
Sigma DeltaNo
S/N Ratio, ADCs / DACs (db) Typ97 / 100
Dynamic Range, ADCs / DACs (db) Typ96.5 / 100
Voltage - Supply, Analog1.8 V ~ 3.65 V
Voltage - Supply, Digital1.63 V ~ 3.65 V
Operating Temperature-25°C ~ 85°C
Mounting TypeSurface Mount
Package / Case30-UFBGA, WLCSP
Supplier Device Package30-WLCSP (3.4x2.64)

ADAU1381BCBZ-RL7 Datasheet

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Low Noise Stereo Codec with Enhanced Recording and Playback Processing ADAU1381 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved. FEATURES 24-bit stereo audio ADC and DAC 400 mW speaker amplifier (into 8 Ω load) Built-in sound engine for audio processing Wind noise detection and autofiltering Enhanced stereo capture (ESC) Dual-band automatic level control (ALC) 6-band equalizer, including notch filter Sampling rates from 8 kHz to 96 kHz Stereo pseudo differential microphone input Optional stereo digital microphone input pulse-density modulation (PDM) Stereo line output PLL supporting a range of input clock rates Analog and digital I/O 1.8 V to 3.3 V Software control via SigmaStudio graphical user interface Software-controllable, clickless mute Software register and hardware pin standby mode 32-lead, 5 mm × 5 mm LFCSP or 30-ball, 6 × 5 bump WLCSP APPLICATIONS Digital still cameras Digital video cameras GENERAL DESCRIPTION The ADAU1381 is a low power, 24-bit stereo audio codec. The low noise DAC and ADC support sample rates from 8 kHz to 96 kHz. Low current draw and power saving modes make the ADAU1381 ideal for battery-powered audio applications. A configurable sound engine provides enhanced record and playback processing to improve overall audio quality. The record path includes two digital stereo microphone inputs and an analog stereo input path. The analog inputs can be configured for either a pseudo differential or a single-ended stereo source. A dedicated analog beep input signal can be mixed into any output path. The ADAU1381 includes a stereo line output and speaker driver, which makes the device capable of supporting dynamic speakers. The serial control bus supports the I2C® or SPI protocols, and the serial audio bus is programmable for I2S, left-justified, right- justified, or TDM mode. A programmable PLL supports flexible clock generation for all standard rates and available master clocks from 11 MHz to 20 MHz. FUNCTIONAL BLOCK DIAGRAM PGA PGA LEFTADC RIGHT ADC LEFT DAC RIGHT DAC PGA BEEP PDN MICBIAS LMIC/LMICN/ MICD1 LMICP RMIC/RMICN/ MICD2 RMICP AOUTL AOUTR SPP SPN PLL SOUND ENGINE DECIMATION FILTERS WIND NOISE NOTCH FILTER EQUALIZER DIGITAL VOLUME CONTROL AUTOMATIC LEVEL CONTROL OUTPUT MIXER M C K I REGULATOR C M IO V D D D G N D D V D D O U T A V D D 1 A G N D 1 A V D D 2 A G N D 2 SERIAL DATA INPUT/OUTPUT PORTS A D C _S D A T A / G P IO 1 B C L K /G P IO 2 L R C L K /G P IO 3 D A C _S D A T A / G P IO 0 I2C/SPI CONTROL PORT A D D R 0/ C D A T A A D D R 1/ C L A T C H S C L /C C L K S D A /C O U T ADAU1381 MICROPHONE BIAS 0 83 13 -0 01 Figure 1.

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ADAU1381 Rev. B | Page 2 of 84 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Record Side Performance Specifications................................... 4 Output Side Performance Specifications................................... 6 Power Supply Specifications........................................................ 8 Typical Power Management Measurements ............................. 9 Digital Filters................................................................................. 9 Digital Input/Output Specifications......................................... 10 Digital Timing Specifications ................................................... 11 Absolute Maximum Ratings.......................................................... 14 Thermal Resistance .................................................................... 14 ESD Caution................................................................................ 14 Pin Configuration and Function Descriptions........................... 15 Typical Performance Characteristics ........................................... 17 System Block Diagrams ................................................................. 20 Theory of Operation ...................................................................... 24 Startup, Initialization, and Power ................................................. 25 Power-Up Sequence ................................................................... 25 Clock Generation and Management........................................ 26 Enabling Digital Power to Functional Subsystems ................ 26 Setting Up the Sound Engine.................................................... 26 Power Reduction Modes............................................................ 26 Power-Down Sequence.............................................................. 26 Clocking and Sampling Rates ....................................................... 27 Core Clock................................................................................... 27 Sampling Rates............................................................................ 27 PLL ............................................................................................... 28 Record Signal Path.......................................................................... 30 Input Signal Path ........................................................................ 30 Analog-to-Digital Converters................................................... 31 Digital Dual-Band Automatic Level Control (ALC) ............. 31 Playback Signal Path ...................................................................... 32 Output Signal Paths ................................................................... 32 Digital-to-Analog Converters................................................... 32 Line Outputs ............................................................................... 32 Speaker Output........................................................................... 32 Control Ports................................................................................... 33 I2C Port ........................................................................................ 33 SPI Port ........................................................................................ 36 Memory and Register Access.................................................... 36 Serial Data Input/Output Ports .................................................... 38 TDM Modes................................................................................ 38 General-Purpose Input/Outputs .................................................. 40 Sound Engine.................................................................................. 41 Signal Processing........................................................................ 41 Processing Flow .......................................................................... 41 Programming.............................................................................. 41 Parameter Memory .................................................................... 41 Applications Information .............................................................. 42 Power Supply Bypass Capacitors.............................................. 42 GSM Noise Filter ........................................................................ 42 Grounding ................................................................................... 42 Speaker Driver Supply Trace (AVDD2) .................................. 42 Exposed Pad PCB Design ......................................................... 42 Control Register Map..................................................................... 43 Clock Management, Internal Regulator, and PLL Control... 44 Record Path Configuration....................................................... 48 Serial Port Configuration.......................................................... 53 Audio Converter Configuration............................................... 58 Playback Path Configuration.................................................... 63

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ADAU1381 Rev. B | Page 3 of 84 Pad Configuration.......................................................................70 Digital Subsystem Configuration..............................................77 Outline Dimensions........................................................................84 Ordering Guide ...........................................................................84 REVISION HISTORY 1/11—Rev. A to Rev. B Changes to Pin PDN Description in Table 10 .............................16 Changes to Power-Down Pin (PDN) Section..............................26 Changes to Table 23 ........................................................................36 3/10—Rev. 0 to Rev. A Changes to Output Side Performance Specifications Section Condition Statement.....................................................................6 Added Endnote 1 to Table 3.............................................................8 Changes to Figure 23 ......................................................................20 Changes to Figure 24 ......................................................................21 Changes to Figure 25 ......................................................................22 Changes to Figure 26 ......................................................................23 Changes to Table 27 ........................................................................43 Added Register 16434 (0x4032), Dejitter Control Section........76 Changes to Ordering Guide...........................................................84 10/09—Revision 0: Initial Version

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ADAU1381 Rev. B | Page 4 of 84 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; temperature = 25°C; master clock (MCLK) = 12.288 MHz (fS = 48 kHz, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width = 24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = 2 mA; high level input voltage = 0.7 × IOVDD; and low level input voltage = 0.3 × IOVDD. All power management registers are set to their default states. RECORD SIDE PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS ADC Resolution All ADCs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB INPUT RESISTANCE Noninverting Inputs PGA (LMICP, RMICP) All gain settings 500 kΩ Inverting Inputs PGA (LMICN, RMICN) 0 dB gain 62 kΩ 6 dB gain 32 kΩ 10 dB gain 22 kΩ 14 dB gain 14 kΩ 17 dB gain 10 kΩ 20 dB gain 8 kΩ 26 dB gain 5 kΩ 32 dB gain 4 kΩ Beep Input PGA 0 dB 20 kΩ 6 dB 9 kΩ 10 dB 6 kΩ 14 dB 3.5 kΩ −23 dB 50 kΩ 20 dB 2 kΩ 26 dB 2 kΩ 32 dB 2 kΩ SINGLE-ENDED MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 94 99.2 dB No Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 92 96.5 dB Total Harmonic Distortion + Noise −3 dBFS AVDD = 1.8 V −88 dB AVDD = 3.3 V −90 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 100 dB No Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 97 dB

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ADAU1381 Rev. B | Page 5 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Left/Right Microphone PGA Gain Range AVDD = 3.3 V 0 32 dB Left/Right Microphone PGA Mute Attenuation AVDD = 3.3 V; mute set by Register 0x400E, Bit 1, and Register 0x400F, Bit 1 −98 dB Interchannel Gain Mismatch AVDD = 3.3 V 50 mdB Offset Error AVDD = 3.3 V 0.25 mV Gain Error AVDD = 3.3 V −1 % Interchannel Isolation AVDD = 3.3 V −98 dB Power Supply Rejection Ratio CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz −55 dB AVDD = 3.3 V, 100 mV p-p at 1 kHz −55 dB DIFFERENTIAL MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 94 99.2 dB No Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 92 96.5 dB Total Harmonic Distortion + Noise −3 dBFS AVDD = 1.8 V −84 dB AVDD = 3.3 V −85 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 100 dB No Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 97 dB Left/Right Microphone PGA Mute Attenuation AVDD = 3.3 V; mute set by Register 0x400E, Bit 1, and Register 0x400F, Bit 1 −98 dB Interchannel Gain Mismatch AVDD = 3.3 V 50 mdB Offset Error AVDD = 3.3 V 0.25 mV Gain Error AVDD = 3.3 V −1 % Interchannel Isolation AVDD = 3.3 V −85 dB Common-Mode Rejection Ratio AVDD = 3.3 V, 100 mV rms, 1 kHz −60 dB AVDD = 3.3 V, 100 mV rms, 20 kHz −45 dB BEEP TO LINE OUTPUT PATH Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Total Harmonic Distortion + Noise −3 dBFS input, measured at AOUTL pin, beep gain set to 0 dB AVDD = 1.8 V −88 dB AVDD = 3.3 V −88 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 99 dB AVDD = 3.3 V 105 dB No Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 102 dB

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ADAU1381 Rev. B | Page 6 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 99 dB AVDD = 3.3 V 105 dB No Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 102 dB Beep Input Mute Attenuation AVDD = 3.3 V; mute set by Register 0x4008, Bit 3 −90 dB Offset Error AVDD = 3.3 V 10 mV Gain Error AVDD = 3.3 V −0.3 dB Interchannel Gain Mismatch 30 mdB Beep Input PGA Gain Range AVDD = 3.3 V −23 +32 dB Beep Playback Mixer Gain Range AVDD = 3.3 V −15 +6 dB Power Supply Rejection Ratio CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz −58 dB AVDD = 3.3 V, 100 mV p-p at 1 kHz −72 dB MICROPHONE BIAS Microphone bias enabled Bias Voltage 0.65 × AVDD AVDD = 1.8 V, low bias 1.17 V AVDD = 3.3 V, low bias 2.145 V 0.90 × AVDD AVDD = 1.8 V, high bias 1.62 V AVDD = 3.3 V, high bias 2.97 V Bias Current Source AVDD = 3.3 V, high bias, high performance 5 mA Noise in the Signal Bandwidth AVDD = 3.3 V, 20 Hz to 20 kHz High bias, high performance 39 nV√Hz High bias, low performance 78 nV√Hz Low bias, high performance 25 nV√Hz Low bias, low performance 35 nV√Hz AVDD = 1.8 V, 20 Hz to 20 kHz High bias, high performance 35 nV√Hz High bias, low performance 45 nV√Hz Low bias, high performance 23 nV√Hz Low bias, low performance 23 nV√Hz OUTPUT SIDE PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). The output load for the speaker output path is an 8 Ω, 400 mW speaker. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL-TO-ANALOG CONVERTERS DAC Resolution All DACs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB DAC TO LINE OUTPUT PATH Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Line Output Mute Attenuation, DAC to Mixer Path Muted AVDD = 3.3 V; mute set by Register 0x401C, Bit 5, and Register 0x401E, Bit 6 −85 dB Line Output Mute Attenuation, Line Output Muted AVDD = 3.3 V; mute set by Register 0x4025, Bit 1, and Register 0x4026, Bit 1 −85 dB

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ADAU1381 Rev. B | Page 7 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 99 dB AVDD = 3.3 V 94 103 dB No Filter (RMS) AVDD = 1.8 V 97 dB AVDD = 3.3 V 92 100 dB Total Harmonic Distortion + Noise −3 dBFS dB AVDD = 1.8 V −88 dB AVDD = 3.3 V −88 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 99 dB AVDD = 3.3 V 103 dB No Filter (RMS) AVDD = 1.8 V 97 dB AVDD = 3.3 V 100 dB Power Supply Rejection Ratio CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz −55 dB AVDD = 3.3 V, 100 mV p-p at 1 kHz −63 dB Gain Error AVDD = 3.3 V −1 dB Interchannel Gain Mismatch AVDD = 3.3 V 50 mdB Offset Error AVDD = 3.3 V 10 mV DAC TO SPEAKER OUTPUT PATH PO = output power Differential Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/1.65 V rms AVDD = 1.8 V 1.1 (3.12) V rms (V p-p) AVDD = 3.3 V 2.0 (5.66) V rms (V p-p) Total Harmonic Distortion + Noise 4 Ω Load AVDD = 1.8 V, PO = 50 mW −60 dB AVDD = 3.3 V, PO = 175 mW −60 dB 8 Ω Load AVDD = 1.8 V, PO = 50 mW −60 dB AVDD = 3.3 V, PO = 175 mW −60 dB AVDD = 3.3 V, PO = 330 mW −60 dB AVDD = 3.3 V, PO = 440 mW −16 dB Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 100 dB AVDD = 3.3 V 94 105 dB No Filter (RMS) AVDD = 1.8 V 98 dB AVDD = 3.3 V 92 103 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 100 dB AVDD = 3.3 V 105 dB No Filter (RMS) AVDD = 1.8 V 98 dB AVDD = 3.3 V 103 dB Power Supply Rejection Ratio CM capacitor = 10 μF AVDD = 3.3 V,100 mV p-p at 217 Hz −55 dB AVDD = 3.3 V, 100 mV p-p at 1 kHz −55 dB Differential Offset Error AVDD = 3.3 V 2 mV Mono Mixer Mute Attenuation, DAC to Mixer Path Muted Mute set by Register 0x401F, Bit 0 −90 dB BEEP TO SPEAKER OUTPUT PATH PO = output power Differential Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/1.65 V rms AVDD = 1.8 V 1.1 (3.12) V rms (V p-p) AVDD = 3.3 V 2.0 (5.66) V rms (V p-p)

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ADAU1381 Rev. B | Page 8 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Total Harmonic Distortion + Noise 8 Ω, 1 nF load, AVDD = 1.8 V, PO = 50 mW −60 dB AVDD = 3.3 V, PO = 175 mW −60 dB Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 97 dB AVDD = 3.3 V 103 dB No Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 100 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 98 dB AVDD = 3.3 V 103 dB No Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 101 dB Power Supply Rejection Ratio CM capacitor = 10 μF 100 mV p-p at 217 Hz −57 dB 100 mV p-p at 1 kHz −60 dB Differential Offset Error 2 mV Mono Mixer Mute Attenuation, Beep to Mixer Path Muted Mute set by Register 0x401F, Bit 0 −90 dB REFERENCE (CM PIN) Common-Mode Reference Output AVDD/2 V POWER SUPPLY SPECIFICATIONS AVDD1 and AVDD2 must always be equal. Power supply measurements are taken with the sound engine processing path enabled. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit AVDD1, AVDD2 1.81 3.3 3.65 V IOVDD 1.63 3.3 3.65 V Digital I/O Current (IOVDD = 3.3 V) 20 pF capacitive load on all digital pins Slave Mode, Analog I/O, 12.288 MHz External MCLK Input fS = 48 kHz 0.20 mA fS = 96 kHz 0.35 mA fS = 8 kHz 0.04 mA Master Mode, MCKO Disabled fS = 48 kHz 1.25 mA fS = 96 kHz 2.50 mA fS = 8 kHz 0.22 mA Digital I/O Current (IOVDD = 1.8 V) 20 pF capacitive load on all digital pins Slave Mode, Analog I/O, 12.288 MHz External MCLK Input fS = 48 kHz 0.10 mA fS = 96 kHz 0.18 mA fS = 8 kHz 0.02 mA Master Mode, MCKO Disabled fS = 48 kHz 0.68 mA fS = 96 kHz 1.33 mA fS = 8 kHz 0.12 mA Analog Current (AVDD) See Table 4 1 The zero-cross detection of the beep path is not supported at AVDD1, AVDD2 < 2.2 V.

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ADAU1381 Rev. B | Page 9 of 84 TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, PLL is active in integer mode at a 256 × fS input rate for fS = 48 kHz, analog and digital input tones are −1 dBFS with a frequency of 1 kHz. Analog input and output are simultaneously active. Pseudo differential stereo input is routed to ADCs, and DACs are routed to stereo line output with a 16 kΩ load. ADC input at −1 dBFS, DAC input at 0 dBFS. The speaker output is disabled. The serial port is configured in slave mode. The beep path is disabled. The sound engine processing path is enabled. Current measurements are given in units of mA rms. Table 4. Mixer Boost and Power Management Conditions Operating Voltage Power Management Mode1 Mixer Boost Mode2 Typical AVDD Current Consumption (mA) Typical ADC THD + N (dB) Typical Line Output THD + N (dB) AVDD = IOVDD = 3.3 V Normal (default) Normal operation 16.84 88.5 93.0 Boost Level 1 16.88 88.5 93.0 Boost Level 2 16.92 88.5 93.0 Boost Level 3 17.00 88.5 93.0 Extreme power saving Normal operation 15.66 88.0 87.5 Boost Level 1 15.68 88.0 87.5 Boost Level 2 15.70 88.0 87.5 Boost Level 3 15.75 88.0 87.5 Enhanced performance Normal operation 17.43 88.5 94.5 Boost Level 1 17.50 88.5 94.5 Boost Level 2 17.53 88.5 94.5 Boost Level 3 17.63 88.5 94.5 Power saving Normal operation 16.25 89.0 90.5 Boost Level 1 16.28 89.0 90.5 Boost Level 2 16.31 89.0 90.5 Boost Level 3 16.38 89.0 90.5 AVDD = IOVDD = 1.8 V Normal (default) Normal operation 15.15 88.5 89.5 Boost Level 1 15.19 88.5 89.5 Boost Level 2 15.23 88.5 89.5 Boost Level 3 15.30 88.5 89.5 Extreme power saving Normal operation 14.03 86.5 85.5 Boost Level 1 14.05 86.5 85.5 Boost Level 2 14.07 86.5 85.5 Boost Level 3 14.12 86.5 85.5 Enhanced performance Normal operation 15.71 88.5 90.5 Boost Level 1 15.76 88.5 90.5 Boost Level 2 15.81 88.5 90.5 Boost Level 3 15.89 88.5 90.5 Power saving Normal operation 14.59 88.0 88.0 Boost Level 1 14.62 88.0 88.0 Boost Level 2 14.65 88.0 88.0 Boost Level 3 14.71 88.0 88.0 1 Set by Register 0x4009, Bits[4:1], and Register 0x4029, Bits[5:2]. 2 Set by Register 0x4009, Bits[6:5]. DIGITAL FILTERS Table 5. Parameter Mode Factor Min Typ Max Unit ADC DECIMATION FILTER All modes, typ value is for 48 kHz Pass Band 0.4375 × fS 21 kHz Pass-Band Ripple ±0.015 dB Transition Band 0.5 × fS 24 kHz Stop Band 0.5625 × fS 27 kHz Stop-Band Attenuation 70 dB Group Delay 22.9844/fS 479 μs

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